1 /* 2 * (C) Copyright 2013 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <fdtdec.h> 10 #include <libfdt.h> 11 #include <dwmmc.h> 12 #include <errno.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clock_manager.h> 15 #include <asm/arch/system_manager.h> 16 17 static const struct socfpga_clock_manager *clock_manager_base = 18 (void *)SOCFPGA_CLKMGR_ADDRESS; 19 static const struct socfpga_system_manager *system_manager_base = 20 (void *)SOCFPGA_SYSMGR_ADDRESS; 21 22 static void socfpga_dwmci_clksel(struct dwmci_host *host) 23 { 24 unsigned int drvsel; 25 unsigned int smplsel; 26 27 /* Disable SDMMC clock. */ 28 clrbits_le32(&clock_manager_base->per_pll.en, 29 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); 30 31 /* Configures drv_sel and smpl_sel */ 32 drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; 33 smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; 34 35 debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); 36 writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), 37 &system_manager_base->sdmmcgrp_ctrl); 38 39 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, 40 readl(&system_manager_base->sdmmcgrp_ctrl)); 41 42 /* Enable SDMMC clock */ 43 setbits_le32(&clock_manager_base->per_pll.en, 44 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); 45 } 46 47 static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) 48 { 49 /* FIXME: probe from DT eventually too/ */ 50 const unsigned long clk = cm_get_mmc_controller_clk_hz(); 51 52 struct dwmci_host *host; 53 fdt_addr_t reg_base; 54 int bus_width, fifo_depth; 55 56 if (clk == 0) { 57 printf("DWMMC%d: MMC clock is zero!", idx); 58 return -EINVAL; 59 } 60 61 /* Get the register address from the device node */ 62 reg_base = fdtdec_get_addr(blob, node, "reg"); 63 if (!reg_base) { 64 printf("DWMMC%d: Can't get base address\n", idx); 65 return -EINVAL; 66 } 67 68 /* Get the bus width from the device node */ 69 bus_width = fdtdec_get_int(blob, node, "bus-width", 0); 70 if (bus_width <= 0) { 71 printf("DWMMC%d: Can't get bus-width\n", idx); 72 return -EINVAL; 73 } 74 75 fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0); 76 if (fifo_depth < 0) { 77 printf("DWMMC%d: Can't get FIFO depth\n", idx); 78 return -EINVAL; 79 } 80 81 /* Allocate the host */ 82 host = calloc(1, sizeof(*host)); 83 if (!host) 84 return -ENOMEM; 85 86 host->name = "SOCFPGA DWMMC"; 87 host->ioaddr = (void *)reg_base; 88 host->buswidth = bus_width; 89 host->clksel = socfpga_dwmci_clksel; 90 host->dev_index = idx; 91 /* Fixed clock divide by 4 which due to the SDMMC wrapper */ 92 host->bus_hz = clk; 93 host->fifoth_val = MSIZE(0x2) | 94 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); 95 96 return add_dwmci(host, host->bus_hz, 400000); 97 } 98 99 static int socfpga_dwmci_process_node(const void *blob, int nodes[], 100 int count) 101 { 102 int i, node, ret; 103 104 for (i = 0; i < count; i++) { 105 node = nodes[i]; 106 if (node <= 0) 107 continue; 108 109 ret = socfpga_dwmci_of_probe(blob, node, i); 110 if (ret) { 111 printf("%s: failed to decode dev %d\n", __func__, i); 112 return ret; 113 } 114 } 115 return 0; 116 } 117 118 int socfpga_dwmmc_init(const void *blob) 119 { 120 int nodes[2]; /* Max. two controllers. */ 121 int ret, count; 122 123 count = fdtdec_find_aliases_for_id(blob, "mmc", 124 COMPAT_ALTERA_SOCFPGA_DWMMC, 125 nodes, ARRAY_SIZE(nodes)); 126 127 ret = socfpga_dwmci_process_node(blob, nodes, count); 128 129 return ret; 130 } 131