1 /* 2 * (C) Copyright 2013 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <fdtdec.h> 10 #include <libfdt.h> 11 #include <dwmmc.h> 12 #include <errno.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clock_manager.h> 15 #include <asm/arch/system_manager.h> 16 17 static const struct socfpga_clock_manager *clock_manager_base = 18 (void *)SOCFPGA_CLKMGR_ADDRESS; 19 static const struct socfpga_system_manager *system_manager_base = 20 (void *)SOCFPGA_SYSMGR_ADDRESS; 21 22 /* socfpga implmentation specific drver private data */ 23 struct dwmci_socfpga_priv_data { 24 unsigned int drvsel; 25 unsigned int smplsel; 26 }; 27 28 static void socfpga_dwmci_clksel(struct dwmci_host *host) 29 { 30 struct dwmci_socfpga_priv_data *priv = host->priv; 31 32 /* Disable SDMMC clock. */ 33 clrbits_le32(&clock_manager_base->per_pll.en, 34 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); 35 36 debug("%s: drvsel %d smplsel %d\n", __func__, 37 priv->drvsel, priv->smplsel); 38 writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel), 39 &system_manager_base->sdmmcgrp_ctrl); 40 41 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, 42 readl(&system_manager_base->sdmmcgrp_ctrl)); 43 44 /* Enable SDMMC clock */ 45 setbits_le32(&clock_manager_base->per_pll.en, 46 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); 47 } 48 49 static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) 50 { 51 /* FIXME: probe from DT eventually too/ */ 52 const unsigned long clk = cm_get_mmc_controller_clk_hz(); 53 54 struct dwmci_host *host; 55 struct dwmci_socfpga_priv_data *priv; 56 fdt_addr_t reg_base; 57 int bus_width, fifo_depth; 58 59 if (clk == 0) { 60 printf("DWMMC%d: MMC clock is zero!", idx); 61 return -EINVAL; 62 } 63 64 /* Get the register address from the device node */ 65 reg_base = fdtdec_get_addr(blob, node, "reg"); 66 if (!reg_base) { 67 printf("DWMMC%d: Can't get base address\n", idx); 68 return -EINVAL; 69 } 70 71 /* Get the bus width from the device node */ 72 bus_width = fdtdec_get_int(blob, node, "bus-width", 0); 73 if (bus_width <= 0) { 74 printf("DWMMC%d: Can't get bus-width\n", idx); 75 return -EINVAL; 76 } 77 78 fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0); 79 if (fifo_depth < 0) { 80 printf("DWMMC%d: Can't get FIFO depth\n", idx); 81 return -EINVAL; 82 } 83 84 /* Allocate the host */ 85 host = calloc(1, sizeof(*host)); 86 if (!host) 87 return -ENOMEM; 88 89 /* Allocate the priv */ 90 priv = calloc(1, sizeof(*priv)); 91 if (!priv) { 92 free(host); 93 return -ENOMEM; 94 } 95 96 host->name = "SOCFPGA DWMMC"; 97 host->ioaddr = (void *)reg_base; 98 host->buswidth = bus_width; 99 host->clksel = socfpga_dwmci_clksel; 100 host->dev_index = idx; 101 /* Fixed clock divide by 4 which due to the SDMMC wrapper */ 102 host->bus_hz = clk; 103 host->fifoth_val = MSIZE(0x2) | 104 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); 105 priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3); 106 priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0); 107 host->priv = priv; 108 109 return add_dwmci(host, host->bus_hz, 400000); 110 } 111 112 static int socfpga_dwmci_process_node(const void *blob, int nodes[], 113 int count) 114 { 115 int i, node, ret; 116 117 for (i = 0; i < count; i++) { 118 node = nodes[i]; 119 if (node <= 0) 120 continue; 121 122 ret = socfpga_dwmci_of_probe(blob, node, i); 123 if (ret) { 124 printf("%s: failed to decode dev %d\n", __func__, i); 125 return ret; 126 } 127 } 128 return 0; 129 } 130 131 int socfpga_dwmmc_init(const void *blob) 132 { 133 int nodes[2]; /* Max. two controllers. */ 134 int ret, count; 135 136 count = fdtdec_find_aliases_for_id(blob, "mmc", 137 COMPAT_ALTERA_SOCFPGA_DWMMC, 138 nodes, ARRAY_SIZE(nodes)); 139 140 ret = socfpga_dwmci_process_node(blob, nodes, count); 141 142 return ret; 143 } 144