1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <asm/arch/clock_manager.h>
8 #include <asm/arch/system_manager.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <dwmmc.h>
12 #include <errno.h>
13 #include <fdtdec.h>
14 #include <linux/libfdt.h>
15 #include <linux/err.h>
16 #include <malloc.h>
17 #include <reset.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 static const struct socfpga_clock_manager *clock_manager_base =
22 (void *)SOCFPGA_CLKMGR_ADDRESS;
23 static const struct socfpga_system_manager *system_manager_base =
24 (void *)SOCFPGA_SYSMGR_ADDRESS;
25
26 struct socfpga_dwmci_plat {
27 struct mmc_config cfg;
28 struct mmc mmc;
29 };
30
31 /* socfpga implmentation specific driver private data */
32 struct dwmci_socfpga_priv_data {
33 struct dwmci_host host;
34 unsigned int drvsel;
35 unsigned int smplsel;
36 };
37
socfpga_dwmci_reset(struct udevice * dev)38 static void socfpga_dwmci_reset(struct udevice *dev)
39 {
40 struct reset_ctl_bulk reset_bulk;
41 int ret;
42
43 ret = reset_get_bulk(dev, &reset_bulk);
44 if (ret) {
45 dev_warn(dev, "Can't get reset: %d\n", ret);
46 return;
47 }
48
49 reset_deassert_bulk(&reset_bulk);
50 }
51
socfpga_dwmci_clksel(struct dwmci_host * host)52 static void socfpga_dwmci_clksel(struct dwmci_host *host)
53 {
54 struct dwmci_socfpga_priv_data *priv = host->priv;
55 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
56 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
57
58 /* Disable SDMMC clock. */
59 clrbits_le32(&clock_manager_base->per_pll.en,
60 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
61
62 debug("%s: drvsel %d smplsel %d\n", __func__,
63 priv->drvsel, priv->smplsel);
64 writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
65
66 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
67 readl(&system_manager_base->sdmmcgrp_ctrl));
68
69 /* Enable SDMMC clock */
70 setbits_le32(&clock_manager_base->per_pll.en,
71 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
72 }
73
socfpga_dwmmc_get_clk_rate(struct udevice * dev)74 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
75 {
76 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
77 struct dwmci_host *host = &priv->host;
78 #if CONFIG_IS_ENABLED(CLK)
79 struct clk clk;
80 int ret;
81
82 ret = clk_get_by_index(dev, 1, &clk);
83 if (ret)
84 return ret;
85
86 host->bus_hz = clk_get_rate(&clk);
87
88 clk_free(&clk);
89 #else
90 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
91 host->bus_hz = cm_get_mmc_controller_clk_hz();
92 #endif
93 if (host->bus_hz == 0) {
94 printf("DWMMC: MMC clock is zero!");
95 return -EINVAL;
96 }
97
98 return 0;
99 }
100
socfpga_dwmmc_ofdata_to_platdata(struct udevice * dev)101 static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
102 {
103 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
104 struct dwmci_host *host = &priv->host;
105 int fifo_depth;
106
107 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
108 "fifo-depth", 0);
109 if (fifo_depth < 0) {
110 printf("DWMMC: Can't get FIFO depth\n");
111 return -EINVAL;
112 }
113
114 host->name = dev->name;
115 host->ioaddr = (void *)devfdt_get_addr(dev);
116 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
117 "bus-width", 4);
118 host->clksel = socfpga_dwmci_clksel;
119
120 /*
121 * TODO(sjg@chromium.org): Remove the need for this hack.
122 * We only have one dwmmc block on gen5 SoCFPGA.
123 */
124 host->dev_index = 0;
125 host->fifoth_val = MSIZE(0x2) |
126 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
127 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
128 "drvsel", 3);
129 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
130 "smplsel", 0);
131 host->priv = priv;
132
133 return 0;
134 }
135
socfpga_dwmmc_probe(struct udevice * dev)136 static int socfpga_dwmmc_probe(struct udevice *dev)
137 {
138 #ifdef CONFIG_BLK
139 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
140 #endif
141 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
142 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
143 struct dwmci_host *host = &priv->host;
144 int ret;
145
146 ret = socfpga_dwmmc_get_clk_rate(dev);
147 if (ret)
148 return ret;
149
150 socfpga_dwmci_reset(dev);
151
152 #ifdef CONFIG_BLK
153 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
154 host->mmc = &plat->mmc;
155 #else
156
157 ret = add_dwmci(host, host->bus_hz, 400000);
158 if (ret)
159 return ret;
160 #endif
161 host->mmc->priv = &priv->host;
162 upriv->mmc = host->mmc;
163 host->mmc->dev = dev;
164
165 return dwmci_probe(dev);
166 }
167
socfpga_dwmmc_bind(struct udevice * dev)168 static int socfpga_dwmmc_bind(struct udevice *dev)
169 {
170 #ifdef CONFIG_BLK
171 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
172 int ret;
173
174 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
175 if (ret)
176 return ret;
177 #endif
178
179 return 0;
180 }
181
182 static const struct udevice_id socfpga_dwmmc_ids[] = {
183 { .compatible = "altr,socfpga-dw-mshc" },
184 { }
185 };
186
187 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
188 .name = "socfpga_dwmmc",
189 .id = UCLASS_MMC,
190 .of_match = socfpga_dwmmc_ids,
191 .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
192 .ops = &dm_dwmci_ops,
193 .bind = socfpga_dwmmc_bind,
194 .probe = socfpga_dwmmc_probe,
195 .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
196 .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
197 };
198