xref: /openbmc/u-boot/drivers/mmc/sh_mmcif.h (revision 7fbeb642) 
1 /*
2  * MMCIF driver.
3  *
4  * Copyright (C)  2011 Renesas Solutions Corp.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License.
9  *
10  */
11 
12 #ifndef _SH_MMCIF_H_
13 #define _SH_MMCIF_H_
14 
15 struct sh_mmcif_regs {
16 	unsigned long ce_cmd_set;
17 	unsigned long reserved;
18 	unsigned long ce_arg;
19 	unsigned long ce_arg_cmd12;
20 	unsigned long ce_cmd_ctrl;
21 	unsigned long ce_block_set;
22 	unsigned long ce_clk_ctrl;
23 	unsigned long ce_buf_acc;
24 	unsigned long ce_resp3;
25 	unsigned long ce_resp2;
26 	unsigned long ce_resp1;
27 	unsigned long ce_resp0;
28 	unsigned long ce_resp_cmd12;
29 	unsigned long ce_data;
30 	unsigned long reserved2[2];
31 	unsigned long ce_int;
32 	unsigned long ce_int_mask;
33 	unsigned long ce_host_sts1;
34 	unsigned long ce_host_sts2;
35 	unsigned long reserved3[11];
36 	unsigned long ce_version;
37 };
38 
39 /* CE_CMD_SET */
40 #define CMD_MASK		0x3f000000
41 #define CMD_SET_RTYP_NO		((0 << 23) | (0 << 22))
42 /* R1/R1b/R3/R4/R5 */
43 #define CMD_SET_RTYP_6B		((0 << 23) | (1 << 22))
44 /* R2 */
45 #define CMD_SET_RTYP_17B	((1 << 23) | (0 << 22))
46 /* R1b */
47 #define CMD_SET_RBSY		(1 << 21)
48 #define CMD_SET_CCSEN		(1 << 20)
49 /* 1: on data, 0: no data */
50 #define CMD_SET_WDAT		(1 << 19)
51 /* 1: write to card, 0: read from card */
52 #define CMD_SET_DWEN		(1 << 18)
53 /* 1: multi block trans, 0: single */
54 #define CMD_SET_CMLTE		(1 << 17)
55 /* 1: CMD12 auto issue */
56 #define CMD_SET_CMD12EN		(1 << 16)
57 /* index check */
58 #define CMD_SET_RIDXC_INDEX	((0 << 15) | (0 << 14))
59 /* check bits check */
60 #define CMD_SET_RIDXC_BITS	((0 << 15) | (1 << 14))
61 /* no check */
62 #define CMD_SET_RIDXC_NO	((1 << 15) | (0 << 14))
63 /* 1: CRC7 check*/
64 #define CMD_SET_CRC7C		((0 << 13) | (0 << 12))
65 /* 1: check bits check*/
66 #define CMD_SET_CRC7C_BITS	((0 << 13) | (1 << 12))
67 /* 1: internal CRC7 check*/
68 #define CMD_SET_CRC7C_INTERNAL	((1 << 13) | (0 << 12))
69 /* 1: CRC16 check*/
70 #define CMD_SET_CRC16C		(1 << 10)
71 /* 1: not receive CRC status */
72 #define CMD_SET_CRCSTE		(1 << 8)
73 /* 1: tran mission bit "Low" */
74 #define CMD_SET_TBIT		(1 << 7)
75 /* 1: open/drain */
76 #define CMD_SET_OPDM		(1 << 6)
77 #define CMD_SET_CCSH		(1 << 5)
78 /* 1bit */
79 #define CMD_SET_DATW_1		((0 << 1) | (0 << 0))
80 /* 4bit */
81 #define CMD_SET_DATW_4		((0 << 1) | (1 << 0))
82 /* 8bit */
83 #define CMD_SET_DATW_8		((1 << 1) | (0 << 0))
84 
85 /* CE_CMD_CTRL */
86 #define CMD_CTRL_BREAK		(1 << 0)
87 
88 /* CE_BLOCK_SET */
89 #define BLOCK_SIZE_MASK		0x0000ffff
90 
91 /* CE_CLK_CTRL */
92 #define CLK_ENABLE		(1 << 24)
93 #define CLK_CLEAR		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
94 #define CLK_PCLK		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
95 /* respons timeout */
96 #define SRSPTO_256		((1 << 13) | (0 << 12))
97 /* respons busy timeout */
98 #define SRBSYTO_29		((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
99 /* read/write timeout */
100 #define SRWDTO_29		((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
101 /* ccs timeout */
102 #define SCCSTO_29		((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0))
103 
104 /* CE_BUF_ACC */
105 #define BUF_ACC_DMAWEN		(1 << 25)
106 #define BUF_ACC_DMAREN		(1 << 24)
107 #define BUF_ACC_BUSW_32		(0 << 17)
108 #define BUF_ACC_BUSW_16		(1 << 17)
109 #define BUF_ACC_ATYP		(1 << 16)
110 
111 /* CE_INT */
112 #define INT_CCSDE		(1 << 29)
113 #define INT_CMD12DRE		(1 << 26)
114 #define INT_CMD12RBE		(1 << 25)
115 #define INT_CMD12CRE		(1 << 24)
116 #define INT_DTRANE		(1 << 23)
117 #define INT_BUFRE		(1 << 22)
118 #define INT_BUFWEN		(1 << 21)
119 #define INT_BUFREN		(1 << 20)
120 #define INT_CCSRCV		(1 << 19)
121 #define INT_RBSYE		(1 << 17)
122 #define INT_CRSPE		(1 << 16)
123 #define INT_CMDVIO		(1 << 15)
124 #define INT_BUFVIO		(1 << 14)
125 #define INT_WDATERR		(1 << 11)
126 #define INT_RDATERR		(1 << 10)
127 #define INT_RIDXERR		(1 << 9)
128 #define INT_RSPERR		(1 << 8)
129 #define INT_CCSTO		(1 << 5)
130 #define INT_CRCSTO		(1 << 4)
131 #define INT_WDATTO		(1 << 3)
132 #define INT_RDATTO		(1 << 2)
133 #define INT_RBSYTO		(1 << 1)
134 #define INT_RSPTO		(1 << 0)
135 #define INT_ERR_STS		(INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
136 				 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
137 				 INT_CCSTO | INT_CRCSTO | INT_WDATTO |	  \
138 				 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
139 #define INT_START_MAGIC		0xD80430C0
140 
141 /* CE_INT_MASK */
142 #define MASK_ALL		0x00000000
143 #define MASK_MCCSDE		(1 << 29)
144 #define MASK_MCMD12DRE		(1 << 26)
145 #define MASK_MCMD12RBE		(1 << 25)
146 #define MASK_MCMD12CRE		(1 << 24)
147 #define MASK_MDTRANE		(1 << 23)
148 #define MASK_MBUFRE		(1 << 22)
149 #define MASK_MBUFWEN		(1 << 21)
150 #define MASK_MBUFREN		(1 << 20)
151 #define MASK_MCCSRCV		(1 << 19)
152 #define MASK_MRBSYE		(1 << 17)
153 #define MASK_MCRSPE		(1 << 16)
154 #define MASK_MCMDVIO		(1 << 15)
155 #define MASK_MBUFVIO		(1 << 14)
156 #define MASK_MWDATERR		(1 << 11)
157 #define MASK_MRDATERR		(1 << 10)
158 #define MASK_MRIDXERR		(1 << 9)
159 #define MASK_MRSPERR		(1 << 8)
160 #define MASK_MCCSTO		(1 << 5)
161 #define MASK_MCRCSTO		(1 << 4)
162 #define MASK_MWDATTO		(1 << 3)
163 #define MASK_MRDATTO		(1 << 2)
164 #define MASK_MRBSYTO		(1 << 1)
165 #define MASK_MRSPTO		(1 << 0)
166 
167 /* CE_HOST_STS1 */
168 #define STS1_CMDSEQ		(1 << 31)
169 
170 /* CE_HOST_STS2 */
171 #define STS2_CRCSTE		(1 << 31)
172 #define STS2_CRC16E		(1 << 30)
173 #define STS2_AC12CRCE		(1 << 29)
174 #define STS2_RSPCRC7E		(1 << 28)
175 #define STS2_CRCSTEBE		(1 << 27)
176 #define STS2_RDATEBE		(1 << 26)
177 #define STS2_AC12REBE		(1 << 25)
178 #define STS2_RSPEBE		(1 << 24)
179 #define STS2_AC12IDXE		(1 << 23)
180 #define STS2_RSPIDXE		(1 << 22)
181 #define STS2_CCSTO		(1 << 15)
182 #define STS2_RDATTO		(1 << 14)
183 #define STS2_DATBSYTO		(1 << 13)
184 #define STS2_CRCSTTO		(1 << 12)
185 #define STS2_AC12BSYTO		(1 << 11)
186 #define STS2_RSPBSYTO		(1 << 10)
187 #define STS2_AC12RSPTO		(1 << 9)
188 #define STS2_RSPTO		(1 << 8)
189 
190 #define STS2_CRC_ERR		(STS2_CRCSTE | STS2_CRC16E |		\
191 				 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
192 #define STS2_TIMEOUT_ERR	(STS2_CCSTO | STS2_RDATTO |		\
193 				 STS2_DATBSYTO | STS2_CRCSTTO |		\
194 				 STS2_AC12BSYTO | STS2_RSPBSYTO |	\
195 				 STS2_AC12RSPTO | STS2_RSPTO)
196 
197 /* CE_VERSION */
198 #define SOFT_RST_ON		(1 << 31)
199 #define SOFT_RST_OFF		(0 << 31)
200 
201 #define CLKDEV_EMMC_DATA	52000000	/* 52MHz */
202 #define	CLKDEV_MMC_INIT		400000		/* 100 - 400 KHz */
203 
204 #define MMC_BUS_WIDTH_1		0
205 #define MMC_BUS_WIDTH_4		2
206 #define MMC_BUS_WIDTH_8		3
207 
208 struct sh_mmcif_host {
209 	struct mmc_data		*data;
210 	struct sh_mmcif_regs	*regs;
211 	unsigned int		clk;
212 	int			bus_width;
213 	u16			wait_int;
214 	u16			sd_error;
215 	u8			last_cmd;
216 };
217 
218 static inline u32 sh_mmcif_read(unsigned long *reg)
219 {
220 	return readl(reg);
221 }
222 
223 static inline void sh_mmcif_write(u32 val, unsigned long *reg)
224 {
225 	writel(val, reg);
226 }
227 
228 static inline void sh_mmcif_bitset(u32 val, unsigned long *reg)
229 {
230 	sh_mmcif_write(val | sh_mmcif_read(reg), reg);
231 }
232 
233 static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg)
234 {
235 	sh_mmcif_write(~val & sh_mmcif_read(reg), reg);
236 }
237 
238 #endif /* _SH_MMCIF_H_ */
239