1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <mmc.h> 14 #include <sdhci.h> 15 16 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 17 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; 18 #else 19 void *aligned_buffer; 20 #endif 21 22 static void sdhci_reset(struct sdhci_host *host, u8 mask) 23 { 24 unsigned long timeout; 25 26 /* Wait max 100 ms */ 27 timeout = 100; 28 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 29 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 30 if (timeout == 0) { 31 printf("%s: Reset 0x%x never completed.\n", 32 __func__, (int)mask); 33 return; 34 } 35 timeout--; 36 udelay(1000); 37 } 38 } 39 40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 41 { 42 int i; 43 if (cmd->resp_type & MMC_RSP_136) { 44 /* CRC is stripped so we need to do some shifting. */ 45 for (i = 0; i < 4; i++) { 46 cmd->response[i] = sdhci_readl(host, 47 SDHCI_RESPONSE + (3-i)*4) << 8; 48 if (i != 3) 49 cmd->response[i] |= sdhci_readb(host, 50 SDHCI_RESPONSE + (3-i)*4-1); 51 } 52 } else { 53 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 54 } 55 } 56 57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 58 { 59 int i; 60 char *offs; 61 for (i = 0; i < data->blocksize; i += 4) { 62 offs = data->dest + i; 63 if (data->flags == MMC_DATA_READ) 64 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 65 else 66 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 67 } 68 } 69 70 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 71 unsigned int start_addr) 72 { 73 unsigned int stat, rdy, mask, timeout, block = 0; 74 #ifdef CONFIG_MMC_SDMA 75 unsigned char ctrl; 76 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 77 ctrl &= ~SDHCI_CTRL_DMA_MASK; 78 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 79 #endif 80 81 timeout = 1000000; 82 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 83 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 84 do { 85 stat = sdhci_readl(host, SDHCI_INT_STATUS); 86 if (stat & SDHCI_INT_ERROR) { 87 printf("%s: Error detected in status(0x%X)!\n", 88 __func__, stat); 89 return -1; 90 } 91 if (stat & rdy) { 92 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 93 continue; 94 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 95 sdhci_transfer_pio(host, data); 96 data->dest += data->blocksize; 97 if (++block >= data->blocks) 98 break; 99 } 100 #ifdef CONFIG_MMC_SDMA 101 if (stat & SDHCI_INT_DMA_END) { 102 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 103 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 104 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 105 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 106 } 107 #endif 108 if (timeout-- > 0) 109 udelay(10); 110 else { 111 printf("%s: Transfer data timeout\n", __func__); 112 return -1; 113 } 114 } while (!(stat & SDHCI_INT_DATA_END)); 115 return 0; 116 } 117 118 /* 119 * No command will be sent by driver if card is busy, so driver must wait 120 * for card ready state. 121 * Every time when card is busy after timeout then (last) timeout value will be 122 * increased twice but only if it doesn't exceed global defined maximum. 123 * Each function call will use last timeout value. Max timeout can be redefined 124 * in board config file. 125 */ 126 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT 127 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 128 #endif 129 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 130 131 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 132 struct mmc_data *data) 133 { 134 struct sdhci_host *host = mmc->priv; 135 unsigned int stat = 0; 136 int ret = 0; 137 int trans_bytes = 0, is_aligned = 1; 138 u32 mask, flags, mode; 139 unsigned int time = 0, start_addr = 0; 140 int mmc_dev = mmc->block_dev.devnum; 141 unsigned start = get_timer(0); 142 143 /* Timeout unit - ms */ 144 static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; 145 146 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 147 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; 148 149 /* We shouldn't wait for data inihibit for stop commands, even 150 though they might use busy signaling */ 151 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 152 mask &= ~SDHCI_DATA_INHIBIT; 153 154 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 155 if (time >= cmd_timeout) { 156 printf("%s: MMC: %d busy ", __func__, mmc_dev); 157 if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) { 158 cmd_timeout += cmd_timeout; 159 printf("timeout increasing to: %u ms.\n", 160 cmd_timeout); 161 } else { 162 puts("timeout.\n"); 163 return COMM_ERR; 164 } 165 } 166 time++; 167 udelay(1000); 168 } 169 170 mask = SDHCI_INT_RESPONSE; 171 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 172 flags = SDHCI_CMD_RESP_NONE; 173 else if (cmd->resp_type & MMC_RSP_136) 174 flags = SDHCI_CMD_RESP_LONG; 175 else if (cmd->resp_type & MMC_RSP_BUSY) { 176 flags = SDHCI_CMD_RESP_SHORT_BUSY; 177 mask |= SDHCI_INT_DATA_END; 178 } else 179 flags = SDHCI_CMD_RESP_SHORT; 180 181 if (cmd->resp_type & MMC_RSP_CRC) 182 flags |= SDHCI_CMD_CRC; 183 if (cmd->resp_type & MMC_RSP_OPCODE) 184 flags |= SDHCI_CMD_INDEX; 185 if (data) 186 flags |= SDHCI_CMD_DATA; 187 188 /* Set Transfer mode regarding to data flag */ 189 if (data != 0) { 190 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 191 mode = SDHCI_TRNS_BLK_CNT_EN; 192 trans_bytes = data->blocks * data->blocksize; 193 if (data->blocks > 1) 194 mode |= SDHCI_TRNS_MULTI; 195 196 if (data->flags == MMC_DATA_READ) 197 mode |= SDHCI_TRNS_READ; 198 199 #ifdef CONFIG_MMC_SDMA 200 if (data->flags == MMC_DATA_READ) 201 start_addr = (unsigned long)data->dest; 202 else 203 start_addr = (unsigned long)data->src; 204 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 205 (start_addr & 0x7) != 0x0) { 206 is_aligned = 0; 207 start_addr = (unsigned long)aligned_buffer; 208 if (data->flags != MMC_DATA_READ) 209 memcpy(aligned_buffer, data->src, trans_bytes); 210 } 211 212 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 213 /* 214 * Always use this bounce-buffer when 215 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined 216 */ 217 is_aligned = 0; 218 start_addr = (unsigned long)aligned_buffer; 219 if (data->flags != MMC_DATA_READ) 220 memcpy(aligned_buffer, data->src, trans_bytes); 221 #endif 222 223 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 224 mode |= SDHCI_TRNS_DMA; 225 #endif 226 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 227 data->blocksize), 228 SDHCI_BLOCK_SIZE); 229 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 230 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 231 } else if (cmd->resp_type & MMC_RSP_BUSY) { 232 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 233 } 234 235 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 236 #ifdef CONFIG_MMC_SDMA 237 flush_cache(start_addr, trans_bytes); 238 #endif 239 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 240 start = get_timer(0); 241 do { 242 stat = sdhci_readl(host, SDHCI_INT_STATUS); 243 if (stat & SDHCI_INT_ERROR) 244 break; 245 } while (((stat & mask) != mask) && 246 (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT)); 247 248 if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) { 249 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) 250 return 0; 251 else { 252 printf("%s: Timeout for status update!\n", __func__); 253 return TIMEOUT; 254 } 255 } 256 257 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 258 sdhci_cmd_done(host, cmd); 259 sdhci_writel(host, mask, SDHCI_INT_STATUS); 260 } else 261 ret = -1; 262 263 if (!ret && data) 264 ret = sdhci_transfer_data(host, data, start_addr); 265 266 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 267 udelay(1000); 268 269 stat = sdhci_readl(host, SDHCI_INT_STATUS); 270 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 271 if (!ret) { 272 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 273 !is_aligned && (data->flags == MMC_DATA_READ)) 274 memcpy(data->dest, aligned_buffer, trans_bytes); 275 return 0; 276 } 277 278 sdhci_reset(host, SDHCI_RESET_CMD); 279 sdhci_reset(host, SDHCI_RESET_DATA); 280 if (stat & SDHCI_INT_TIMEOUT) 281 return TIMEOUT; 282 else 283 return COMM_ERR; 284 } 285 286 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) 287 { 288 struct sdhci_host *host = mmc->priv; 289 unsigned int div, clk, timeout, reg; 290 291 /* Wait max 20 ms */ 292 timeout = 200; 293 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 294 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 295 if (timeout == 0) { 296 printf("%s: Timeout to wait cmd & data inhibit\n", 297 __func__); 298 return -1; 299 } 300 301 timeout--; 302 udelay(100); 303 } 304 305 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 306 reg &= ~SDHCI_CLOCK_CARD_EN; 307 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 308 309 if (clock == 0) 310 return 0; 311 312 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 313 /* Version 3.00 divisors must be a multiple of 2. */ 314 if (mmc->cfg->f_max <= clock) 315 div = 1; 316 else { 317 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { 318 if ((mmc->cfg->f_max / div) <= clock) 319 break; 320 } 321 } 322 } else { 323 /* Version 2.00 divisors must be a power of 2. */ 324 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 325 if ((mmc->cfg->f_max / div) <= clock) 326 break; 327 } 328 } 329 div >>= 1; 330 331 if (host->set_clock) 332 host->set_clock(host->index, div); 333 334 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 335 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 336 << SDHCI_DIVIDER_HI_SHIFT; 337 clk |= SDHCI_CLOCK_INT_EN; 338 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 339 340 /* Wait max 20 ms */ 341 timeout = 20; 342 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 343 & SDHCI_CLOCK_INT_STABLE)) { 344 if (timeout == 0) { 345 printf("%s: Internal clock never stabilised.\n", 346 __func__); 347 return -1; 348 } 349 timeout--; 350 udelay(1000); 351 } 352 353 clk |= SDHCI_CLOCK_CARD_EN; 354 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 355 return 0; 356 } 357 358 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 359 { 360 u8 pwr = 0; 361 362 if (power != (unsigned short)-1) { 363 switch (1 << power) { 364 case MMC_VDD_165_195: 365 pwr = SDHCI_POWER_180; 366 break; 367 case MMC_VDD_29_30: 368 case MMC_VDD_30_31: 369 pwr = SDHCI_POWER_300; 370 break; 371 case MMC_VDD_32_33: 372 case MMC_VDD_33_34: 373 pwr = SDHCI_POWER_330; 374 break; 375 } 376 } 377 378 if (pwr == 0) { 379 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 380 return; 381 } 382 383 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 384 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 385 386 pwr |= SDHCI_POWER_ON; 387 388 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 389 } 390 391 static void sdhci_set_ios(struct mmc *mmc) 392 { 393 u32 ctrl; 394 struct sdhci_host *host = mmc->priv; 395 396 if (host->set_control_reg) 397 host->set_control_reg(host); 398 399 if (mmc->clock != host->clock) 400 sdhci_set_clock(mmc, mmc->clock); 401 402 /* Set bus width */ 403 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 404 if (mmc->bus_width == 8) { 405 ctrl &= ~SDHCI_CTRL_4BITBUS; 406 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 407 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 408 ctrl |= SDHCI_CTRL_8BITBUS; 409 } else { 410 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 411 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 412 ctrl &= ~SDHCI_CTRL_8BITBUS; 413 if (mmc->bus_width == 4) 414 ctrl |= SDHCI_CTRL_4BITBUS; 415 else 416 ctrl &= ~SDHCI_CTRL_4BITBUS; 417 } 418 419 if (mmc->clock > 26000000) 420 ctrl |= SDHCI_CTRL_HISPD; 421 else 422 ctrl &= ~SDHCI_CTRL_HISPD; 423 424 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) 425 ctrl &= ~SDHCI_CTRL_HISPD; 426 427 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 428 } 429 430 static int sdhci_init(struct mmc *mmc) 431 { 432 struct sdhci_host *host = mmc->priv; 433 434 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 435 aligned_buffer = memalign(8, 512*1024); 436 if (!aligned_buffer) { 437 printf("%s: Aligned buffer alloc failed!!!\n", 438 __func__); 439 return -1; 440 } 441 } 442 443 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 444 445 if (host->quirks & SDHCI_QUIRK_NO_CD) { 446 #if defined(CONFIG_PIC32_SDHCI) 447 /* PIC32 SDHCI CD errata: 448 * - set CD_TEST and clear CD_TEST_INS bit 449 */ 450 sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL); 451 #else 452 unsigned int status; 453 454 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, 455 SDHCI_HOST_CONTROL); 456 457 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 458 while ((!(status & SDHCI_CARD_PRESENT)) || 459 (!(status & SDHCI_CARD_STATE_STABLE)) || 460 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) 461 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 462 #endif 463 } 464 465 /* Enable only interrupts served by the SD controller */ 466 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 467 SDHCI_INT_ENABLE); 468 /* Mask all sdhci interrupt sources */ 469 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 470 471 return 0; 472 } 473 474 475 static const struct mmc_ops sdhci_ops = { 476 .send_cmd = sdhci_send_command, 477 .set_ios = sdhci_set_ios, 478 .init = sdhci_init, 479 }; 480 481 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) 482 { 483 unsigned int caps; 484 485 host->cfg.name = host->name; 486 host->cfg.ops = &sdhci_ops; 487 488 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 489 #ifdef CONFIG_MMC_SDMA 490 if (!(caps & SDHCI_CAN_DO_SDMA)) { 491 printf("%s: Your controller doesn't support SDMA!!\n", 492 __func__); 493 return -1; 494 } 495 #endif 496 497 if (max_clk) 498 host->cfg.f_max = max_clk; 499 else { 500 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 501 host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) 502 >> SDHCI_CLOCK_BASE_SHIFT; 503 else 504 host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) 505 >> SDHCI_CLOCK_BASE_SHIFT; 506 host->cfg.f_max *= 1000000; 507 } 508 if (host->cfg.f_max == 0) { 509 printf("%s: Hardware doesn't specify base clock frequency\n", 510 __func__); 511 return -1; 512 } 513 if (min_clk) 514 host->cfg.f_min = min_clk; 515 else { 516 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 517 host->cfg.f_min = host->cfg.f_max / 518 SDHCI_MAX_DIV_SPEC_300; 519 else 520 host->cfg.f_min = host->cfg.f_max / 521 SDHCI_MAX_DIV_SPEC_200; 522 } 523 524 host->cfg.voltages = 0; 525 if (caps & SDHCI_CAN_VDD_330) 526 host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 527 if (caps & SDHCI_CAN_VDD_300) 528 host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 529 if (caps & SDHCI_CAN_VDD_180) 530 host->cfg.voltages |= MMC_VDD_165_195; 531 532 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 533 host->cfg.voltages |= host->voltages; 534 535 host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 536 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 537 if (caps & SDHCI_CAN_DO_8BIT) 538 host->cfg.host_caps |= MMC_MODE_8BIT; 539 } 540 541 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) 542 host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); 543 544 if (host->host_caps) 545 host->cfg.host_caps |= host->host_caps; 546 547 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 548 549 sdhci_reset(host, SDHCI_RESET_ALL); 550 551 host->mmc = mmc_create(&host->cfg, host); 552 if (host->mmc == NULL) { 553 printf("%s: mmc create fail!\n", __func__); 554 return -1; 555 } 556 557 return 0; 558 } 559