xref: /openbmc/u-boot/drivers/mmc/sdhci.c (revision dac09fc1)
1 /*
2  * Copyright 2011, Marvell Semiconductor Inc.
3  * Lei Wen <leiwen@marvell.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  *
7  * Back ported to the 8xx platform (from the 8260 platform) by
8  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9  */
10 
11 #include <common.h>
12 #include <errno.h>
13 #include <malloc.h>
14 #include <mmc.h>
15 #include <sdhci.h>
16 
17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
19 #else
20 void *aligned_buffer;
21 #endif
22 
23 static void sdhci_reset(struct sdhci_host *host, u8 mask)
24 {
25 	unsigned long timeout;
26 
27 	/* Wait max 100 ms */
28 	timeout = 100;
29 	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
30 	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
31 		if (timeout == 0) {
32 			printf("%s: Reset 0x%x never completed.\n",
33 			       __func__, (int)mask);
34 			return;
35 		}
36 		timeout--;
37 		udelay(1000);
38 	}
39 }
40 
41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
42 {
43 	int i;
44 	if (cmd->resp_type & MMC_RSP_136) {
45 		/* CRC is stripped so we need to do some shifting. */
46 		for (i = 0; i < 4; i++) {
47 			cmd->response[i] = sdhci_readl(host,
48 					SDHCI_RESPONSE + (3-i)*4) << 8;
49 			if (i != 3)
50 				cmd->response[i] |= sdhci_readb(host,
51 						SDHCI_RESPONSE + (3-i)*4-1);
52 		}
53 	} else {
54 		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
55 	}
56 }
57 
58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
59 {
60 	int i;
61 	char *offs;
62 	for (i = 0; i < data->blocksize; i += 4) {
63 		offs = data->dest + i;
64 		if (data->flags == MMC_DATA_READ)
65 			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
66 		else
67 			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
68 	}
69 }
70 
71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
72 				unsigned int start_addr)
73 {
74 	unsigned int stat, rdy, mask, timeout, block = 0;
75 #ifdef CONFIG_MMC_SDMA
76 	unsigned char ctrl;
77 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
78 	ctrl &= ~SDHCI_CTRL_DMA_MASK;
79 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
80 #endif
81 
82 	timeout = 1000000;
83 	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
84 	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
85 	do {
86 		stat = sdhci_readl(host, SDHCI_INT_STATUS);
87 		if (stat & SDHCI_INT_ERROR) {
88 			printf("%s: Error detected in status(0x%X)!\n",
89 			       __func__, stat);
90 			return -EIO;
91 		}
92 		if (stat & rdy) {
93 			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
94 				continue;
95 			sdhci_writel(host, rdy, SDHCI_INT_STATUS);
96 			sdhci_transfer_pio(host, data);
97 			data->dest += data->blocksize;
98 			if (++block >= data->blocks)
99 				break;
100 		}
101 #ifdef CONFIG_MMC_SDMA
102 		if (stat & SDHCI_INT_DMA_END) {
103 			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
104 			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
105 			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
106 			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
107 		}
108 #endif
109 		if (timeout-- > 0)
110 			udelay(10);
111 		else {
112 			printf("%s: Transfer data timeout\n", __func__);
113 			return -ETIMEDOUT;
114 		}
115 	} while (!(stat & SDHCI_INT_DATA_END));
116 	return 0;
117 }
118 
119 /*
120  * No command will be sent by driver if card is busy, so driver must wait
121  * for card ready state.
122  * Every time when card is busy after timeout then (last) timeout value will be
123  * increased twice but only if it doesn't exceed global defined maximum.
124  * Each function call will use last timeout value.
125  */
126 #define SDHCI_CMD_MAX_TIMEOUT			3200
127 #define SDHCI_CMD_DEFAULT_TIMEOUT		100
128 #define SDHCI_READ_STATUS_TIMEOUT		1000
129 
130 #ifdef CONFIG_DM_MMC_OPS
131 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
132 			      struct mmc_data *data)
133 {
134 	struct mmc *mmc = mmc_get_mmc_dev(dev);
135 
136 #else
137 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
138 			      struct mmc_data *data)
139 {
140 #endif
141 	struct sdhci_host *host = mmc->priv;
142 	unsigned int stat = 0;
143 	int ret = 0;
144 	int trans_bytes = 0, is_aligned = 1;
145 	u32 mask, flags, mode;
146 	unsigned int time = 0, start_addr = 0;
147 	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
148 	unsigned start = get_timer(0);
149 
150 	/* Timeout unit - ms */
151 	static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
152 
153 	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
154 	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
155 
156 	/* We shouldn't wait for data inihibit for stop commands, even
157 	   though they might use busy signaling */
158 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
159 		mask &= ~SDHCI_DATA_INHIBIT;
160 
161 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
162 		if (time >= cmd_timeout) {
163 			printf("%s: MMC: %d busy ", __func__, mmc_dev);
164 			if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
165 				cmd_timeout += cmd_timeout;
166 				printf("timeout increasing to: %u ms.\n",
167 				       cmd_timeout);
168 			} else {
169 				puts("timeout.\n");
170 				return -ECOMM;
171 			}
172 		}
173 		time++;
174 		udelay(1000);
175 	}
176 
177 	mask = SDHCI_INT_RESPONSE;
178 	if (!(cmd->resp_type & MMC_RSP_PRESENT))
179 		flags = SDHCI_CMD_RESP_NONE;
180 	else if (cmd->resp_type & MMC_RSP_136)
181 		flags = SDHCI_CMD_RESP_LONG;
182 	else if (cmd->resp_type & MMC_RSP_BUSY) {
183 		flags = SDHCI_CMD_RESP_SHORT_BUSY;
184 		if (data)
185 			mask |= SDHCI_INT_DATA_END;
186 	} else
187 		flags = SDHCI_CMD_RESP_SHORT;
188 
189 	if (cmd->resp_type & MMC_RSP_CRC)
190 		flags |= SDHCI_CMD_CRC;
191 	if (cmd->resp_type & MMC_RSP_OPCODE)
192 		flags |= SDHCI_CMD_INDEX;
193 	if (data)
194 		flags |= SDHCI_CMD_DATA;
195 
196 	/* Set Transfer mode regarding to data flag */
197 	if (data != 0) {
198 		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
199 		mode = SDHCI_TRNS_BLK_CNT_EN;
200 		trans_bytes = data->blocks * data->blocksize;
201 		if (data->blocks > 1)
202 			mode |= SDHCI_TRNS_MULTI;
203 
204 		if (data->flags == MMC_DATA_READ)
205 			mode |= SDHCI_TRNS_READ;
206 
207 #ifdef CONFIG_MMC_SDMA
208 		if (data->flags == MMC_DATA_READ)
209 			start_addr = (unsigned long)data->dest;
210 		else
211 			start_addr = (unsigned long)data->src;
212 		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
213 				(start_addr & 0x7) != 0x0) {
214 			is_aligned = 0;
215 			start_addr = (unsigned long)aligned_buffer;
216 			if (data->flags != MMC_DATA_READ)
217 				memcpy(aligned_buffer, data->src, trans_bytes);
218 		}
219 
220 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
221 		/*
222 		 * Always use this bounce-buffer when
223 		 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
224 		 */
225 		is_aligned = 0;
226 		start_addr = (unsigned long)aligned_buffer;
227 		if (data->flags != MMC_DATA_READ)
228 			memcpy(aligned_buffer, data->src, trans_bytes);
229 #endif
230 
231 		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
232 		mode |= SDHCI_TRNS_DMA;
233 #endif
234 		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
235 				data->blocksize),
236 				SDHCI_BLOCK_SIZE);
237 		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
238 		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
239 	} else if (cmd->resp_type & MMC_RSP_BUSY) {
240 		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
241 	}
242 
243 	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
244 #ifdef CONFIG_MMC_SDMA
245 	trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
246 	flush_cache(start_addr, trans_bytes);
247 #endif
248 	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
249 	start = get_timer(0);
250 	do {
251 		stat = sdhci_readl(host, SDHCI_INT_STATUS);
252 		if (stat & SDHCI_INT_ERROR)
253 			break;
254 
255 		if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
256 			if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
257 				return 0;
258 			} else {
259 				printf("%s: Timeout for status update!\n",
260 				       __func__);
261 				return -ETIMEDOUT;
262 			}
263 		}
264 	} while ((stat & mask) != mask);
265 
266 	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
267 		sdhci_cmd_done(host, cmd);
268 		sdhci_writel(host, mask, SDHCI_INT_STATUS);
269 	} else
270 		ret = -1;
271 
272 	if (!ret && data)
273 		ret = sdhci_transfer_data(host, data, start_addr);
274 
275 	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
276 		udelay(1000);
277 
278 	stat = sdhci_readl(host, SDHCI_INT_STATUS);
279 	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
280 	if (!ret) {
281 		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
282 				!is_aligned && (data->flags == MMC_DATA_READ))
283 			memcpy(data->dest, aligned_buffer, trans_bytes);
284 		return 0;
285 	}
286 
287 	sdhci_reset(host, SDHCI_RESET_CMD);
288 	sdhci_reset(host, SDHCI_RESET_DATA);
289 	if (stat & SDHCI_INT_TIMEOUT)
290 		return -ETIMEDOUT;
291 	else
292 		return -ECOMM;
293 }
294 
295 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
296 {
297 	struct sdhci_host *host = mmc->priv;
298 	unsigned int div, clk = 0, timeout, reg;
299 
300 	/* Wait max 20 ms */
301 	timeout = 200;
302 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
303 			   (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
304 		if (timeout == 0) {
305 			printf("%s: Timeout to wait cmd & data inhibit\n",
306 			       __func__);
307 			return -EBUSY;
308 		}
309 
310 		timeout--;
311 		udelay(100);
312 	}
313 
314 	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
315 	reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
316 	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
317 
318 	if (clock == 0)
319 		return 0;
320 
321 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
322 		/*
323 		 * Check if the Host Controller supports Programmable Clock
324 		 * Mode.
325 		 */
326 		if (host->clk_mul) {
327 			for (div = 1; div <= 1024; div++) {
328 				if ((mmc->cfg->f_max * host->clk_mul / div)
329 					<= clock)
330 					break;
331 			}
332 
333 			/*
334 			 * Set Programmable Clock Mode in the Clock
335 			 * Control register.
336 			 */
337 			clk = SDHCI_PROG_CLOCK_MODE;
338 			div--;
339 		} else {
340 			/* Version 3.00 divisors must be a multiple of 2. */
341 			if (mmc->cfg->f_max <= clock) {
342 				div = 1;
343 			} else {
344 				for (div = 2;
345 				     div < SDHCI_MAX_DIV_SPEC_300;
346 				     div += 2) {
347 					if ((mmc->cfg->f_max / div) <= clock)
348 						break;
349 				}
350 			}
351 			div >>= 1;
352 		}
353 	} else {
354 		/* Version 2.00 divisors must be a power of 2. */
355 		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
356 			if ((mmc->cfg->f_max / div) <= clock)
357 				break;
358 		}
359 		div >>= 1;
360 	}
361 
362 	if (host->set_clock)
363 		host->set_clock(host->index, div);
364 
365 	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
366 	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
367 		<< SDHCI_DIVIDER_HI_SHIFT;
368 	clk |= SDHCI_CLOCK_INT_EN;
369 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
370 
371 	/* Wait max 20 ms */
372 	timeout = 20;
373 	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
374 		& SDHCI_CLOCK_INT_STABLE)) {
375 		if (timeout == 0) {
376 			printf("%s: Internal clock never stabilised.\n",
377 			       __func__);
378 			return -EBUSY;
379 		}
380 		timeout--;
381 		udelay(1000);
382 	}
383 
384 	clk |= SDHCI_CLOCK_CARD_EN;
385 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
386 	return 0;
387 }
388 
389 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
390 {
391 	u8 pwr = 0;
392 
393 	if (power != (unsigned short)-1) {
394 		switch (1 << power) {
395 		case MMC_VDD_165_195:
396 			pwr = SDHCI_POWER_180;
397 			break;
398 		case MMC_VDD_29_30:
399 		case MMC_VDD_30_31:
400 			pwr = SDHCI_POWER_300;
401 			break;
402 		case MMC_VDD_32_33:
403 		case MMC_VDD_33_34:
404 			pwr = SDHCI_POWER_330;
405 			break;
406 		}
407 	}
408 
409 	if (pwr == 0) {
410 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
411 		return;
412 	}
413 
414 	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
415 		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
416 
417 	pwr |= SDHCI_POWER_ON;
418 
419 	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
420 }
421 
422 #ifdef CONFIG_DM_MMC_OPS
423 static int sdhci_set_ios(struct udevice *dev)
424 {
425 	struct mmc *mmc = mmc_get_mmc_dev(dev);
426 #else
427 static void sdhci_set_ios(struct mmc *mmc)
428 {
429 #endif
430 	u32 ctrl;
431 	struct sdhci_host *host = mmc->priv;
432 
433 	if (host->set_control_reg)
434 		host->set_control_reg(host);
435 
436 	if (mmc->clock != host->clock)
437 		sdhci_set_clock(mmc, mmc->clock);
438 
439 	/* Set bus width */
440 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
441 	if (mmc->bus_width == 8) {
442 		ctrl &= ~SDHCI_CTRL_4BITBUS;
443 		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
444 				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
445 			ctrl |= SDHCI_CTRL_8BITBUS;
446 	} else {
447 		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
448 				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
449 			ctrl &= ~SDHCI_CTRL_8BITBUS;
450 		if (mmc->bus_width == 4)
451 			ctrl |= SDHCI_CTRL_4BITBUS;
452 		else
453 			ctrl &= ~SDHCI_CTRL_4BITBUS;
454 	}
455 
456 	if (mmc->clock > 26000000)
457 		ctrl |= SDHCI_CTRL_HISPD;
458 	else
459 		ctrl &= ~SDHCI_CTRL_HISPD;
460 
461 	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
462 		ctrl &= ~SDHCI_CTRL_HISPD;
463 
464 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
465 #ifdef CONFIG_DM_MMC_OPS
466 	return 0;
467 #endif
468 }
469 
470 static int sdhci_init(struct mmc *mmc)
471 {
472 	struct sdhci_host *host = mmc->priv;
473 
474 	sdhci_reset(host, SDHCI_RESET_ALL);
475 
476 	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
477 		aligned_buffer = memalign(8, 512*1024);
478 		if (!aligned_buffer) {
479 			printf("%s: Aligned buffer alloc failed!!!\n",
480 			       __func__);
481 			return -ENOMEM;
482 		}
483 	}
484 
485 	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
486 
487 	if (host->quirks & SDHCI_QUIRK_NO_CD) {
488 #if defined(CONFIG_PIC32_SDHCI)
489 		/* PIC32 SDHCI CD errata:
490 		 * - set CD_TEST and clear CD_TEST_INS bit
491 		 */
492 		sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
493 #else
494 		unsigned int status;
495 
496 		sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
497 			SDHCI_HOST_CONTROL);
498 
499 		status = sdhci_readl(host, SDHCI_PRESENT_STATE);
500 		while ((!(status & SDHCI_CARD_PRESENT)) ||
501 		    (!(status & SDHCI_CARD_STATE_STABLE)) ||
502 		    (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
503 			status = sdhci_readl(host, SDHCI_PRESENT_STATE);
504 #endif
505 	}
506 
507 	/* Enable only interrupts served by the SD controller */
508 	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
509 		     SDHCI_INT_ENABLE);
510 	/* Mask all sdhci interrupt sources */
511 	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
512 
513 	return 0;
514 }
515 
516 #ifdef CONFIG_DM_MMC_OPS
517 int sdhci_probe(struct udevice *dev)
518 {
519 	struct mmc *mmc = mmc_get_mmc_dev(dev);
520 
521 	return sdhci_init(mmc);
522 }
523 
524 const struct dm_mmc_ops sdhci_ops = {
525 	.send_cmd	= sdhci_send_command,
526 	.set_ios	= sdhci_set_ios,
527 };
528 #else
529 static const struct mmc_ops sdhci_ops = {
530 	.send_cmd	= sdhci_send_command,
531 	.set_ios	= sdhci_set_ios,
532 	.init		= sdhci_init,
533 };
534 #endif
535 
536 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
537 		u32 max_clk, u32 min_clk)
538 {
539 	u32 caps, caps_1;
540 
541 	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
542 
543 #ifdef CONFIG_MMC_SDMA
544 	if (!(caps & SDHCI_CAN_DO_SDMA)) {
545 		printf("%s: Your controller doesn't support SDMA!!\n",
546 		       __func__);
547 		return -EINVAL;
548 	}
549 #endif
550 	if (host->quirks & SDHCI_QUIRK_REG32_RW)
551 		host->version =
552 			sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
553 	else
554 		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
555 
556 	cfg->name = host->name;
557 #ifndef CONFIG_DM_MMC_OPS
558 	cfg->ops = &sdhci_ops;
559 #endif
560 	if (max_clk)
561 		cfg->f_max = max_clk;
562 	else {
563 		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
564 			cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
565 				SDHCI_CLOCK_BASE_SHIFT;
566 		else
567 			cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
568 				SDHCI_CLOCK_BASE_SHIFT;
569 		cfg->f_max *= 1000000;
570 	}
571 	if (cfg->f_max == 0) {
572 		printf("%s: Hardware doesn't specify base clock frequency\n",
573 		       __func__);
574 		return -EINVAL;
575 	}
576 	if (min_clk)
577 		cfg->f_min = min_clk;
578 	else {
579 		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
580 			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
581 		else
582 			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
583 	}
584 	cfg->voltages = 0;
585 	if (caps & SDHCI_CAN_VDD_330)
586 		cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
587 	if (caps & SDHCI_CAN_VDD_300)
588 		cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
589 	if (caps & SDHCI_CAN_VDD_180)
590 		cfg->voltages |= MMC_VDD_165_195;
591 
592 	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
593 		cfg->voltages |= host->voltages;
594 
595 	cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
596 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
597 		if (caps & SDHCI_CAN_DO_8BIT)
598 			cfg->host_caps |= MMC_MODE_8BIT;
599 	}
600 
601 	if (host->host_caps)
602 		cfg->host_caps |= host->host_caps;
603 
604 
605 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
606 
607 	/*
608 	 * In case of Host Controller v3.00, find out whether clock
609 	 * multiplier is supported.
610 	 */
611 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
612 		caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
613 		host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
614 				SDHCI_CLOCK_MUL_SHIFT;
615 	}
616 
617 	return 0;
618 }
619 
620 #ifdef CONFIG_BLK
621 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
622 {
623 	return mmc_bind(dev, mmc, cfg);
624 }
625 #else
626 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
627 {
628 	int ret;
629 
630 	ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
631 	if (ret)
632 		return ret;
633 
634 	host->mmc = mmc_create(&host->cfg, host);
635 	if (host->mmc == NULL) {
636 		printf("%s: mmc create fail!\n", __func__);
637 		return -ENOMEM;
638 	}
639 
640 	return 0;
641 }
642 #endif
643