1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <sdhci.h> 16 17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; 19 #else 20 void *aligned_buffer; 21 #endif 22 23 static void sdhci_reset(struct sdhci_host *host, u8 mask) 24 { 25 unsigned long timeout; 26 27 /* Wait max 100 ms */ 28 timeout = 100; 29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 31 if (timeout == 0) { 32 printf("%s: Reset 0x%x never completed.\n", 33 __func__, (int)mask); 34 return; 35 } 36 timeout--; 37 udelay(1000); 38 } 39 } 40 41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 42 { 43 int i; 44 if (cmd->resp_type & MMC_RSP_136) { 45 /* CRC is stripped so we need to do some shifting. */ 46 for (i = 0; i < 4; i++) { 47 cmd->response[i] = sdhci_readl(host, 48 SDHCI_RESPONSE + (3-i)*4) << 8; 49 if (i != 3) 50 cmd->response[i] |= sdhci_readb(host, 51 SDHCI_RESPONSE + (3-i)*4-1); 52 } 53 } else { 54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 55 } 56 } 57 58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 59 { 60 int i; 61 char *offs; 62 for (i = 0; i < data->blocksize; i += 4) { 63 offs = data->dest + i; 64 if (data->flags == MMC_DATA_READ) 65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 66 else 67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 68 } 69 } 70 71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 72 unsigned int start_addr) 73 { 74 unsigned int stat, rdy, mask, timeout, block = 0; 75 #ifdef CONFIG_MMC_SDMA 76 unsigned char ctrl; 77 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 78 ctrl &= ~SDHCI_CTRL_DMA_MASK; 79 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 80 #endif 81 82 timeout = 1000000; 83 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 84 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 85 do { 86 stat = sdhci_readl(host, SDHCI_INT_STATUS); 87 if (stat & SDHCI_INT_ERROR) { 88 printf("%s: Error detected in status(0x%X)!\n", 89 __func__, stat); 90 return -1; 91 } 92 if (stat & rdy) { 93 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 94 continue; 95 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 96 sdhci_transfer_pio(host, data); 97 data->dest += data->blocksize; 98 if (++block >= data->blocks) 99 break; 100 } 101 #ifdef CONFIG_MMC_SDMA 102 if (stat & SDHCI_INT_DMA_END) { 103 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 104 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 105 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 106 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 107 } 108 #endif 109 if (timeout-- > 0) 110 udelay(10); 111 else { 112 printf("%s: Transfer data timeout\n", __func__); 113 return -1; 114 } 115 } while (!(stat & SDHCI_INT_DATA_END)); 116 return 0; 117 } 118 119 /* 120 * No command will be sent by driver if card is busy, so driver must wait 121 * for card ready state. 122 * Every time when card is busy after timeout then (last) timeout value will be 123 * increased twice but only if it doesn't exceed global defined maximum. 124 * Each function call will use last timeout value. Max timeout can be redefined 125 * in board config file. 126 */ 127 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT 128 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 129 #endif 130 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 131 #define SDHCI_READ_STATUS_TIMEOUT 1000 132 133 #ifdef CONFIG_DM_MMC_OPS 134 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, 135 struct mmc_data *data) 136 { 137 struct mmc *mmc = mmc_get_mmc_dev(dev); 138 139 #else 140 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 141 struct mmc_data *data) 142 { 143 #endif 144 struct sdhci_host *host = mmc->priv; 145 unsigned int stat = 0; 146 int ret = 0; 147 int trans_bytes = 0, is_aligned = 1; 148 u32 mask, flags, mode; 149 unsigned int time = 0, start_addr = 0; 150 int mmc_dev = mmc_get_blk_desc(mmc)->devnum; 151 unsigned start = get_timer(0); 152 153 /* Timeout unit - ms */ 154 static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; 155 156 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 157 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; 158 159 /* We shouldn't wait for data inihibit for stop commands, even 160 though they might use busy signaling */ 161 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 162 mask &= ~SDHCI_DATA_INHIBIT; 163 164 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 165 if (time >= cmd_timeout) { 166 printf("%s: MMC: %d busy ", __func__, mmc_dev); 167 if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) { 168 cmd_timeout += cmd_timeout; 169 printf("timeout increasing to: %u ms.\n", 170 cmd_timeout); 171 } else { 172 puts("timeout.\n"); 173 return COMM_ERR; 174 } 175 } 176 time++; 177 udelay(1000); 178 } 179 180 mask = SDHCI_INT_RESPONSE; 181 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 182 flags = SDHCI_CMD_RESP_NONE; 183 else if (cmd->resp_type & MMC_RSP_136) 184 flags = SDHCI_CMD_RESP_LONG; 185 else if (cmd->resp_type & MMC_RSP_BUSY) { 186 flags = SDHCI_CMD_RESP_SHORT_BUSY; 187 mask |= SDHCI_INT_DATA_END; 188 } else 189 flags = SDHCI_CMD_RESP_SHORT; 190 191 if (cmd->resp_type & MMC_RSP_CRC) 192 flags |= SDHCI_CMD_CRC; 193 if (cmd->resp_type & MMC_RSP_OPCODE) 194 flags |= SDHCI_CMD_INDEX; 195 if (data) 196 flags |= SDHCI_CMD_DATA; 197 198 /* Set Transfer mode regarding to data flag */ 199 if (data != 0) { 200 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 201 mode = SDHCI_TRNS_BLK_CNT_EN; 202 trans_bytes = data->blocks * data->blocksize; 203 if (data->blocks > 1) 204 mode |= SDHCI_TRNS_MULTI; 205 206 if (data->flags == MMC_DATA_READ) 207 mode |= SDHCI_TRNS_READ; 208 209 #ifdef CONFIG_MMC_SDMA 210 if (data->flags == MMC_DATA_READ) 211 start_addr = (unsigned long)data->dest; 212 else 213 start_addr = (unsigned long)data->src; 214 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 215 (start_addr & 0x7) != 0x0) { 216 is_aligned = 0; 217 start_addr = (unsigned long)aligned_buffer; 218 if (data->flags != MMC_DATA_READ) 219 memcpy(aligned_buffer, data->src, trans_bytes); 220 } 221 222 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 223 /* 224 * Always use this bounce-buffer when 225 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined 226 */ 227 is_aligned = 0; 228 start_addr = (unsigned long)aligned_buffer; 229 if (data->flags != MMC_DATA_READ) 230 memcpy(aligned_buffer, data->src, trans_bytes); 231 #endif 232 233 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 234 mode |= SDHCI_TRNS_DMA; 235 #endif 236 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 237 data->blocksize), 238 SDHCI_BLOCK_SIZE); 239 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 240 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 241 } else if (cmd->resp_type & MMC_RSP_BUSY) { 242 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 243 } 244 245 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 246 #ifdef CONFIG_MMC_SDMA 247 flush_cache(start_addr, trans_bytes); 248 #endif 249 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 250 start = get_timer(0); 251 do { 252 stat = sdhci_readl(host, SDHCI_INT_STATUS); 253 if (stat & SDHCI_INT_ERROR) 254 break; 255 } while (((stat & mask) != mask) && 256 (get_timer(start) < SDHCI_READ_STATUS_TIMEOUT)); 257 258 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { 259 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) 260 return 0; 261 else { 262 printf("%s: Timeout for status update!\n", __func__); 263 return TIMEOUT; 264 } 265 } 266 267 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 268 sdhci_cmd_done(host, cmd); 269 sdhci_writel(host, mask, SDHCI_INT_STATUS); 270 } else 271 ret = -1; 272 273 if (!ret && data) 274 ret = sdhci_transfer_data(host, data, start_addr); 275 276 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 277 udelay(1000); 278 279 stat = sdhci_readl(host, SDHCI_INT_STATUS); 280 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 281 if (!ret) { 282 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 283 !is_aligned && (data->flags == MMC_DATA_READ)) 284 memcpy(data->dest, aligned_buffer, trans_bytes); 285 return 0; 286 } 287 288 sdhci_reset(host, SDHCI_RESET_CMD); 289 sdhci_reset(host, SDHCI_RESET_DATA); 290 if (stat & SDHCI_INT_TIMEOUT) 291 return TIMEOUT; 292 else 293 return COMM_ERR; 294 } 295 296 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) 297 { 298 struct sdhci_host *host = mmc->priv; 299 unsigned int div, clk, timeout, reg; 300 301 /* Wait max 20 ms */ 302 timeout = 200; 303 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 304 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 305 if (timeout == 0) { 306 printf("%s: Timeout to wait cmd & data inhibit\n", 307 __func__); 308 return -1; 309 } 310 311 timeout--; 312 udelay(100); 313 } 314 315 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 316 reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); 317 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 318 319 if (clock == 0) 320 return 0; 321 322 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 323 /* Version 3.00 divisors must be a multiple of 2. */ 324 if (mmc->cfg->f_max <= clock) 325 div = 1; 326 else { 327 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { 328 if ((mmc->cfg->f_max / div) <= clock) 329 break; 330 } 331 } 332 } else { 333 /* Version 2.00 divisors must be a power of 2. */ 334 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 335 if ((mmc->cfg->f_max / div) <= clock) 336 break; 337 } 338 } 339 div >>= 1; 340 341 if (host->set_clock) 342 host->set_clock(host->index, div); 343 344 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 345 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 346 << SDHCI_DIVIDER_HI_SHIFT; 347 clk |= SDHCI_CLOCK_INT_EN; 348 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 349 350 /* Wait max 20 ms */ 351 timeout = 20; 352 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 353 & SDHCI_CLOCK_INT_STABLE)) { 354 if (timeout == 0) { 355 printf("%s: Internal clock never stabilised.\n", 356 __func__); 357 return -1; 358 } 359 timeout--; 360 udelay(1000); 361 } 362 363 clk |= SDHCI_CLOCK_CARD_EN; 364 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 365 return 0; 366 } 367 368 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 369 { 370 u8 pwr = 0; 371 372 if (power != (unsigned short)-1) { 373 switch (1 << power) { 374 case MMC_VDD_165_195: 375 pwr = SDHCI_POWER_180; 376 break; 377 case MMC_VDD_29_30: 378 case MMC_VDD_30_31: 379 pwr = SDHCI_POWER_300; 380 break; 381 case MMC_VDD_32_33: 382 case MMC_VDD_33_34: 383 pwr = SDHCI_POWER_330; 384 break; 385 } 386 } 387 388 if (pwr == 0) { 389 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 390 return; 391 } 392 393 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 394 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 395 396 pwr |= SDHCI_POWER_ON; 397 398 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 399 } 400 401 #ifdef CONFIG_DM_MMC_OPS 402 static int sdhci_set_ios(struct udevice *dev) 403 { 404 struct mmc *mmc = mmc_get_mmc_dev(dev); 405 #else 406 static void sdhci_set_ios(struct mmc *mmc) 407 { 408 #endif 409 u32 ctrl; 410 struct sdhci_host *host = mmc->priv; 411 412 if (host->set_control_reg) 413 host->set_control_reg(host); 414 415 if (mmc->clock != host->clock) 416 sdhci_set_clock(mmc, mmc->clock); 417 418 /* Set bus width */ 419 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 420 if (mmc->bus_width == 8) { 421 ctrl &= ~SDHCI_CTRL_4BITBUS; 422 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 423 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 424 ctrl |= SDHCI_CTRL_8BITBUS; 425 } else { 426 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 427 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 428 ctrl &= ~SDHCI_CTRL_8BITBUS; 429 if (mmc->bus_width == 4) 430 ctrl |= SDHCI_CTRL_4BITBUS; 431 else 432 ctrl &= ~SDHCI_CTRL_4BITBUS; 433 } 434 435 if (mmc->clock > 26000000) 436 ctrl |= SDHCI_CTRL_HISPD; 437 else 438 ctrl &= ~SDHCI_CTRL_HISPD; 439 440 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) 441 ctrl &= ~SDHCI_CTRL_HISPD; 442 443 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 444 #ifdef CONFIG_DM_MMC_OPS 445 return 0; 446 #endif 447 } 448 449 static int sdhci_init(struct mmc *mmc) 450 { 451 struct sdhci_host *host = mmc->priv; 452 453 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 454 aligned_buffer = memalign(8, 512*1024); 455 if (!aligned_buffer) { 456 printf("%s: Aligned buffer alloc failed!!!\n", 457 __func__); 458 return -1; 459 } 460 } 461 462 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 463 464 if (host->quirks & SDHCI_QUIRK_NO_CD) { 465 #if defined(CONFIG_PIC32_SDHCI) 466 /* PIC32 SDHCI CD errata: 467 * - set CD_TEST and clear CD_TEST_INS bit 468 */ 469 sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL); 470 #else 471 unsigned int status; 472 473 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, 474 SDHCI_HOST_CONTROL); 475 476 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 477 while ((!(status & SDHCI_CARD_PRESENT)) || 478 (!(status & SDHCI_CARD_STATE_STABLE)) || 479 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) 480 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 481 #endif 482 } 483 484 /* Enable only interrupts served by the SD controller */ 485 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 486 SDHCI_INT_ENABLE); 487 /* Mask all sdhci interrupt sources */ 488 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 489 490 return 0; 491 } 492 493 #ifdef CONFIG_DM_MMC_OPS 494 int sdhci_probe(struct udevice *dev) 495 { 496 struct mmc *mmc = mmc_get_mmc_dev(dev); 497 498 return sdhci_init(mmc); 499 } 500 501 const struct dm_mmc_ops sdhci_ops = { 502 .send_cmd = sdhci_send_command, 503 .set_ios = sdhci_set_ios, 504 }; 505 #else 506 static const struct mmc_ops sdhci_ops = { 507 .send_cmd = sdhci_send_command, 508 .set_ios = sdhci_set_ios, 509 .init = sdhci_init, 510 }; 511 #endif 512 513 int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, 514 uint caps, u32 max_clk, u32 min_clk, uint version, 515 uint quirks, uint host_caps) 516 { 517 cfg->name = name; 518 #ifndef CONFIG_DM_MMC_OPS 519 cfg->ops = &sdhci_ops; 520 #endif 521 if (max_clk) 522 cfg->f_max = max_clk; 523 else { 524 if (version >= SDHCI_SPEC_300) 525 cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 526 SDHCI_CLOCK_BASE_SHIFT; 527 else 528 cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >> 529 SDHCI_CLOCK_BASE_SHIFT; 530 cfg->f_max *= 1000000; 531 } 532 if (cfg->f_max == 0) 533 return -EINVAL; 534 if (min_clk) 535 cfg->f_min = min_clk; 536 else { 537 if (version >= SDHCI_SPEC_300) 538 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; 539 else 540 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; 541 } 542 cfg->voltages = 0; 543 if (caps & SDHCI_CAN_VDD_330) 544 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 545 if (caps & SDHCI_CAN_VDD_300) 546 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 547 if (caps & SDHCI_CAN_VDD_180) 548 cfg->voltages |= MMC_VDD_165_195; 549 550 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 551 if (version >= SDHCI_SPEC_300) { 552 if (caps & SDHCI_CAN_DO_8BIT) 553 cfg->host_caps |= MMC_MODE_8BIT; 554 } 555 556 if (quirks & SDHCI_QUIRK_NO_HISPD_BIT) 557 cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); 558 559 if (host_caps) 560 cfg->host_caps |= host_caps; 561 562 563 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 564 565 return 0; 566 } 567 568 #ifdef CONFIG_BLK 569 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 570 { 571 return mmc_bind(dev, mmc, cfg); 572 } 573 #else 574 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) 575 { 576 unsigned int caps; 577 578 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 579 #ifdef CONFIG_MMC_SDMA 580 if (!(caps & SDHCI_CAN_DO_SDMA)) { 581 printf("%s: Your controller doesn't support SDMA!!\n", 582 __func__); 583 return -1; 584 } 585 #endif 586 587 if (sdhci_setup_cfg(&host->cfg, host->name, host->bus_width, caps, 588 max_clk, min_clk, SDHCI_GET_VERSION(host), 589 host->quirks, host->host_caps)) { 590 printf("%s: Hardware doesn't specify base clock frequency\n", 591 __func__); 592 return -EINVAL; 593 } 594 595 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 596 host->cfg.voltages |= host->voltages; 597 598 sdhci_reset(host, SDHCI_RESET_ALL); 599 600 host->mmc = mmc_create(&host->cfg, host); 601 if (host->mmc == NULL) { 602 printf("%s: mmc create fail!\n", __func__); 603 return -1; 604 } 605 606 return 0; 607 } 608 #endif 609