1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <mmc.h> 14 #include <sdhci.h> 15 16 void *aligned_buffer; 17 18 static void sdhci_reset(struct sdhci_host *host, u8 mask) 19 { 20 unsigned long timeout; 21 22 /* Wait max 100 ms */ 23 timeout = 100; 24 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 25 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 26 if (timeout == 0) { 27 printf("%s: Reset 0x%x never completed.\n", 28 __func__, (int)mask); 29 return; 30 } 31 timeout--; 32 udelay(1000); 33 } 34 } 35 36 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 37 { 38 int i; 39 if (cmd->resp_type & MMC_RSP_136) { 40 /* CRC is stripped so we need to do some shifting. */ 41 for (i = 0; i < 4; i++) { 42 cmd->response[i] = sdhci_readl(host, 43 SDHCI_RESPONSE + (3-i)*4) << 8; 44 if (i != 3) 45 cmd->response[i] |= sdhci_readb(host, 46 SDHCI_RESPONSE + (3-i)*4-1); 47 } 48 } else { 49 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 50 } 51 } 52 53 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 54 { 55 int i; 56 char *offs; 57 for (i = 0; i < data->blocksize; i += 4) { 58 offs = data->dest + i; 59 if (data->flags == MMC_DATA_READ) 60 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 61 else 62 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 63 } 64 } 65 66 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 67 unsigned int start_addr) 68 { 69 unsigned int stat, rdy, mask, timeout, block = 0; 70 #ifdef CONFIG_MMC_SDMA 71 unsigned char ctrl; 72 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 73 ctrl &= ~SDHCI_CTRL_DMA_MASK; 74 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 75 #endif 76 77 timeout = 1000000; 78 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 79 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 80 do { 81 stat = sdhci_readl(host, SDHCI_INT_STATUS); 82 if (stat & SDHCI_INT_ERROR) { 83 printf("%s: Error detected in status(0x%X)!\n", 84 __func__, stat); 85 return -1; 86 } 87 if (stat & rdy) { 88 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 89 continue; 90 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 91 sdhci_transfer_pio(host, data); 92 data->dest += data->blocksize; 93 if (++block >= data->blocks) 94 break; 95 } 96 #ifdef CONFIG_MMC_SDMA 97 if (stat & SDHCI_INT_DMA_END) { 98 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 99 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 100 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 101 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 102 } 103 #endif 104 if (timeout-- > 0) 105 udelay(10); 106 else { 107 printf("%s: Transfer data timeout\n", __func__); 108 return -1; 109 } 110 } while (!(stat & SDHCI_INT_DATA_END)); 111 return 0; 112 } 113 114 /* 115 * No command will be sent by driver if card is busy, so driver must wait 116 * for card ready state. 117 * Every time when card is busy after timeout then (last) timeout value will be 118 * increased twice but only if it doesn't exceed global defined maximum. 119 * Each function call will use last timeout value. Max timeout can be redefined 120 * in board config file. 121 */ 122 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT 123 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 124 #endif 125 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 126 127 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 128 struct mmc_data *data) 129 { 130 struct sdhci_host *host = mmc->priv; 131 unsigned int stat = 0; 132 int ret = 0; 133 int trans_bytes = 0, is_aligned = 1; 134 u32 mask, flags, mode; 135 unsigned int time = 0, start_addr = 0; 136 unsigned int retry = 10000; 137 int mmc_dev = mmc->block_dev.dev; 138 139 /* Timeout unit - ms */ 140 static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; 141 142 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 143 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; 144 145 /* We shouldn't wait for data inihibit for stop commands, even 146 though they might use busy signaling */ 147 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 148 mask &= ~SDHCI_DATA_INHIBIT; 149 150 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 151 if (time >= cmd_timeout) { 152 printf("%s: MMC: %d busy ", __func__, mmc_dev); 153 if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) { 154 cmd_timeout += cmd_timeout; 155 printf("timeout increasing to: %u ms.\n", 156 cmd_timeout); 157 } else { 158 puts("timeout.\n"); 159 return COMM_ERR; 160 } 161 } 162 time++; 163 udelay(1000); 164 } 165 166 mask = SDHCI_INT_RESPONSE; 167 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 168 flags = SDHCI_CMD_RESP_NONE; 169 else if (cmd->resp_type & MMC_RSP_136) 170 flags = SDHCI_CMD_RESP_LONG; 171 else if (cmd->resp_type & MMC_RSP_BUSY) { 172 flags = SDHCI_CMD_RESP_SHORT_BUSY; 173 mask |= SDHCI_INT_DATA_END; 174 } else 175 flags = SDHCI_CMD_RESP_SHORT; 176 177 if (cmd->resp_type & MMC_RSP_CRC) 178 flags |= SDHCI_CMD_CRC; 179 if (cmd->resp_type & MMC_RSP_OPCODE) 180 flags |= SDHCI_CMD_INDEX; 181 if (data) 182 flags |= SDHCI_CMD_DATA; 183 184 /* Set Transfer mode regarding to data flag */ 185 if (data != 0) { 186 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 187 mode = SDHCI_TRNS_BLK_CNT_EN; 188 trans_bytes = data->blocks * data->blocksize; 189 if (data->blocks > 1) 190 mode |= SDHCI_TRNS_MULTI; 191 192 if (data->flags == MMC_DATA_READ) 193 mode |= SDHCI_TRNS_READ; 194 195 #ifdef CONFIG_MMC_SDMA 196 if (data->flags == MMC_DATA_READ) 197 start_addr = (unsigned long)data->dest; 198 else 199 start_addr = (unsigned long)data->src; 200 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 201 (start_addr & 0x7) != 0x0) { 202 is_aligned = 0; 203 start_addr = (unsigned long)aligned_buffer; 204 if (data->flags != MMC_DATA_READ) 205 memcpy(aligned_buffer, data->src, trans_bytes); 206 } 207 208 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 209 mode |= SDHCI_TRNS_DMA; 210 #endif 211 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 212 data->blocksize), 213 SDHCI_BLOCK_SIZE); 214 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 215 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 216 } else if (cmd->resp_type & MMC_RSP_BUSY) { 217 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 218 } 219 220 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 221 #ifdef CONFIG_MMC_SDMA 222 flush_cache(start_addr, trans_bytes); 223 #endif 224 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 225 do { 226 stat = sdhci_readl(host, SDHCI_INT_STATUS); 227 if (stat & SDHCI_INT_ERROR) 228 break; 229 if (--retry == 0) 230 break; 231 } while ((stat & mask) != mask); 232 233 if (retry == 0) { 234 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) 235 return 0; 236 else { 237 printf("%s: Timeout for status update!\n", __func__); 238 return TIMEOUT; 239 } 240 } 241 242 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 243 sdhci_cmd_done(host, cmd); 244 sdhci_writel(host, mask, SDHCI_INT_STATUS); 245 } else 246 ret = -1; 247 248 if (!ret && data) 249 ret = sdhci_transfer_data(host, data, start_addr); 250 251 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 252 udelay(1000); 253 254 stat = sdhci_readl(host, SDHCI_INT_STATUS); 255 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 256 if (!ret) { 257 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 258 !is_aligned && (data->flags == MMC_DATA_READ)) 259 memcpy(data->dest, aligned_buffer, trans_bytes); 260 return 0; 261 } 262 263 sdhci_reset(host, SDHCI_RESET_CMD); 264 sdhci_reset(host, SDHCI_RESET_DATA); 265 if (stat & SDHCI_INT_TIMEOUT) 266 return TIMEOUT; 267 else 268 return COMM_ERR; 269 } 270 271 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) 272 { 273 struct sdhci_host *host = mmc->priv; 274 unsigned int div, clk, timeout; 275 276 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 277 278 if (clock == 0) 279 return 0; 280 281 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 282 /* Version 3.00 divisors must be a multiple of 2. */ 283 if (mmc->cfg->f_max <= clock) 284 div = 1; 285 else { 286 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { 287 if ((mmc->cfg->f_max / div) <= clock) 288 break; 289 } 290 } 291 } else { 292 /* Version 2.00 divisors must be a power of 2. */ 293 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 294 if ((mmc->cfg->f_max / div) <= clock) 295 break; 296 } 297 } 298 div >>= 1; 299 300 if (host->set_clock) 301 host->set_clock(host->index, div); 302 303 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 304 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 305 << SDHCI_DIVIDER_HI_SHIFT; 306 clk |= SDHCI_CLOCK_INT_EN; 307 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 308 309 /* Wait max 20 ms */ 310 timeout = 20; 311 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 312 & SDHCI_CLOCK_INT_STABLE)) { 313 if (timeout == 0) { 314 printf("%s: Internal clock never stabilised.\n", 315 __func__); 316 return -1; 317 } 318 timeout--; 319 udelay(1000); 320 } 321 322 clk |= SDHCI_CLOCK_CARD_EN; 323 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 324 return 0; 325 } 326 327 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 328 { 329 u8 pwr = 0; 330 331 if (power != (unsigned short)-1) { 332 switch (1 << power) { 333 case MMC_VDD_165_195: 334 pwr = SDHCI_POWER_180; 335 break; 336 case MMC_VDD_29_30: 337 case MMC_VDD_30_31: 338 pwr = SDHCI_POWER_300; 339 break; 340 case MMC_VDD_32_33: 341 case MMC_VDD_33_34: 342 pwr = SDHCI_POWER_330; 343 break; 344 } 345 } 346 347 if (pwr == 0) { 348 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 349 return; 350 } 351 352 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 353 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 354 355 pwr |= SDHCI_POWER_ON; 356 357 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 358 } 359 360 static void sdhci_set_ios(struct mmc *mmc) 361 { 362 u32 ctrl; 363 struct sdhci_host *host = mmc->priv; 364 365 if (host->set_control_reg) 366 host->set_control_reg(host); 367 368 if (mmc->clock != host->clock) 369 sdhci_set_clock(mmc, mmc->clock); 370 371 /* Set bus width */ 372 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 373 if (mmc->bus_width == 8) { 374 ctrl &= ~SDHCI_CTRL_4BITBUS; 375 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 376 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 377 ctrl |= SDHCI_CTRL_8BITBUS; 378 } else { 379 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 380 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 381 ctrl &= ~SDHCI_CTRL_8BITBUS; 382 if (mmc->bus_width == 4) 383 ctrl |= SDHCI_CTRL_4BITBUS; 384 else 385 ctrl &= ~SDHCI_CTRL_4BITBUS; 386 } 387 388 if (mmc->clock > 26000000) 389 ctrl |= SDHCI_CTRL_HISPD; 390 else 391 ctrl &= ~SDHCI_CTRL_HISPD; 392 393 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) 394 ctrl &= ~SDHCI_CTRL_HISPD; 395 396 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 397 } 398 399 static int sdhci_init(struct mmc *mmc) 400 { 401 struct sdhci_host *host = mmc->priv; 402 403 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 404 aligned_buffer = memalign(8, 512*1024); 405 if (!aligned_buffer) { 406 printf("%s: Aligned buffer alloc failed!!!\n", 407 __func__); 408 return -1; 409 } 410 } 411 412 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 413 414 if (host->quirks & SDHCI_QUIRK_NO_CD) { 415 unsigned int status; 416 417 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, 418 SDHCI_HOST_CONTROL); 419 420 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 421 while ((!(status & SDHCI_CARD_PRESENT)) || 422 (!(status & SDHCI_CARD_STATE_STABLE)) || 423 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) 424 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 425 } 426 427 /* Enable only interrupts served by the SD controller */ 428 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 429 SDHCI_INT_ENABLE); 430 /* Mask all sdhci interrupt sources */ 431 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 432 433 return 0; 434 } 435 436 437 static const struct mmc_ops sdhci_ops = { 438 .send_cmd = sdhci_send_command, 439 .set_ios = sdhci_set_ios, 440 .init = sdhci_init, 441 }; 442 443 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) 444 { 445 unsigned int caps; 446 447 host->cfg.name = host->name; 448 host->cfg.ops = &sdhci_ops; 449 450 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 451 #ifdef CONFIG_MMC_SDMA 452 if (!(caps & SDHCI_CAN_DO_SDMA)) { 453 printf("%s: Your controller doesn't support SDMA!!\n", 454 __func__); 455 return -1; 456 } 457 #endif 458 459 if (max_clk) 460 host->cfg.f_max = max_clk; 461 else { 462 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 463 host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) 464 >> SDHCI_CLOCK_BASE_SHIFT; 465 else 466 host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) 467 >> SDHCI_CLOCK_BASE_SHIFT; 468 host->cfg.f_max *= 1000000; 469 } 470 if (host->cfg.f_max == 0) { 471 printf("%s: Hardware doesn't specify base clock frequency\n", 472 __func__); 473 return -1; 474 } 475 if (min_clk) 476 host->cfg.f_min = min_clk; 477 else { 478 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 479 host->cfg.f_min = host->cfg.f_max / 480 SDHCI_MAX_DIV_SPEC_300; 481 else 482 host->cfg.f_min = host->cfg.f_max / 483 SDHCI_MAX_DIV_SPEC_200; 484 } 485 486 host->cfg.voltages = 0; 487 if (caps & SDHCI_CAN_VDD_330) 488 host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 489 if (caps & SDHCI_CAN_VDD_300) 490 host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 491 if (caps & SDHCI_CAN_VDD_180) 492 host->cfg.voltages |= MMC_VDD_165_195; 493 494 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 495 host->cfg.voltages |= host->voltages; 496 497 host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 498 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 499 if (caps & SDHCI_CAN_DO_8BIT) 500 host->cfg.host_caps |= MMC_MODE_8BIT; 501 } 502 if (host->host_caps) 503 host->cfg.host_caps |= host->host_caps; 504 505 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 506 507 sdhci_reset(host, SDHCI_RESET_ALL); 508 509 host->mmc = mmc_create(&host->cfg, host); 510 if (host->mmc == NULL) { 511 printf("%s: mmc create fail!\n", __func__); 512 return -1; 513 } 514 515 return 0; 516 } 517