1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <mmc.h> 14 #include <sdhci.h> 15 16 void *aligned_buffer; 17 18 static void sdhci_reset(struct sdhci_host *host, u8 mask) 19 { 20 unsigned long timeout; 21 22 /* Wait max 100 ms */ 23 timeout = 100; 24 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 25 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 26 if (timeout == 0) { 27 printf("%s: Reset 0x%x never completed.\n", 28 __func__, (int)mask); 29 return; 30 } 31 timeout--; 32 udelay(1000); 33 } 34 } 35 36 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 37 { 38 int i; 39 if (cmd->resp_type & MMC_RSP_136) { 40 /* CRC is stripped so we need to do some shifting. */ 41 for (i = 0; i < 4; i++) { 42 cmd->response[i] = sdhci_readl(host, 43 SDHCI_RESPONSE + (3-i)*4) << 8; 44 if (i != 3) 45 cmd->response[i] |= sdhci_readb(host, 46 SDHCI_RESPONSE + (3-i)*4-1); 47 } 48 } else { 49 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 50 } 51 } 52 53 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 54 { 55 int i; 56 char *offs; 57 for (i = 0; i < data->blocksize; i += 4) { 58 offs = data->dest + i; 59 if (data->flags == MMC_DATA_READ) 60 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 61 else 62 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 63 } 64 } 65 66 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 67 unsigned int start_addr) 68 { 69 unsigned int stat, rdy, mask, timeout, block = 0; 70 #ifdef CONFIG_MMC_SDMA 71 unsigned char ctrl; 72 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 73 ctrl &= ~SDHCI_CTRL_DMA_MASK; 74 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 75 #endif 76 77 timeout = 1000000; 78 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 79 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 80 do { 81 stat = sdhci_readl(host, SDHCI_INT_STATUS); 82 if (stat & SDHCI_INT_ERROR) { 83 printf("%s: Error detected in status(0x%X)!\n", 84 __func__, stat); 85 return -1; 86 } 87 if (stat & rdy) { 88 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 89 continue; 90 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 91 sdhci_transfer_pio(host, data); 92 data->dest += data->blocksize; 93 if (++block >= data->blocks) 94 break; 95 } 96 #ifdef CONFIG_MMC_SDMA 97 if (stat & SDHCI_INT_DMA_END) { 98 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 99 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 100 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 101 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 102 } 103 #endif 104 if (timeout-- > 0) 105 udelay(10); 106 else { 107 printf("%s: Transfer data timeout\n", __func__); 108 return -1; 109 } 110 } while (!(stat & SDHCI_INT_DATA_END)); 111 return 0; 112 } 113 114 /* 115 * No command will be sent by driver if card is busy, so driver must wait 116 * for card ready state. 117 * Every time when card is busy after timeout then (last) timeout value will be 118 * increased twice but only if it doesn't exceed global defined maximum. 119 * Each function call will use last timeout value. Max timeout can be redefined 120 * in board config file. 121 */ 122 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT 123 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 124 #endif 125 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 126 127 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 128 struct mmc_data *data) 129 { 130 struct sdhci_host *host = mmc->priv; 131 unsigned int stat = 0; 132 int ret = 0; 133 int trans_bytes = 0, is_aligned = 1; 134 u32 mask, flags, mode; 135 unsigned int time = 0, start_addr = 0; 136 unsigned int retry = 10000; 137 int mmc_dev = mmc->block_dev.dev; 138 139 /* Timeout unit - ms */ 140 static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; 141 142 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 143 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; 144 145 /* We shouldn't wait for data inihibit for stop commands, even 146 though they might use busy signaling */ 147 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 148 mask &= ~SDHCI_DATA_INHIBIT; 149 150 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 151 if (time >= cmd_timeout) { 152 printf("%s: MMC: %d busy ", __func__, mmc_dev); 153 if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) { 154 cmd_timeout += cmd_timeout; 155 printf("timeout increasing to: %u ms.\n", 156 cmd_timeout); 157 } else { 158 puts("timeout.\n"); 159 return COMM_ERR; 160 } 161 } 162 time++; 163 udelay(1000); 164 } 165 166 mask = SDHCI_INT_RESPONSE; 167 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 168 flags = SDHCI_CMD_RESP_NONE; 169 else if (cmd->resp_type & MMC_RSP_136) 170 flags = SDHCI_CMD_RESP_LONG; 171 else if (cmd->resp_type & MMC_RSP_BUSY) { 172 flags = SDHCI_CMD_RESP_SHORT_BUSY; 173 mask |= SDHCI_INT_DATA_END; 174 } else 175 flags = SDHCI_CMD_RESP_SHORT; 176 177 if (cmd->resp_type & MMC_RSP_CRC) 178 flags |= SDHCI_CMD_CRC; 179 if (cmd->resp_type & MMC_RSP_OPCODE) 180 flags |= SDHCI_CMD_INDEX; 181 if (data) 182 flags |= SDHCI_CMD_DATA; 183 184 /* Set Transfer mode regarding to data flag */ 185 if (data != 0) { 186 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 187 mode = SDHCI_TRNS_BLK_CNT_EN; 188 trans_bytes = data->blocks * data->blocksize; 189 if (data->blocks > 1) 190 mode |= SDHCI_TRNS_MULTI; 191 192 if (data->flags == MMC_DATA_READ) 193 mode |= SDHCI_TRNS_READ; 194 195 #ifdef CONFIG_MMC_SDMA 196 if (data->flags == MMC_DATA_READ) 197 start_addr = (unsigned long)data->dest; 198 else 199 start_addr = (unsigned long)data->src; 200 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 201 (start_addr & 0x7) != 0x0) { 202 is_aligned = 0; 203 start_addr = (unsigned long)aligned_buffer; 204 if (data->flags != MMC_DATA_READ) 205 memcpy(aligned_buffer, data->src, trans_bytes); 206 } 207 208 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 209 mode |= SDHCI_TRNS_DMA; 210 #endif 211 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 212 data->blocksize), 213 SDHCI_BLOCK_SIZE); 214 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 215 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 216 } 217 218 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 219 #ifdef CONFIG_MMC_SDMA 220 flush_cache(start_addr, trans_bytes); 221 #endif 222 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 223 do { 224 stat = sdhci_readl(host, SDHCI_INT_STATUS); 225 if (stat & SDHCI_INT_ERROR) 226 break; 227 if (--retry == 0) 228 break; 229 } while ((stat & mask) != mask); 230 231 if (retry == 0) { 232 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) 233 return 0; 234 else { 235 printf("%s: Timeout for status update!\n", __func__); 236 return TIMEOUT; 237 } 238 } 239 240 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 241 sdhci_cmd_done(host, cmd); 242 sdhci_writel(host, mask, SDHCI_INT_STATUS); 243 } else 244 ret = -1; 245 246 if (!ret && data) 247 ret = sdhci_transfer_data(host, data, start_addr); 248 249 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 250 udelay(1000); 251 252 stat = sdhci_readl(host, SDHCI_INT_STATUS); 253 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 254 if (!ret) { 255 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 256 !is_aligned && (data->flags == MMC_DATA_READ)) 257 memcpy(data->dest, aligned_buffer, trans_bytes); 258 return 0; 259 } 260 261 sdhci_reset(host, SDHCI_RESET_CMD); 262 sdhci_reset(host, SDHCI_RESET_DATA); 263 if (stat & SDHCI_INT_TIMEOUT) 264 return TIMEOUT; 265 else 266 return COMM_ERR; 267 } 268 269 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) 270 { 271 struct sdhci_host *host = mmc->priv; 272 unsigned int div, clk, timeout; 273 274 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 275 276 if (clock == 0) 277 return 0; 278 279 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 280 /* Version 3.00 divisors must be a multiple of 2. */ 281 if (mmc->cfg->f_max <= clock) 282 div = 1; 283 else { 284 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { 285 if ((mmc->cfg->f_max / div) <= clock) 286 break; 287 } 288 } 289 } else { 290 /* Version 2.00 divisors must be a power of 2. */ 291 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 292 if ((mmc->cfg->f_max / div) <= clock) 293 break; 294 } 295 } 296 div >>= 1; 297 298 if (host->set_clock) 299 host->set_clock(host->index, div); 300 301 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 302 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 303 << SDHCI_DIVIDER_HI_SHIFT; 304 clk |= SDHCI_CLOCK_INT_EN; 305 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 306 307 /* Wait max 20 ms */ 308 timeout = 20; 309 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 310 & SDHCI_CLOCK_INT_STABLE)) { 311 if (timeout == 0) { 312 printf("%s: Internal clock never stabilised.\n", 313 __func__); 314 return -1; 315 } 316 timeout--; 317 udelay(1000); 318 } 319 320 clk |= SDHCI_CLOCK_CARD_EN; 321 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 322 return 0; 323 } 324 325 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 326 { 327 u8 pwr = 0; 328 329 if (power != (unsigned short)-1) { 330 switch (1 << power) { 331 case MMC_VDD_165_195: 332 pwr = SDHCI_POWER_180; 333 break; 334 case MMC_VDD_29_30: 335 case MMC_VDD_30_31: 336 pwr = SDHCI_POWER_300; 337 break; 338 case MMC_VDD_32_33: 339 case MMC_VDD_33_34: 340 pwr = SDHCI_POWER_330; 341 break; 342 } 343 } 344 345 if (pwr == 0) { 346 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 347 return; 348 } 349 350 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 351 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 352 353 pwr |= SDHCI_POWER_ON; 354 355 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 356 } 357 358 static void sdhci_set_ios(struct mmc *mmc) 359 { 360 u32 ctrl; 361 struct sdhci_host *host = mmc->priv; 362 363 if (host->set_control_reg) 364 host->set_control_reg(host); 365 366 if (mmc->clock != host->clock) 367 sdhci_set_clock(mmc, mmc->clock); 368 369 /* Set bus width */ 370 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 371 if (mmc->bus_width == 8) { 372 ctrl &= ~SDHCI_CTRL_4BITBUS; 373 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 374 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 375 ctrl |= SDHCI_CTRL_8BITBUS; 376 } else { 377 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 378 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 379 ctrl &= ~SDHCI_CTRL_8BITBUS; 380 if (mmc->bus_width == 4) 381 ctrl |= SDHCI_CTRL_4BITBUS; 382 else 383 ctrl &= ~SDHCI_CTRL_4BITBUS; 384 } 385 386 if (mmc->clock > 26000000) 387 ctrl |= SDHCI_CTRL_HISPD; 388 else 389 ctrl &= ~SDHCI_CTRL_HISPD; 390 391 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) 392 ctrl &= ~SDHCI_CTRL_HISPD; 393 394 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 395 } 396 397 static int sdhci_init(struct mmc *mmc) 398 { 399 struct sdhci_host *host = mmc->priv; 400 401 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 402 aligned_buffer = memalign(8, 512*1024); 403 if (!aligned_buffer) { 404 printf("%s: Aligned buffer alloc failed!!!\n", 405 __func__); 406 return -1; 407 } 408 } 409 410 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 411 412 if (host->quirks & SDHCI_QUIRK_NO_CD) { 413 unsigned int status; 414 415 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, 416 SDHCI_HOST_CONTROL); 417 418 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 419 while ((!(status & SDHCI_CARD_PRESENT)) || 420 (!(status & SDHCI_CARD_STATE_STABLE)) || 421 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) 422 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 423 } 424 425 /* Enable only interrupts served by the SD controller */ 426 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 427 SDHCI_INT_ENABLE); 428 /* Mask all sdhci interrupt sources */ 429 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 430 431 return 0; 432 } 433 434 435 static const struct mmc_ops sdhci_ops = { 436 .send_cmd = sdhci_send_command, 437 .set_ios = sdhci_set_ios, 438 .init = sdhci_init, 439 }; 440 441 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) 442 { 443 unsigned int caps; 444 445 host->cfg.name = host->name; 446 host->cfg.ops = &sdhci_ops; 447 448 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 449 #ifdef CONFIG_MMC_SDMA 450 if (!(caps & SDHCI_CAN_DO_SDMA)) { 451 printf("%s: Your controller doesn't support SDMA!!\n", 452 __func__); 453 return -1; 454 } 455 #endif 456 457 if (max_clk) 458 host->cfg.f_max = max_clk; 459 else { 460 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 461 host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) 462 >> SDHCI_CLOCK_BASE_SHIFT; 463 else 464 host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) 465 >> SDHCI_CLOCK_BASE_SHIFT; 466 host->cfg.f_max *= 1000000; 467 } 468 if (host->cfg.f_max == 0) { 469 printf("%s: Hardware doesn't specify base clock frequency\n", 470 __func__); 471 return -1; 472 } 473 if (min_clk) 474 host->cfg.f_min = min_clk; 475 else { 476 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 477 host->cfg.f_min = host->cfg.f_max / 478 SDHCI_MAX_DIV_SPEC_300; 479 else 480 host->cfg.f_min = host->cfg.f_max / 481 SDHCI_MAX_DIV_SPEC_200; 482 } 483 484 host->cfg.voltages = 0; 485 if (caps & SDHCI_CAN_VDD_330) 486 host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 487 if (caps & SDHCI_CAN_VDD_300) 488 host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 489 if (caps & SDHCI_CAN_VDD_180) 490 host->cfg.voltages |= MMC_VDD_165_195; 491 492 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 493 host->cfg.voltages |= host->voltages; 494 495 host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 496 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 497 if (caps & SDHCI_CAN_DO_8BIT) 498 host->cfg.host_caps |= MMC_MODE_8BIT; 499 } 500 if (host->host_caps) 501 host->cfg.host_caps |= host->host_caps; 502 503 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 504 505 sdhci_reset(host, SDHCI_RESET_ALL); 506 507 host->mmc = mmc_create(&host->cfg, host); 508 if (host->mmc == NULL) { 509 printf("%s: mmc create fail!\n", __func__); 510 return -1; 511 } 512 513 return 0; 514 } 515