1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 SAMSUNG Electronics 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <malloc.h> 10 #include <sdhci.h> 11 #include <fdtdec.h> 12 #include <linux/libfdt.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/mmc.h> 15 #include <asm/arch/clk.h> 16 #include <errno.h> 17 #include <asm/arch/pinmux.h> 18 19 #ifdef CONFIG_DM_MMC 20 struct s5p_sdhci_plat { 21 struct mmc_config cfg; 22 struct mmc mmc; 23 }; 24 25 DECLARE_GLOBAL_DATA_PTR; 26 #endif 27 28 static char *S5P_NAME = "SAMSUNG SDHCI"; 29 static void s5p_sdhci_set_control_reg(struct sdhci_host *host) 30 { 31 unsigned long val, ctrl; 32 /* 33 * SELCLKPADDS[17:16] 34 * 00 = 2mA 35 * 01 = 4mA 36 * 10 = 7mA 37 * 11 = 9mA 38 */ 39 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); 40 41 val = sdhci_readl(host, SDHCI_CONTROL2); 42 val &= SDHCI_CTRL2_SELBASECLK_MASK(3); 43 44 val |= SDHCI_CTRL2_ENSTAASYNCCLR | 45 SDHCI_CTRL2_ENCMDCNFMSK | 46 SDHCI_CTRL2_ENFBCLKRX | 47 SDHCI_CTRL2_ENCLKOUTHOLD; 48 49 sdhci_writel(host, val, SDHCI_CONTROL2); 50 51 /* 52 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7] 53 * FCSel[1:0] : Rx Feedback Clock Delay Control 54 * Inverter delay means10ns delay if SDCLK 50MHz setting 55 * 01 = Delay1 (basic delay) 56 * 11 = Delay2 (basic delay + 2ns) 57 * 00 = Delay3 (inverter delay) 58 * 10 = Delay4 (inverter delay + 2ns) 59 */ 60 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1; 61 sdhci_writel(host, val, SDHCI_CONTROL3); 62 63 /* 64 * SELBASECLK[5:4] 65 * 00/01 = HCLK 66 * 10 = EPLL 67 * 11 = XTI or XEXTCLK 68 */ 69 ctrl = sdhci_readl(host, SDHCI_CONTROL2); 70 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3); 71 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2); 72 sdhci_writel(host, ctrl, SDHCI_CONTROL2); 73 } 74 75 static void s5p_set_clock(struct sdhci_host *host, u32 div) 76 { 77 /* ToDo : Use the Clock Framework */ 78 set_mmc_clk(host->index, div); 79 } 80 81 static const struct sdhci_ops s5p_sdhci_ops = { 82 .set_clock = &s5p_set_clock, 83 .set_control_reg = &s5p_sdhci_set_control_reg, 84 }; 85 86 static int s5p_sdhci_core_init(struct sdhci_host *host) 87 { 88 host->name = S5P_NAME; 89 90 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | 91 SDHCI_QUIRK_32BIT_DMA_ADDR | 92 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; 93 host->max_clk = 52000000; 94 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 95 host->ops = &s5p_sdhci_ops; 96 97 if (host->bus_width == 8) 98 host->host_caps |= MMC_MODE_8BIT; 99 100 #ifndef CONFIG_BLK 101 return add_sdhci(host, 0, 400000); 102 #else 103 return 0; 104 #endif 105 } 106 107 int s5p_sdhci_init(u32 regbase, int index, int bus_width) 108 { 109 struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host)); 110 if (!host) { 111 printf("sdhci__host allocation fail!\n"); 112 return -ENOMEM; 113 } 114 host->ioaddr = (void *)regbase; 115 host->index = index; 116 host->bus_width = bus_width; 117 118 return s5p_sdhci_core_init(host); 119 } 120 121 static int do_sdhci_init(struct sdhci_host *host) 122 { 123 int dev_id, flag, ret; 124 125 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 126 dev_id = host->index + PERIPH_ID_SDMMC0; 127 128 ret = exynos_pinmux_config(dev_id, flag); 129 if (ret) { 130 printf("external SD not configured\n"); 131 return ret; 132 } 133 134 if (dm_gpio_is_valid(&host->pwr_gpio)) { 135 dm_gpio_set_value(&host->pwr_gpio, 1); 136 ret = exynos_pinmux_config(dev_id, flag); 137 if (ret) { 138 debug("MMC not configured\n"); 139 return ret; 140 } 141 } 142 143 if (dm_gpio_is_valid(&host->cd_gpio)) { 144 ret = dm_gpio_get_value(&host->cd_gpio); 145 if (ret) { 146 debug("no SD card detected (%d)\n", ret); 147 return -ENODEV; 148 } 149 } 150 151 return s5p_sdhci_core_init(host); 152 } 153 154 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) 155 { 156 int bus_width, dev_id; 157 unsigned int base; 158 159 /* Get device id */ 160 dev_id = pinmux_decode_periph_id(blob, node); 161 if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) { 162 debug("MMC: Can't get device id\n"); 163 return -EINVAL; 164 } 165 host->index = dev_id - PERIPH_ID_SDMMC0; 166 167 /* Get bus width */ 168 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 169 if (bus_width <= 0) { 170 debug("MMC: Can't get bus-width\n"); 171 return -EINVAL; 172 } 173 host->bus_width = bus_width; 174 175 /* Get the base address from the device node */ 176 base = fdtdec_get_addr(blob, node, "reg"); 177 if (!base) { 178 debug("MMC: Can't get base address\n"); 179 return -EINVAL; 180 } 181 host->ioaddr = (void *)base; 182 183 gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0, 184 &host->pwr_gpio, GPIOD_IS_OUT); 185 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0, 186 &host->cd_gpio, GPIOD_IS_IN); 187 188 return 0; 189 } 190 191 #ifdef CONFIG_DM_MMC 192 static int s5p_sdhci_probe(struct udevice *dev) 193 { 194 struct s5p_sdhci_plat *plat = dev_get_platdata(dev); 195 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 196 struct sdhci_host *host = dev_get_priv(dev); 197 int ret; 198 199 ret = sdhci_get_config(gd->fdt_blob, dev_of_offset(dev), host); 200 if (ret) 201 return ret; 202 203 ret = do_sdhci_init(host); 204 if (ret) 205 return ret; 206 207 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000); 208 if (ret) 209 return ret; 210 211 host->mmc = &plat->mmc; 212 host->mmc->priv = host; 213 host->mmc->dev = dev; 214 upriv->mmc = host->mmc; 215 216 return sdhci_probe(dev); 217 } 218 219 static int s5p_sdhci_bind(struct udevice *dev) 220 { 221 struct s5p_sdhci_plat *plat = dev_get_platdata(dev); 222 int ret; 223 224 ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); 225 if (ret) 226 return ret; 227 228 return 0; 229 } 230 231 static const struct udevice_id s5p_sdhci_ids[] = { 232 { .compatible = "samsung,exynos4412-sdhci"}, 233 { } 234 }; 235 236 U_BOOT_DRIVER(s5p_sdhci_drv) = { 237 .name = "s5p_sdhci", 238 .id = UCLASS_MMC, 239 .of_match = s5p_sdhci_ids, 240 .bind = s5p_sdhci_bind, 241 .ops = &sdhci_ops, 242 .probe = s5p_sdhci_probe, 243 .priv_auto_alloc_size = sizeof(struct sdhci_host), 244 .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat), 245 }; 246 #endif /* CONFIG_DM_MMC */ 247