1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <malloc.h> 11 #include <sdhci.h> 12 #include <fdtdec.h> 13 #include <libfdt.h> 14 #include <asm/gpio.h> 15 #include <asm/arch/mmc.h> 16 #include <asm/arch/clk.h> 17 #include <errno.h> 18 #include <asm/arch/pinmux.h> 19 20 #ifdef CONFIG_DM_MMC 21 struct s5p_sdhci_plat { 22 struct mmc_config cfg; 23 struct mmc mmc; 24 }; 25 26 DECLARE_GLOBAL_DATA_PTR; 27 #endif 28 29 static char *S5P_NAME = "SAMSUNG SDHCI"; 30 static void s5p_sdhci_set_control_reg(struct sdhci_host *host) 31 { 32 unsigned long val, ctrl; 33 /* 34 * SELCLKPADDS[17:16] 35 * 00 = 2mA 36 * 01 = 4mA 37 * 10 = 7mA 38 * 11 = 9mA 39 */ 40 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); 41 42 val = sdhci_readl(host, SDHCI_CONTROL2); 43 val &= SDHCI_CTRL2_SELBASECLK_MASK(3); 44 45 val |= SDHCI_CTRL2_ENSTAASYNCCLR | 46 SDHCI_CTRL2_ENCMDCNFMSK | 47 SDHCI_CTRL2_ENFBCLKRX | 48 SDHCI_CTRL2_ENCLKOUTHOLD; 49 50 sdhci_writel(host, val, SDHCI_CONTROL2); 51 52 /* 53 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7] 54 * FCSel[1:0] : Rx Feedback Clock Delay Control 55 * Inverter delay means10ns delay if SDCLK 50MHz setting 56 * 01 = Delay1 (basic delay) 57 * 11 = Delay2 (basic delay + 2ns) 58 * 00 = Delay3 (inverter delay) 59 * 10 = Delay4 (inverter delay + 2ns) 60 */ 61 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1; 62 sdhci_writel(host, val, SDHCI_CONTROL3); 63 64 /* 65 * SELBASECLK[5:4] 66 * 00/01 = HCLK 67 * 10 = EPLL 68 * 11 = XTI or XEXTCLK 69 */ 70 ctrl = sdhci_readl(host, SDHCI_CONTROL2); 71 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3); 72 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2); 73 sdhci_writel(host, ctrl, SDHCI_CONTROL2); 74 } 75 76 static void s5p_set_clock(struct sdhci_host *host, u32 div) 77 { 78 /* ToDo : Use the Clock Framework */ 79 set_mmc_clk(host->index, div); 80 } 81 82 static const struct sdhci_ops s5p_sdhci_ops = { 83 .set_clock = &s5p_set_clock, 84 .set_control_reg = &s5p_sdhci_set_control_reg, 85 }; 86 87 static int s5p_sdhci_core_init(struct sdhci_host *host) 88 { 89 host->name = S5P_NAME; 90 91 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | 92 SDHCI_QUIRK_32BIT_DMA_ADDR | 93 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; 94 host->max_clk = 52000000; 95 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 96 host->ops = &s5p_sdhci_ops; 97 98 if (host->bus_width == 8) 99 host->host_caps |= MMC_MODE_8BIT; 100 101 #ifndef CONFIG_BLK 102 return add_sdhci(host, 0, 400000); 103 #else 104 return 0; 105 #endif 106 } 107 108 int s5p_sdhci_init(u32 regbase, int index, int bus_width) 109 { 110 struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host)); 111 if (!host) { 112 printf("sdhci__host allocation fail!\n"); 113 return -ENOMEM; 114 } 115 host->ioaddr = (void *)regbase; 116 host->index = index; 117 host->bus_width = bus_width; 118 119 return s5p_sdhci_core_init(host); 120 } 121 122 #if CONFIG_IS_ENABLED(OF_CONTROL) 123 struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; 124 125 static int do_sdhci_init(struct sdhci_host *host) 126 { 127 int dev_id, flag, ret; 128 129 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 130 dev_id = host->index + PERIPH_ID_SDMMC0; 131 132 ret = exynos_pinmux_config(dev_id, flag); 133 if (ret) { 134 printf("external SD not configured\n"); 135 return ret; 136 } 137 138 if (dm_gpio_is_valid(&host->pwr_gpio)) { 139 dm_gpio_set_value(&host->pwr_gpio, 1); 140 ret = exynos_pinmux_config(dev_id, flag); 141 if (ret) { 142 debug("MMC not configured\n"); 143 return ret; 144 } 145 } 146 147 if (dm_gpio_is_valid(&host->cd_gpio)) { 148 ret = dm_gpio_get_value(&host->cd_gpio); 149 if (ret) { 150 debug("no SD card detected (%d)\n", ret); 151 return -ENODEV; 152 } 153 } 154 155 return s5p_sdhci_core_init(host); 156 } 157 158 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) 159 { 160 int bus_width, dev_id; 161 unsigned int base; 162 163 /* Get device id */ 164 dev_id = pinmux_decode_periph_id(blob, node); 165 if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) { 166 debug("MMC: Can't get device id\n"); 167 return -EINVAL; 168 } 169 host->index = dev_id - PERIPH_ID_SDMMC0; 170 171 /* Get bus width */ 172 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 173 if (bus_width <= 0) { 174 debug("MMC: Can't get bus-width\n"); 175 return -EINVAL; 176 } 177 host->bus_width = bus_width; 178 179 /* Get the base address from the device node */ 180 base = fdtdec_get_addr(blob, node, "reg"); 181 if (!base) { 182 debug("MMC: Can't get base address\n"); 183 return -EINVAL; 184 } 185 host->ioaddr = (void *)base; 186 187 gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0, 188 &host->pwr_gpio, GPIOD_IS_OUT); 189 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0, 190 &host->cd_gpio, GPIOD_IS_IN); 191 192 return 0; 193 } 194 195 static int process_nodes(const void *blob, int node_list[], int count) 196 { 197 struct sdhci_host *host; 198 int i, node, ret; 199 int failed = 0; 200 201 debug("%s: count = %d\n", __func__, count); 202 203 /* build sdhci_host[] for each controller */ 204 for (i = 0; i < count; i++) { 205 node = node_list[i]; 206 if (node <= 0) 207 continue; 208 209 host = &sdhci_host[i]; 210 211 ret = sdhci_get_config(blob, node, host); 212 if (ret) { 213 printf("%s: failed to decode dev %d (%d)\n", __func__, i, ret); 214 failed++; 215 continue; 216 } 217 218 ret = do_sdhci_init(host); 219 if (ret && ret != -ENODEV) { 220 printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret); 221 failed++; 222 } 223 } 224 225 /* we only consider it an error when all nodes fail */ 226 return (failed == count ? -1 : 0); 227 } 228 229 int exynos_mmc_init(const void *blob) 230 { 231 int count; 232 int node_list[SDHCI_MAX_HOSTS]; 233 234 count = fdtdec_find_aliases_for_id(blob, "mmc", 235 COMPAT_SAMSUNG_EXYNOS_MMC, node_list, 236 SDHCI_MAX_HOSTS); 237 238 return process_nodes(blob, node_list, count); 239 } 240 #endif 241 242 #ifdef CONFIG_DM_MMC 243 static int s5p_sdhci_probe(struct udevice *dev) 244 { 245 struct s5p_sdhci_plat *plat = dev_get_platdata(dev); 246 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 247 struct sdhci_host *host = dev_get_priv(dev); 248 int ret; 249 250 ret = sdhci_get_config(gd->fdt_blob, dev_of_offset(dev), host); 251 if (ret) 252 return ret; 253 254 ret = do_sdhci_init(host); 255 if (ret) 256 return ret; 257 258 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000); 259 if (ret) 260 return ret; 261 262 host->mmc = &plat->mmc; 263 host->mmc->priv = host; 264 host->mmc->dev = dev; 265 upriv->mmc = host->mmc; 266 267 return sdhci_probe(dev); 268 } 269 270 static int s5p_sdhci_bind(struct udevice *dev) 271 { 272 struct s5p_sdhci_plat *plat = dev_get_platdata(dev); 273 int ret; 274 275 ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); 276 if (ret) 277 return ret; 278 279 return 0; 280 } 281 282 static const struct udevice_id s5p_sdhci_ids[] = { 283 { .compatible = "samsung,exynos4412-sdhci"}, 284 { } 285 }; 286 287 U_BOOT_DRIVER(s5p_sdhci_drv) = { 288 .name = "s5p_sdhci", 289 .id = UCLASS_MMC, 290 .of_match = s5p_sdhci_ids, 291 .bind = s5p_sdhci_bind, 292 .ops = &sdhci_ops, 293 .probe = s5p_sdhci_probe, 294 .priv_auto_alloc_size = sizeof(struct sdhci_host), 295 .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat), 296 }; 297 #endif /* CONFIG_DM_MMC */ 298