1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <malloc.h> 10 #include <sdhci.h> 11 #include <fdtdec.h> 12 #include <libfdt.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/mmc.h> 15 #include <asm/arch/clk.h> 16 #include <errno.h> 17 #include <asm/arch/pinmux.h> 18 19 static char *S5P_NAME = "SAMSUNG SDHCI"; 20 static void s5p_sdhci_set_control_reg(struct sdhci_host *host) 21 { 22 unsigned long val, ctrl; 23 /* 24 * SELCLKPADDS[17:16] 25 * 00 = 2mA 26 * 01 = 4mA 27 * 10 = 7mA 28 * 11 = 9mA 29 */ 30 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); 31 32 val = sdhci_readl(host, SDHCI_CONTROL2); 33 val &= SDHCI_CTRL2_SELBASECLK_SHIFT; 34 35 val |= SDHCI_CTRL2_ENSTAASYNCCLR | 36 SDHCI_CTRL2_ENCMDCNFMSK | 37 SDHCI_CTRL2_ENFBCLKRX | 38 SDHCI_CTRL2_ENCLKOUTHOLD; 39 40 sdhci_writel(host, val, SDHCI_CONTROL2); 41 42 /* 43 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7] 44 * FCSel[1:0] : Rx Feedback Clock Delay Control 45 * Inverter delay means10ns delay if SDCLK 50MHz setting 46 * 01 = Delay1 (basic delay) 47 * 11 = Delay2 (basic delay + 2ns) 48 * 00 = Delay3 (inverter delay) 49 * 10 = Delay4 (inverter delay + 2ns) 50 */ 51 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1; 52 sdhci_writel(host, val, SDHCI_CONTROL3); 53 54 /* 55 * SELBASECLK[5:4] 56 * 00/01 = HCLK 57 * 10 = EPLL 58 * 11 = XTI or XEXTCLK 59 */ 60 ctrl = sdhci_readl(host, SDHCI_CONTROL2); 61 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3); 62 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2); 63 sdhci_writel(host, ctrl, SDHCI_CONTROL2); 64 } 65 66 static int s5p_sdhci_core_init(struct sdhci_host *host) 67 { 68 host->name = S5P_NAME; 69 70 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | 71 SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | 72 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; 73 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 74 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 75 76 host->set_control_reg = &s5p_sdhci_set_control_reg; 77 host->set_clock = set_mmc_clk; 78 79 host->host_caps = MMC_MODE_HC; 80 if (host->bus_width == 8) 81 host->host_caps |= MMC_MODE_8BIT; 82 83 return add_sdhci(host, 52000000, 400000); 84 } 85 86 int s5p_sdhci_init(u32 regbase, int index, int bus_width) 87 { 88 struct sdhci_host *host = malloc(sizeof(struct sdhci_host)); 89 if (!host) { 90 printf("sdhci__host malloc fail!\n"); 91 return 1; 92 } 93 host->ioaddr = (void *)regbase; 94 host->index = index; 95 host->bus_width = bus_width; 96 97 return s5p_sdhci_core_init(host); 98 } 99 100 #ifdef CONFIG_OF_CONTROL 101 struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; 102 103 static int do_sdhci_init(struct sdhci_host *host) 104 { 105 int dev_id, flag; 106 int err = 0; 107 108 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 109 dev_id = host->index + PERIPH_ID_SDMMC0; 110 111 if (dm_gpio_is_valid(&host->pwr_gpio)) { 112 dm_gpio_set_value(&host->pwr_gpio, 1); 113 err = exynos_pinmux_config(dev_id, flag); 114 if (err) { 115 debug("MMC not configured\n"); 116 return err; 117 } 118 } 119 120 if (dm_gpio_is_valid(&host->cd_gpio)) { 121 if (dm_gpio_get_value(&host->cd_gpio)) 122 return -ENODEV; 123 124 err = exynos_pinmux_config(dev_id, flag); 125 if (err) { 126 printf("external SD not configured\n"); 127 return err; 128 } 129 } 130 131 return s5p_sdhci_core_init(host); 132 } 133 134 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) 135 { 136 int bus_width, dev_id; 137 unsigned int base; 138 139 /* Get device id */ 140 dev_id = pinmux_decode_periph_id(blob, node); 141 if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) { 142 debug("MMC: Can't get device id\n"); 143 return -1; 144 } 145 host->index = dev_id - PERIPH_ID_SDMMC0; 146 147 /* Get bus width */ 148 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 149 if (bus_width <= 0) { 150 debug("MMC: Can't get bus-width\n"); 151 return -1; 152 } 153 host->bus_width = bus_width; 154 155 /* Get the base address from the device node */ 156 base = fdtdec_get_addr(blob, node, "reg"); 157 if (!base) { 158 debug("MMC: Can't get base address\n"); 159 return -1; 160 } 161 host->ioaddr = (void *)base; 162 163 gpio_request_by_name_nodev(blob, node, "pwr-gpios", 0, &host->pwr_gpio, 164 GPIOD_IS_OUT); 165 gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio, 166 GPIOD_IS_IN); 167 168 return 0; 169 } 170 171 static int process_nodes(const void *blob, int node_list[], int count) 172 { 173 struct sdhci_host *host; 174 int i, node; 175 176 debug("%s: count = %d\n", __func__, count); 177 178 /* build sdhci_host[] for each controller */ 179 for (i = 0; i < count; i++) { 180 node = node_list[i]; 181 if (node <= 0) 182 continue; 183 184 host = &sdhci_host[i]; 185 186 if (sdhci_get_config(blob, node, host)) { 187 printf("%s: failed to decode dev %d\n", __func__, i); 188 return -1; 189 } 190 do_sdhci_init(host); 191 } 192 return 0; 193 } 194 195 int exynos_mmc_init(const void *blob) 196 { 197 int count; 198 int node_list[SDHCI_MAX_HOSTS]; 199 200 count = fdtdec_find_aliases_for_id(blob, "mmc", 201 COMPAT_SAMSUNG_EXYNOS_MMC, node_list, 202 SDHCI_MAX_HOSTS); 203 204 process_nodes(blob, node_list, count); 205 206 return 1; 207 } 208 #endif 209