1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 SAMSUNG Electronics 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <malloc.h> 10 #include <sdhci.h> 11 #include <fdtdec.h> 12 #include <linux/libfdt.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/mmc.h> 15 #include <asm/arch/clk.h> 16 #include <errno.h> 17 #include <asm/arch/pinmux.h> 18 19 #ifdef CONFIG_DM_MMC 20 struct s5p_sdhci_plat { 21 struct mmc_config cfg; 22 struct mmc mmc; 23 }; 24 25 DECLARE_GLOBAL_DATA_PTR; 26 #endif 27 28 static char *S5P_NAME = "SAMSUNG SDHCI"; 29 static void s5p_sdhci_set_control_reg(struct sdhci_host *host) 30 { 31 unsigned long val, ctrl; 32 /* 33 * SELCLKPADDS[17:16] 34 * 00 = 2mA 35 * 01 = 4mA 36 * 10 = 7mA 37 * 11 = 9mA 38 */ 39 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); 40 41 val = sdhci_readl(host, SDHCI_CONTROL2); 42 val &= SDHCI_CTRL2_SELBASECLK_MASK(3); 43 44 val |= SDHCI_CTRL2_ENSTAASYNCCLR | 45 SDHCI_CTRL2_ENCMDCNFMSK | 46 SDHCI_CTRL2_ENFBCLKRX | 47 SDHCI_CTRL2_ENCLKOUTHOLD; 48 49 sdhci_writel(host, val, SDHCI_CONTROL2); 50 51 /* 52 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7] 53 * FCSel[1:0] : Rx Feedback Clock Delay Control 54 * Inverter delay means10ns delay if SDCLK 50MHz setting 55 * 01 = Delay1 (basic delay) 56 * 11 = Delay2 (basic delay + 2ns) 57 * 00 = Delay3 (inverter delay) 58 * 10 = Delay4 (inverter delay + 2ns) 59 */ 60 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1; 61 sdhci_writel(host, val, SDHCI_CONTROL3); 62 63 /* 64 * SELBASECLK[5:4] 65 * 00/01 = HCLK 66 * 10 = EPLL 67 * 11 = XTI or XEXTCLK 68 */ 69 ctrl = sdhci_readl(host, SDHCI_CONTROL2); 70 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3); 71 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2); 72 sdhci_writel(host, ctrl, SDHCI_CONTROL2); 73 } 74 75 static void s5p_set_clock(struct sdhci_host *host, u32 div) 76 { 77 /* ToDo : Use the Clock Framework */ 78 set_mmc_clk(host->index, div); 79 } 80 81 static const struct sdhci_ops s5p_sdhci_ops = { 82 .set_clock = &s5p_set_clock, 83 .set_control_reg = &s5p_sdhci_set_control_reg, 84 }; 85 86 static int s5p_sdhci_core_init(struct sdhci_host *host) 87 { 88 host->name = S5P_NAME; 89 90 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | 91 SDHCI_QUIRK_32BIT_DMA_ADDR | 92 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; 93 host->max_clk = 52000000; 94 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 95 host->ops = &s5p_sdhci_ops; 96 97 if (host->bus_width == 8) 98 host->host_caps |= MMC_MODE_8BIT; 99 100 #ifndef CONFIG_BLK 101 return add_sdhci(host, 0, 400000); 102 #else 103 return 0; 104 #endif 105 } 106 107 int s5p_sdhci_init(u32 regbase, int index, int bus_width) 108 { 109 struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host)); 110 if (!host) { 111 printf("sdhci__host allocation fail!\n"); 112 return -ENOMEM; 113 } 114 host->ioaddr = (void *)regbase; 115 host->index = index; 116 host->bus_width = bus_width; 117 118 return s5p_sdhci_core_init(host); 119 } 120 121 #if CONFIG_IS_ENABLED(OF_CONTROL) 122 struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; 123 124 static int do_sdhci_init(struct sdhci_host *host) 125 { 126 int dev_id, flag, ret; 127 128 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 129 dev_id = host->index + PERIPH_ID_SDMMC0; 130 131 ret = exynos_pinmux_config(dev_id, flag); 132 if (ret) { 133 printf("external SD not configured\n"); 134 return ret; 135 } 136 137 if (dm_gpio_is_valid(&host->pwr_gpio)) { 138 dm_gpio_set_value(&host->pwr_gpio, 1); 139 ret = exynos_pinmux_config(dev_id, flag); 140 if (ret) { 141 debug("MMC not configured\n"); 142 return ret; 143 } 144 } 145 146 if (dm_gpio_is_valid(&host->cd_gpio)) { 147 ret = dm_gpio_get_value(&host->cd_gpio); 148 if (ret) { 149 debug("no SD card detected (%d)\n", ret); 150 return -ENODEV; 151 } 152 } 153 154 return s5p_sdhci_core_init(host); 155 } 156 157 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) 158 { 159 int bus_width, dev_id; 160 unsigned int base; 161 162 /* Get device id */ 163 dev_id = pinmux_decode_periph_id(blob, node); 164 if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) { 165 debug("MMC: Can't get device id\n"); 166 return -EINVAL; 167 } 168 host->index = dev_id - PERIPH_ID_SDMMC0; 169 170 /* Get bus width */ 171 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 172 if (bus_width <= 0) { 173 debug("MMC: Can't get bus-width\n"); 174 return -EINVAL; 175 } 176 host->bus_width = bus_width; 177 178 /* Get the base address from the device node */ 179 base = fdtdec_get_addr(blob, node, "reg"); 180 if (!base) { 181 debug("MMC: Can't get base address\n"); 182 return -EINVAL; 183 } 184 host->ioaddr = (void *)base; 185 186 gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0, 187 &host->pwr_gpio, GPIOD_IS_OUT); 188 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0, 189 &host->cd_gpio, GPIOD_IS_IN); 190 191 return 0; 192 } 193 194 static int process_nodes(const void *blob, int node_list[], int count) 195 { 196 struct sdhci_host *host; 197 int i, node, ret; 198 int failed = 0; 199 200 debug("%s: count = %d\n", __func__, count); 201 202 /* build sdhci_host[] for each controller */ 203 for (i = 0; i < count; i++) { 204 node = node_list[i]; 205 if (node <= 0) 206 continue; 207 208 host = &sdhci_host[i]; 209 210 ret = sdhci_get_config(blob, node, host); 211 if (ret) { 212 printf("%s: failed to decode dev %d (%d)\n", __func__, i, ret); 213 failed++; 214 continue; 215 } 216 217 ret = do_sdhci_init(host); 218 if (ret && ret != -ENODEV) { 219 printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret); 220 failed++; 221 } 222 } 223 224 /* we only consider it an error when all nodes fail */ 225 return (failed == count ? -1 : 0); 226 } 227 228 int exynos_mmc_init(const void *blob) 229 { 230 int count; 231 int node_list[SDHCI_MAX_HOSTS]; 232 233 count = fdtdec_find_aliases_for_id(blob, "mmc", 234 COMPAT_SAMSUNG_EXYNOS_MMC, node_list, 235 SDHCI_MAX_HOSTS); 236 237 return process_nodes(blob, node_list, count); 238 } 239 #endif 240 241 #ifdef CONFIG_DM_MMC 242 static int s5p_sdhci_probe(struct udevice *dev) 243 { 244 struct s5p_sdhci_plat *plat = dev_get_platdata(dev); 245 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 246 struct sdhci_host *host = dev_get_priv(dev); 247 int ret; 248 249 ret = sdhci_get_config(gd->fdt_blob, dev_of_offset(dev), host); 250 if (ret) 251 return ret; 252 253 ret = do_sdhci_init(host); 254 if (ret) 255 return ret; 256 257 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000); 258 if (ret) 259 return ret; 260 261 host->mmc = &plat->mmc; 262 host->mmc->priv = host; 263 host->mmc->dev = dev; 264 upriv->mmc = host->mmc; 265 266 return sdhci_probe(dev); 267 } 268 269 static int s5p_sdhci_bind(struct udevice *dev) 270 { 271 struct s5p_sdhci_plat *plat = dev_get_platdata(dev); 272 int ret; 273 274 ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); 275 if (ret) 276 return ret; 277 278 return 0; 279 } 280 281 static const struct udevice_id s5p_sdhci_ids[] = { 282 { .compatible = "samsung,exynos4412-sdhci"}, 283 { } 284 }; 285 286 U_BOOT_DRIVER(s5p_sdhci_drv) = { 287 .name = "s5p_sdhci", 288 .id = UCLASS_MMC, 289 .of_match = s5p_sdhci_ids, 290 .bind = s5p_sdhci_bind, 291 .ops = &sdhci_ops, 292 .probe = s5p_sdhci_probe, 293 .priv_auto_alloc_size = sizeof(struct sdhci_host), 294 .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat), 295 }; 296 #endif /* CONFIG_DM_MMC */ 297