1 /* 2 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * Rockchip SD Host Controller Interface 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <linux/libfdt.h> 13 #include <malloc.h> 14 #include <mapmem.h> 15 #include <sdhci.h> 16 #include <clk.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 /* 400KHz is max freq for card ID etc. Use that as min */ 20 #define EMMC_MIN_FREQ 400000 21 22 struct rockchip_sdhc_plat { 23 #if CONFIG_IS_ENABLED(OF_PLATDATA) 24 struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; 25 #endif 26 struct mmc_config cfg; 27 struct mmc mmc; 28 }; 29 30 struct rockchip_sdhc { 31 struct sdhci_host host; 32 void *base; 33 }; 34 35 static int arasan_sdhci_probe(struct udevice *dev) 36 { 37 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 38 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 39 struct rockchip_sdhc *prv = dev_get_priv(dev); 40 struct sdhci_host *host = &prv->host; 41 int max_frequency, ret; 42 struct clk clk; 43 44 #if CONFIG_IS_ENABLED(OF_PLATDATA) 45 struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; 46 47 host->name = dev->name; 48 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 49 max_frequency = dtplat->max_frequency; 50 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); 51 #else 52 max_frequency = dev_read_u32_default(dev, "max-frequency", 0); 53 ret = clk_get_by_index(dev, 0, &clk); 54 #endif 55 if (!ret) { 56 ret = clk_set_rate(&clk, max_frequency); 57 if (IS_ERR_VALUE(ret)) 58 printf("%s clk set rate fail!\n", __func__); 59 } else { 60 printf("%s fail to get clk\n", __func__); 61 } 62 63 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; 64 host->max_clk = max_frequency; 65 /* 66 * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg 67 * doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't 68 * check for other bus-width values. 69 */ 70 if (host->bus_width == 8) 71 host->host_caps |= MMC_MODE_8BIT; 72 73 ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); 74 75 host->mmc = &plat->mmc; 76 if (ret) 77 return ret; 78 host->mmc->priv = &prv->host; 79 host->mmc->dev = dev; 80 upriv->mmc = host->mmc; 81 82 return sdhci_probe(dev); 83 } 84 85 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) 86 { 87 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 88 struct sdhci_host *host = dev_get_priv(dev); 89 90 host->name = dev->name; 91 host->ioaddr = dev_read_addr_ptr(dev); 92 host->bus_width = dev_read_u32_default(dev, "bus-width", 4); 93 #endif 94 95 return 0; 96 } 97 98 static int rockchip_sdhci_bind(struct udevice *dev) 99 { 100 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 101 102 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 103 } 104 105 static const struct udevice_id arasan_sdhci_ids[] = { 106 { .compatible = "arasan,sdhci-5.1" }, 107 { } 108 }; 109 110 U_BOOT_DRIVER(arasan_sdhci_drv) = { 111 .name = "rockchip_rk3399_sdhci_5_1", 112 .id = UCLASS_MMC, 113 .of_match = arasan_sdhci_ids, 114 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, 115 .ops = &sdhci_ops, 116 .bind = rockchip_sdhci_bind, 117 .probe = arasan_sdhci_probe, 118 .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), 119 .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), 120 }; 121