1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2013 Google, Inc
4  */
5 
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <dt-structs.h>
10 #include <dwmmc.h>
11 #include <errno.h>
12 #include <mapmem.h>
13 #include <pwrseq.h>
14 #include <syscon.h>
15 #include <asm/gpio.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/periph.h>
18 #include <linux/err.h>
19 
20 struct rockchip_mmc_plat {
21 #if CONFIG_IS_ENABLED(OF_PLATDATA)
22 	struct dtd_rockchip_rk3288_dw_mshc dtplat;
23 #endif
24 	struct mmc_config cfg;
25 	struct mmc mmc;
26 };
27 
28 struct rockchip_dwmmc_priv {
29 	struct clk clk;
30 	struct dwmci_host host;
31 	int fifo_depth;
32 	bool fifo_mode;
33 	u32 minmax[2];
34 };
35 
36 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
37 {
38 	struct udevice *dev = host->priv;
39 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
40 	int ret;
41 
42 	ret = clk_set_rate(&priv->clk, freq);
43 	if (ret < 0) {
44 		debug("%s: err=%d\n", __func__, ret);
45 		return ret;
46 	}
47 
48 	return freq;
49 }
50 
51 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
52 {
53 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
54 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
55 	struct dwmci_host *host = &priv->host;
56 
57 	host->name = dev->name;
58 	host->ioaddr = dev_read_addr_ptr(dev);
59 	host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
60 	host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
61 	host->priv = dev;
62 
63 	/* use non-removeable as sdcard and emmc as judgement */
64 	if (dev_read_bool(dev, "non-removable"))
65 		host->dev_index = 0;
66 	else
67 		host->dev_index = 1;
68 
69 	priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
70 
71 	if (priv->fifo_depth < 0)
72 		return -EINVAL;
73 	priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
74 
75 	/*
76 	 * 'clock-freq-min-max' is deprecated
77 	 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
78 	 */
79 	if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
80 		int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
81 
82 		if (val < 0)
83 			return val;
84 
85 		priv->minmax[0] = 400000;  /* 400 kHz */
86 		priv->minmax[1] = val;
87 	} else {
88 		debug("%s: 'clock-freq-min-max' property was deprecated.\n",
89 		      __func__);
90 	}
91 #endif
92 	return 0;
93 }
94 
95 static int rockchip_dwmmc_probe(struct udevice *dev)
96 {
97 	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
98 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
99 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
100 	struct dwmci_host *host = &priv->host;
101 	struct udevice *pwr_dev __maybe_unused;
102 	int ret;
103 
104 #if CONFIG_IS_ENABLED(OF_PLATDATA)
105 	struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
106 
107 	host->name = dev->name;
108 	host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
109 	host->buswidth = dtplat->bus_width;
110 	host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
111 	host->priv = dev;
112 	host->dev_index = 0;
113 	priv->fifo_depth = dtplat->fifo_depth;
114 	priv->fifo_mode = 0;
115 	priv->minmax[0] = 400000;  /*  400 kHz */
116 	priv->minmax[1] = dtplat->max_frequency;
117 
118 	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
119 	if (ret < 0)
120 		return ret;
121 #else
122 	ret = clk_get_by_index(dev, 0, &priv->clk);
123 	if (ret < 0)
124 		return ret;
125 #endif
126 	host->fifoth_val = MSIZE(0x2) |
127 		RX_WMARK(priv->fifo_depth / 2 - 1) |
128 		TX_WMARK(priv->fifo_depth / 2);
129 
130 	host->fifo_mode = priv->fifo_mode;
131 
132 #ifdef CONFIG_PWRSEQ
133 	/* Enable power if needed */
134 	ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
135 					   &pwr_dev);
136 	if (!ret) {
137 		ret = pwrseq_set_power(pwr_dev, true);
138 		if (ret)
139 			return ret;
140 	}
141 #endif
142 	dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
143 	host->mmc = &plat->mmc;
144 	host->mmc->priv = &priv->host;
145 	host->mmc->dev = dev;
146 	upriv->mmc = host->mmc;
147 
148 	return dwmci_probe(dev);
149 }
150 
151 static int rockchip_dwmmc_bind(struct udevice *dev)
152 {
153 	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
154 
155 	return dwmci_bind(dev, &plat->mmc, &plat->cfg);
156 }
157 
158 static const struct udevice_id rockchip_dwmmc_ids[] = {
159 	{ .compatible = "rockchip,rk3288-dw-mshc" },
160 	{ }
161 };
162 
163 U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
164 	.name		= "rockchip_rk3288_dw_mshc",
165 	.id		= UCLASS_MMC,
166 	.of_match	= rockchip_dwmmc_ids,
167 	.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
168 	.ops		= &dm_dwmci_ops,
169 	.bind		= rockchip_dwmmc_bind,
170 	.probe		= rockchip_dwmmc_probe,
171 	.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
172 	.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
173 };
174 
175 #ifdef CONFIG_PWRSEQ
176 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
177 {
178 	struct gpio_desc reset;
179 	int ret;
180 
181 	ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
182 	if (ret)
183 		return ret;
184 	dm_gpio_set_value(&reset, 1);
185 	udelay(1);
186 	dm_gpio_set_value(&reset, 0);
187 	udelay(200);
188 
189 	return 0;
190 }
191 
192 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
193 	.set_power	= rockchip_dwmmc_pwrseq_set_power,
194 };
195 
196 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
197 	{ .compatible = "mmc-pwrseq-emmc" },
198 	{ }
199 };
200 
201 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
202 	.name		= "mmc_pwrseq_emmc",
203 	.id		= UCLASS_PWRSEQ,
204 	.of_match	= rockchip_dwmmc_pwrseq_ids,
205 	.ops		= &rockchip_dwmmc_pwrseq_ops,
206 };
207 #endif
208