1 /* 2 * Copyright (c) 2013 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <dt-structs.h> 11 #include <dwmmc.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <pwrseq.h> 15 #include <syscon.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/periph.h> 19 #include <linux/err.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 struct rockchip_mmc_plat { 24 #if CONFIG_IS_ENABLED(OF_PLATDATA) 25 struct dtd_rockchip_rk3288_dw_mshc dtplat; 26 #endif 27 struct mmc_config cfg; 28 struct mmc mmc; 29 }; 30 31 struct rockchip_dwmmc_priv { 32 struct clk clk; 33 struct dwmci_host host; 34 int fifo_depth; 35 bool fifo_mode; 36 u32 minmax[2]; 37 }; 38 39 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) 40 { 41 struct udevice *dev = host->priv; 42 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 43 int ret; 44 45 ret = clk_set_rate(&priv->clk, freq); 46 if (ret < 0) { 47 debug("%s: err=%d\n", __func__, ret); 48 return ret; 49 } 50 51 return freq; 52 } 53 54 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) 55 { 56 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 57 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 58 struct dwmci_host *host = &priv->host; 59 60 host->name = dev->name; 61 host->ioaddr = dev_read_addr_ptr(dev); 62 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); 63 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 64 host->priv = dev; 65 66 /* use non-removeable as sdcard and emmc as judgement */ 67 if (dev_read_bool(dev, "non-removable")) 68 host->dev_index = 0; 69 else 70 host->dev_index = 1; 71 72 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); 73 74 if (priv->fifo_depth < 0) 75 return -EINVAL; 76 priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); 77 78 /* 79 * 'clock-freq-min-max' is deprecated 80 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) 81 */ 82 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { 83 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); 84 85 if (val < 0) 86 return val; 87 88 priv->minmax[0] = 400000; /* 400 kHz */ 89 priv->minmax[1] = val; 90 } else { 91 debug("%s: 'clock-freq-min-max' property was deprecated.\n", 92 __func__); 93 } 94 #endif 95 return 0; 96 } 97 98 static int rockchip_dwmmc_probe(struct udevice *dev) 99 { 100 struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 101 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 102 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 103 struct dwmci_host *host = &priv->host; 104 struct udevice *pwr_dev __maybe_unused; 105 int ret; 106 107 #if CONFIG_IS_ENABLED(OF_PLATDATA) 108 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; 109 110 host->name = dev->name; 111 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 112 host->buswidth = dtplat->bus_width; 113 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 114 host->priv = dev; 115 host->dev_index = 0; 116 priv->fifo_depth = dtplat->fifo_depth; 117 priv->fifo_mode = 0; 118 priv->minmax[0] = 400000; /* 400 kHz */ 119 priv->minmax[1] = dtplat->max_frequency; 120 121 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); 122 if (ret < 0) 123 return ret; 124 #else 125 ret = clk_get_by_index(dev, 0, &priv->clk); 126 if (ret < 0) 127 return ret; 128 #endif 129 host->fifoth_val = MSIZE(0x2) | 130 RX_WMARK(priv->fifo_depth / 2 - 1) | 131 TX_WMARK(priv->fifo_depth / 2); 132 133 host->fifo_mode = priv->fifo_mode; 134 135 #ifdef CONFIG_PWRSEQ 136 /* Enable power if needed */ 137 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", 138 &pwr_dev); 139 if (!ret) { 140 ret = pwrseq_set_power(pwr_dev, true); 141 if (ret) 142 return ret; 143 } 144 #endif 145 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); 146 host->mmc = &plat->mmc; 147 host->mmc->priv = &priv->host; 148 host->mmc->dev = dev; 149 upriv->mmc = host->mmc; 150 151 return dwmci_probe(dev); 152 } 153 154 static int rockchip_dwmmc_bind(struct udevice *dev) 155 { 156 struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 157 158 return dwmci_bind(dev, &plat->mmc, &plat->cfg); 159 } 160 161 static const struct udevice_id rockchip_dwmmc_ids[] = { 162 { .compatible = "rockchip,rk3288-dw-mshc" }, 163 { } 164 }; 165 166 U_BOOT_DRIVER(rockchip_dwmmc_drv) = { 167 .name = "rockchip_rk3288_dw_mshc", 168 .id = UCLASS_MMC, 169 .of_match = rockchip_dwmmc_ids, 170 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, 171 .ops = &dm_dwmci_ops, 172 .bind = rockchip_dwmmc_bind, 173 .probe = rockchip_dwmmc_probe, 174 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), 175 .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), 176 }; 177 178 #ifdef CONFIG_PWRSEQ 179 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable) 180 { 181 struct gpio_desc reset; 182 int ret; 183 184 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); 185 if (ret) 186 return ret; 187 dm_gpio_set_value(&reset, 1); 188 udelay(1); 189 dm_gpio_set_value(&reset, 0); 190 udelay(200); 191 192 return 0; 193 } 194 195 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = { 196 .set_power = rockchip_dwmmc_pwrseq_set_power, 197 }; 198 199 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = { 200 { .compatible = "mmc-pwrseq-emmc" }, 201 { } 202 }; 203 204 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = { 205 .name = "mmc_pwrseq_emmc", 206 .id = UCLASS_PWRSEQ, 207 .of_match = rockchip_dwmmc_pwrseq_ids, 208 .ops = &rockchip_dwmmc_pwrseq_ops, 209 }; 210 #endif 211