1 /*
2  * Copyright (c) 2013 Google, Inc
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <dt-structs.h>
11 #include <dwmmc.h>
12 #include <errno.h>
13 #include <mapmem.h>
14 #include <pwrseq.h>
15 #include <syscon.h>
16 #include <asm/gpio.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/periph.h>
19 #include <linux/err.h>
20 
21 DECLARE_GLOBAL_DATA_PTR;
22 
23 struct rockchip_mmc_plat {
24 #if CONFIG_IS_ENABLED(OF_PLATDATA)
25 	struct dtd_rockchip_rk3288_dw_mshc dtplat;
26 #endif
27 	struct mmc_config cfg;
28 	struct mmc mmc;
29 };
30 
31 struct rockchip_dwmmc_priv {
32 	struct clk clk;
33 	struct dwmci_host host;
34 	int fifo_depth;
35 	bool fifo_mode;
36 	u32 minmax[2];
37 };
38 
39 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
40 {
41 	struct udevice *dev = host->priv;
42 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
43 	int ret;
44 
45 	ret = clk_set_rate(&priv->clk, freq);
46 	if (ret < 0) {
47 		debug("%s: err=%d\n", __func__, ret);
48 		return ret;
49 	}
50 
51 	return freq;
52 }
53 
54 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
55 {
56 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
57 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
58 	struct dwmci_host *host = &priv->host;
59 
60 	host->name = dev->name;
61 	host->ioaddr = (void *)dev_get_addr(dev);
62 	host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
63 					"bus-width", 4);
64 	host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
65 	host->priv = dev;
66 
67 	/* use non-removeable as sdcard and emmc as judgement */
68 	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
69 		host->dev_index = 0;
70 	else
71 		host->dev_index = 1;
72 
73 	priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
74 				    "fifo-depth", 0);
75 	if (priv->fifo_depth < 0)
76 		return -EINVAL;
77 	priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
78 					  "fifo-mode");
79 	if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
80 				 "clock-freq-min-max", priv->minmax, 2))
81 		return -EINVAL;
82 #endif
83 	return 0;
84 }
85 
86 static int rockchip_dwmmc_probe(struct udevice *dev)
87 {
88 	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
89 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
90 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
91 	struct dwmci_host *host = &priv->host;
92 	struct udevice *pwr_dev __maybe_unused;
93 	int ret;
94 
95 #if CONFIG_IS_ENABLED(OF_PLATDATA)
96 	struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
97 
98 	host->name = dev->name;
99 	host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
100 	host->buswidth = dtplat->bus_width;
101 	host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
102 	host->priv = dev;
103 	host->dev_index = 0;
104 	priv->fifo_depth = dtplat->fifo_depth;
105 	priv->fifo_mode = 0;
106 	memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
107 
108 	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
109 	if (ret < 0)
110 		return ret;
111 #else
112 	ret = clk_get_by_index(dev, 0, &priv->clk);
113 	if (ret < 0)
114 		return ret;
115 #endif
116 	host->fifoth_val = MSIZE(0x2) |
117 		RX_WMARK(priv->fifo_depth / 2 - 1) |
118 		TX_WMARK(priv->fifo_depth / 2);
119 
120 	host->fifo_mode = priv->fifo_mode;
121 
122 #ifdef CONFIG_PWRSEQ
123 	/* Enable power if needed */
124 	ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
125 					   &pwr_dev);
126 	if (!ret) {
127 		ret = pwrseq_set_power(pwr_dev, true);
128 		if (ret)
129 			return ret;
130 	}
131 #endif
132 	dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
133 	host->mmc = &plat->mmc;
134 	host->mmc->priv = &priv->host;
135 	host->mmc->dev = dev;
136 	upriv->mmc = host->mmc;
137 
138 	return dwmci_probe(dev);
139 }
140 
141 static int rockchip_dwmmc_bind(struct udevice *dev)
142 {
143 	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
144 
145 	return dwmci_bind(dev, &plat->mmc, &plat->cfg);
146 }
147 
148 static const struct udevice_id rockchip_dwmmc_ids[] = {
149 	{ .compatible = "rockchip,rk3288-dw-mshc" },
150 	{ }
151 };
152 
153 U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
154 	.name		= "rockchip_rk3288_dw_mshc",
155 	.id		= UCLASS_MMC,
156 	.of_match	= rockchip_dwmmc_ids,
157 	.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
158 	.ops		= &dm_dwmci_ops,
159 	.bind		= rockchip_dwmmc_bind,
160 	.probe		= rockchip_dwmmc_probe,
161 	.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
162 	.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
163 };
164 
165 #ifdef CONFIG_PWRSEQ
166 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
167 {
168 	struct gpio_desc reset;
169 	int ret;
170 
171 	ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
172 	if (ret)
173 		return ret;
174 	dm_gpio_set_value(&reset, 1);
175 	udelay(1);
176 	dm_gpio_set_value(&reset, 0);
177 	udelay(200);
178 
179 	return 0;
180 }
181 
182 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
183 	.set_power	= rockchip_dwmmc_pwrseq_set_power,
184 };
185 
186 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
187 	{ .compatible = "mmc-pwrseq-emmc" },
188 	{ }
189 };
190 
191 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
192 	.name		= "mmc_pwrseq_emmc",
193 	.id		= UCLASS_PWRSEQ,
194 	.of_match	= rockchip_dwmmc_pwrseq_ids,
195 	.ops		= &rockchip_dwmmc_pwrseq_ops,
196 };
197 #endif
198