1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a8cb4fb5SSimon Glass /* 3a8cb4fb5SSimon Glass * Copyright (c) 2013 Google, Inc 4a8cb4fb5SSimon Glass */ 5a8cb4fb5SSimon Glass 6a8cb4fb5SSimon Glass #include <common.h> 7a8cb4fb5SSimon Glass #include <clk.h> 8a8cb4fb5SSimon Glass #include <dm.h> 9bfeb443eSSimon Glass #include <dt-structs.h> 10a8cb4fb5SSimon Glass #include <dwmmc.h> 11a8cb4fb5SSimon Glass #include <errno.h> 12bfeb443eSSimon Glass #include <mapmem.h> 13e1efec4eSSimon Glass #include <pwrseq.h> 14a8cb4fb5SSimon Glass #include <syscon.h> 15e1efec4eSSimon Glass #include <asm/gpio.h> 16a8cb4fb5SSimon Glass #include <asm/arch/clock.h> 17a8cb4fb5SSimon Glass #include <asm/arch/periph.h> 18a8cb4fb5SSimon Glass #include <linux/err.h> 19a8cb4fb5SSimon Glass 20f6e41d17SSimon Glass struct rockchip_mmc_plat { 21bfeb443eSSimon Glass #if CONFIG_IS_ENABLED(OF_PLATDATA) 22bfeb443eSSimon Glass struct dtd_rockchip_rk3288_dw_mshc dtplat; 23bfeb443eSSimon Glass #endif 24f6e41d17SSimon Glass struct mmc_config cfg; 25f6e41d17SSimon Glass struct mmc mmc; 26f6e41d17SSimon Glass }; 27f6e41d17SSimon Glass 28a8cb4fb5SSimon Glass struct rockchip_dwmmc_priv { 29135aa950SStephen Warren struct clk clk; 30a8cb4fb5SSimon Glass struct dwmci_host host; 316809b04fSSimon Glass int fifo_depth; 326809b04fSSimon Glass bool fifo_mode; 336809b04fSSimon Glass u32 minmax[2]; 34a8cb4fb5SSimon Glass }; 35a8cb4fb5SSimon Glass 36a8cb4fb5SSimon Glass static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) 37a8cb4fb5SSimon Glass { 38a8cb4fb5SSimon Glass struct udevice *dev = host->priv; 39a8cb4fb5SSimon Glass struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 40a8cb4fb5SSimon Glass int ret; 41a8cb4fb5SSimon Glass 42135aa950SStephen Warren ret = clk_set_rate(&priv->clk, freq); 43a8cb4fb5SSimon Glass if (ret < 0) { 44419b0801SKever Yang debug("%s: err=%d\n", __func__, ret); 45a8cb4fb5SSimon Glass return ret; 46a8cb4fb5SSimon Glass } 47a8cb4fb5SSimon Glass 48a8cb4fb5SSimon Glass return freq; 49a8cb4fb5SSimon Glass } 50a8cb4fb5SSimon Glass 51a8cb4fb5SSimon Glass static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) 52a8cb4fb5SSimon Glass { 53bfeb443eSSimon Glass #if !CONFIG_IS_ENABLED(OF_PLATDATA) 54a8cb4fb5SSimon Glass struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 55a8cb4fb5SSimon Glass struct dwmci_host *host = &priv->host; 56a8cb4fb5SSimon Glass 57a8cb4fb5SSimon Glass host->name = dev->name; 58be5f04e8SPhilipp Tomsich host->ioaddr = dev_read_addr_ptr(dev); 59fd1bf8dfSPhilipp Tomsich host->buswidth = dev_read_u32_default(dev, "bus-width", 4); 60a8cb4fb5SSimon Glass host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 61a8cb4fb5SSimon Glass host->priv = dev; 62a8cb4fb5SSimon Glass 63ace2198bShuang lin /* use non-removeable as sdcard and emmc as judgement */ 64fd1bf8dfSPhilipp Tomsich if (dev_read_bool(dev, "non-removable")) 656579385bShuang lin host->dev_index = 0; 666579385bShuang lin else 67ace2198bShuang lin host->dev_index = 1; 68a8cb4fb5SSimon Glass 69fd1bf8dfSPhilipp Tomsich priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); 70fd1bf8dfSPhilipp Tomsich 716809b04fSSimon Glass if (priv->fifo_depth < 0) 726809b04fSSimon Glass return -EINVAL; 73fd1bf8dfSPhilipp Tomsich priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); 74ff71f9acSPhilipp Tomsich 75ff71f9acSPhilipp Tomsich /* 76ff71f9acSPhilipp Tomsich * 'clock-freq-min-max' is deprecated 77ff71f9acSPhilipp Tomsich * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) 78ff71f9acSPhilipp Tomsich */ 79fd1bf8dfSPhilipp Tomsich if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { 80fd1bf8dfSPhilipp Tomsich int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); 81ff71f9acSPhilipp Tomsich 82ff71f9acSPhilipp Tomsich if (val < 0) 83ff71f9acSPhilipp Tomsich return val; 84ff71f9acSPhilipp Tomsich 85ff71f9acSPhilipp Tomsich priv->minmax[0] = 400000; /* 400 kHz */ 86ff71f9acSPhilipp Tomsich priv->minmax[1] = val; 87ff71f9acSPhilipp Tomsich } else { 88ff71f9acSPhilipp Tomsich debug("%s: 'clock-freq-min-max' property was deprecated.\n", 89ff71f9acSPhilipp Tomsich __func__); 90ff71f9acSPhilipp Tomsich } 91bfeb443eSSimon Glass #endif 92a8cb4fb5SSimon Glass return 0; 93a8cb4fb5SSimon Glass } 94a8cb4fb5SSimon Glass 95a8cb4fb5SSimon Glass static int rockchip_dwmmc_probe(struct udevice *dev) 96a8cb4fb5SSimon Glass { 97f6e41d17SSimon Glass struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 98a8cb4fb5SSimon Glass struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 99a8cb4fb5SSimon Glass struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); 100a8cb4fb5SSimon Glass struct dwmci_host *host = &priv->host; 101e1efec4eSSimon Glass struct udevice *pwr_dev __maybe_unused; 102a8cb4fb5SSimon Glass int ret; 103a8cb4fb5SSimon Glass 104bfeb443eSSimon Glass #if CONFIG_IS_ENABLED(OF_PLATDATA) 105bfeb443eSSimon Glass struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; 106bfeb443eSSimon Glass 107bfeb443eSSimon Glass host->name = dev->name; 108bfeb443eSSimon Glass host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 109bfeb443eSSimon Glass host->buswidth = dtplat->bus_width; 110bfeb443eSSimon Glass host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; 111bfeb443eSSimon Glass host->priv = dev; 112bfeb443eSSimon Glass host->dev_index = 0; 113bfeb443eSSimon Glass priv->fifo_depth = dtplat->fifo_depth; 114bfeb443eSSimon Glass priv->fifo_mode = 0; 11580935298SKever Yang priv->minmax[0] = 400000; /* 400 kHz */ 11680935298SKever Yang priv->minmax[1] = dtplat->max_frequency; 117bfeb443eSSimon Glass 118bfeb443eSSimon Glass ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); 119bfeb443eSSimon Glass if (ret < 0) 120bfeb443eSSimon Glass return ret; 121bfeb443eSSimon Glass #else 122419b0801SKever Yang ret = clk_get_by_index(dev, 0, &priv->clk); 123898d6439SSimon Glass if (ret < 0) 124a8cb4fb5SSimon Glass return ret; 125bfeb443eSSimon Glass #endif 12628637248Shuang lin host->fifoth_val = MSIZE(0x2) | 1276809b04fSSimon Glass RX_WMARK(priv->fifo_depth / 2 - 1) | 1286809b04fSSimon Glass TX_WMARK(priv->fifo_depth / 2); 12928637248Shuang lin 1306809b04fSSimon Glass host->fifo_mode = priv->fifo_mode; 13128637248Shuang lin 132e1efec4eSSimon Glass #ifdef CONFIG_PWRSEQ 133e1efec4eSSimon Glass /* Enable power if needed */ 134e1efec4eSSimon Glass ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", 135e1efec4eSSimon Glass &pwr_dev); 136e1efec4eSSimon Glass if (!ret) { 137e1efec4eSSimon Glass ret = pwrseq_set_power(pwr_dev, true); 138e1efec4eSSimon Glass if (ret) 139e1efec4eSSimon Glass return ret; 140e1efec4eSSimon Glass } 141e1efec4eSSimon Glass #endif 142e5113c33SJaehoon Chung dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); 143f6e41d17SSimon Glass host->mmc = &plat->mmc; 144f6e41d17SSimon Glass host->mmc->priv = &priv->host; 145cffe5d86SSimon Glass host->mmc->dev = dev; 146a8cb4fb5SSimon Glass upriv->mmc = host->mmc; 147a8cb4fb5SSimon Glass 14842b37d8dSSimon Glass return dwmci_probe(dev); 149a8cb4fb5SSimon Glass } 150a8cb4fb5SSimon Glass 151f6e41d17SSimon Glass static int rockchip_dwmmc_bind(struct udevice *dev) 152f6e41d17SSimon Glass { 153f6e41d17SSimon Glass struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 154f6e41d17SSimon Glass 15524f5aec3SMasahiro Yamada return dwmci_bind(dev, &plat->mmc, &plat->cfg); 156f6e41d17SSimon Glass } 157f6e41d17SSimon Glass 158a8cb4fb5SSimon Glass static const struct udevice_id rockchip_dwmmc_ids[] = { 159a8cb4fb5SSimon Glass { .compatible = "rockchip,rk3288-dw-mshc" }, 160a8cb4fb5SSimon Glass { } 161a8cb4fb5SSimon Glass }; 162a8cb4fb5SSimon Glass 163a8cb4fb5SSimon Glass U_BOOT_DRIVER(rockchip_dwmmc_drv) = { 164bfeb443eSSimon Glass .name = "rockchip_rk3288_dw_mshc", 165a8cb4fb5SSimon Glass .id = UCLASS_MMC, 166a8cb4fb5SSimon Glass .of_match = rockchip_dwmmc_ids, 167a8cb4fb5SSimon Glass .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, 16842b37d8dSSimon Glass .ops = &dm_dwmci_ops, 169f6e41d17SSimon Glass .bind = rockchip_dwmmc_bind, 170a8cb4fb5SSimon Glass .probe = rockchip_dwmmc_probe, 171a8cb4fb5SSimon Glass .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), 172f6e41d17SSimon Glass .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), 173a8cb4fb5SSimon Glass }; 174e1efec4eSSimon Glass 175e1efec4eSSimon Glass #ifdef CONFIG_PWRSEQ 176e1efec4eSSimon Glass static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable) 177e1efec4eSSimon Glass { 178e1efec4eSSimon Glass struct gpio_desc reset; 179e1efec4eSSimon Glass int ret; 180e1efec4eSSimon Glass 181e1efec4eSSimon Glass ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); 182e1efec4eSSimon Glass if (ret) 183e1efec4eSSimon Glass return ret; 184e1efec4eSSimon Glass dm_gpio_set_value(&reset, 1); 185e1efec4eSSimon Glass udelay(1); 186e1efec4eSSimon Glass dm_gpio_set_value(&reset, 0); 187e1efec4eSSimon Glass udelay(200); 188e1efec4eSSimon Glass 189e1efec4eSSimon Glass return 0; 190e1efec4eSSimon Glass } 191e1efec4eSSimon Glass 192e1efec4eSSimon Glass static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = { 193e1efec4eSSimon Glass .set_power = rockchip_dwmmc_pwrseq_set_power, 194e1efec4eSSimon Glass }; 195e1efec4eSSimon Glass 196e1efec4eSSimon Glass static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = { 197e1efec4eSSimon Glass { .compatible = "mmc-pwrseq-emmc" }, 198e1efec4eSSimon Glass { } 199e1efec4eSSimon Glass }; 200e1efec4eSSimon Glass 201e1efec4eSSimon Glass U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = { 202e1efec4eSSimon Glass .name = "mmc_pwrseq_emmc", 203e1efec4eSSimon Glass .id = UCLASS_PWRSEQ, 204e1efec4eSSimon Glass .of_match = rockchip_dwmmc_pwrseq_ids, 205e1efec4eSSimon Glass .ops = &rockchip_dwmmc_pwrseq_ops, 206e1efec4eSSimon Glass }; 207e1efec4eSSimon Glass #endif 208