1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 4 */ 5 6 #include <common.h> 7 #include <clk.h> 8 #include <fdtdec.h> 9 #include <mmc.h> 10 #include <dm.h> 11 #include <linux/compat.h> 12 #include <linux/dma-direction.h> 13 #include <linux/io.h> 14 #include <linux/sizes.h> 15 #include <power/regulator.h> 16 #include <asm/unaligned.h> 17 18 #include "tmio-common.h" 19 20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ 21 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ 22 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 23 24 /* SCC registers */ 25 #define RENESAS_SDHI_SCC_DTCNTL 0x800 26 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0) 27 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 28 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 29 #define RENESAS_SDHI_SCC_TAPSET 0x804 30 #define RENESAS_SDHI_SCC_DT2FF 0x808 31 #define RENESAS_SDHI_SCC_CKSEL 0x80c 32 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0) 33 #define RENESAS_SDHI_SCC_RVSCNTL 0x810 34 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 35 #define RENESAS_SDHI_SCC_RVSREQ 0x814 36 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2) 37 #define RENESAS_SDHI_SCC_SMPCMP 0x818 38 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c 39 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 40 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 41 42 #define RENESAS_SDHI_MAX_TAP 3 43 44 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv) 45 { 46 u32 reg; 47 48 /* Initialize SCC */ 49 tmio_sd_writel(priv, 0, TMIO_SD_INFO1); 50 51 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); 52 reg &= ~TMIO_SD_CLKCTL_SCLKEN; 53 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); 54 55 /* Set sampling clock selection range */ 56 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) | 57 RENESAS_SDHI_SCC_DTCNTL_TAPEN, 58 RENESAS_SDHI_SCC_DTCNTL); 59 60 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); 61 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; 62 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); 63 64 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); 65 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN; 66 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); 67 68 tmio_sd_writel(priv, 0x300 /* scc_tappos */, 69 RENESAS_SDHI_SCC_DT2FF); 70 71 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); 72 reg |= TMIO_SD_CLKCTL_SCLKEN; 73 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); 74 75 /* Read TAPNUM */ 76 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >> 77 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 78 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK; 79 } 80 81 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv) 82 { 83 u32 reg; 84 85 /* Reset SCC */ 86 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); 87 reg &= ~TMIO_SD_CLKCTL_SCLKEN; 88 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); 89 90 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); 91 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL; 92 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); 93 94 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2); 95 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN | 96 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL); 97 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2); 98 99 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); 100 reg |= TMIO_SD_CLKCTL_SCLKEN; 101 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); 102 103 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); 104 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN; 105 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); 106 107 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); 108 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN; 109 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); 110 } 111 112 static int renesas_sdhi_hs400(struct udevice *dev) 113 { 114 struct tmio_sd_priv *priv = dev_get_priv(dev); 115 struct mmc *mmc = mmc_get_mmc_dev(dev); 116 bool hs400 = (mmc->selected_mode == MMC_HS_400); 117 int ret, taps = hs400 ? priv->nrtaps : 8; 118 u32 reg; 119 120 if (taps == 4) /* HS400 on 4tap SoC needs different clock */ 121 ret = clk_set_rate(&priv->clk, 400000000); 122 else 123 ret = clk_set_rate(&priv->clk, 200000000); 124 if (ret < 0) 125 return ret; 126 127 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); 128 129 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2); 130 if (hs400) { 131 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN | 132 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL; 133 } else { 134 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN | 135 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL); 136 } 137 138 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2); 139 140 tmio_sd_writel(priv, (taps << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) | 141 RENESAS_SDHI_SCC_DTCNTL_TAPEN, 142 RENESAS_SDHI_SCC_DTCNTL); 143 144 if (taps == 4) { 145 tmio_sd_writel(priv, priv->tap_set >> 1, 146 RENESAS_SDHI_SCC_TAPSET); 147 } else { 148 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); 149 } 150 151 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); 152 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; 153 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); 154 155 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); 156 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN; 157 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); 158 159 return 0; 160 } 161 162 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv, 163 unsigned long tap) 164 { 165 /* Set sampling clock position */ 166 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET); 167 } 168 169 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv) 170 { 171 /* Get comparison of sampling data */ 172 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP); 173 } 174 175 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, 176 unsigned int tap_num, unsigned int taps, 177 unsigned int smpcmp) 178 { 179 unsigned long tap_cnt; /* counter of tuning success */ 180 unsigned long tap_start;/* start position of tuning success */ 181 unsigned long tap_end; /* end position of tuning success */ 182 unsigned long ntap; /* temporary counter of tuning success */ 183 unsigned long match_cnt;/* counter of matching data */ 184 unsigned long i; 185 bool select = false; 186 u32 reg; 187 188 /* Clear SCC_RVSREQ */ 189 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); 190 191 /* Merge the results */ 192 for (i = 0; i < tap_num * 2; i++) { 193 if (!(taps & BIT(i))) { 194 taps &= ~BIT(i % tap_num); 195 taps &= ~BIT((i % tap_num) + tap_num); 196 } 197 if (!(smpcmp & BIT(i))) { 198 smpcmp &= ~BIT(i % tap_num); 199 smpcmp &= ~BIT((i % tap_num) + tap_num); 200 } 201 } 202 203 /* 204 * Find the longest consecutive run of successful probes. If that 205 * is more than RENESAS_SDHI_MAX_TAP probes long then use the 206 * center index as the tap. 207 */ 208 tap_cnt = 0; 209 ntap = 0; 210 tap_start = 0; 211 tap_end = 0; 212 for (i = 0; i < tap_num * 2; i++) { 213 if (taps & BIT(i)) 214 ntap++; 215 else { 216 if (ntap > tap_cnt) { 217 tap_start = i - ntap; 218 tap_end = i - 1; 219 tap_cnt = ntap; 220 } 221 ntap = 0; 222 } 223 } 224 225 if (ntap > tap_cnt) { 226 tap_start = i - ntap; 227 tap_end = i - 1; 228 tap_cnt = ntap; 229 } 230 231 /* 232 * If all of the TAP is OK, the sampling clock position is selected by 233 * identifying the change point of data. 234 */ 235 if (tap_cnt == tap_num * 2) { 236 match_cnt = 0; 237 ntap = 0; 238 tap_start = 0; 239 tap_end = 0; 240 for (i = 0; i < tap_num * 2; i++) { 241 if (smpcmp & BIT(i)) 242 ntap++; 243 else { 244 if (ntap > match_cnt) { 245 tap_start = i - ntap; 246 tap_end = i - 1; 247 match_cnt = ntap; 248 } 249 ntap = 0; 250 } 251 } 252 if (ntap > match_cnt) { 253 tap_start = i - ntap; 254 tap_end = i - 1; 255 match_cnt = ntap; 256 } 257 if (match_cnt) 258 select = true; 259 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP) 260 select = true; 261 262 if (select) 263 priv->tap_set = ((tap_start + tap_end) / 2) % tap_num; 264 else 265 return -EIO; 266 267 /* Set SCC */ 268 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); 269 270 /* Enable auto re-tuning */ 271 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); 272 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN; 273 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); 274 275 return 0; 276 } 277 278 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) 279 { 280 struct tmio_sd_priv *priv = dev_get_priv(dev); 281 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 282 struct mmc *mmc = upriv->mmc; 283 unsigned int tap_num; 284 unsigned int taps = 0, smpcmp = 0; 285 int i, ret = 0; 286 u32 caps; 287 288 /* Only supported on Renesas RCar */ 289 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS)) 290 return -EINVAL; 291 292 /* clock tuning is not needed for upto 52MHz */ 293 if (!((mmc->selected_mode == MMC_HS_200) || 294 (mmc->selected_mode == MMC_HS_400) || 295 (mmc->selected_mode == UHS_SDR104) || 296 (mmc->selected_mode == UHS_SDR50))) 297 return 0; 298 299 tap_num = renesas_sdhi_init_tuning(priv); 300 if (!tap_num) 301 /* Tuning is not supported */ 302 goto out; 303 304 if (tap_num * 2 >= sizeof(taps) * 8) { 305 dev_err(dev, 306 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n"); 307 goto out; 308 } 309 310 /* Issue CMD19 twice for each tap */ 311 for (i = 0; i < 2 * tap_num; i++) { 312 renesas_sdhi_prepare_tuning(priv, i % tap_num); 313 314 /* Force PIO for the tuning */ 315 caps = priv->caps; 316 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL; 317 318 ret = mmc_send_tuning(mmc, opcode, NULL); 319 320 priv->caps = caps; 321 322 if (ret == 0) 323 taps |= BIT(i); 324 325 ret = renesas_sdhi_compare_scc_data(priv); 326 if (ret == 0) 327 smpcmp |= BIT(i); 328 329 mdelay(1); 330 } 331 332 ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp); 333 334 out: 335 if (ret < 0) { 336 dev_warn(dev, "Tuning procedure failed\n"); 337 renesas_sdhi_reset_tuning(priv); 338 } 339 340 return ret; 341 } 342 #else 343 static int renesas_sdhi_hs400(struct udevice *dev) 344 { 345 return 0; 346 } 347 #endif 348 349 static int renesas_sdhi_set_ios(struct udevice *dev) 350 { 351 struct tmio_sd_priv *priv = dev_get_priv(dev); 352 u32 tmp; 353 int ret; 354 355 /* Stop the clock before changing its rate to avoid a glitch signal */ 356 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); 357 tmp &= ~TMIO_SD_CLKCTL_SCLKEN; 358 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 359 360 ret = renesas_sdhi_hs400(dev); 361 if (ret) 362 return ret; 363 364 ret = tmio_sd_set_ios(dev); 365 366 mdelay(10); 367 368 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ 369 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ 370 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 371 struct mmc *mmc = mmc_get_mmc_dev(dev); 372 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) && 373 (mmc->selected_mode != UHS_SDR104) && 374 (mmc->selected_mode != MMC_HS_200) && 375 (mmc->selected_mode != MMC_HS_400)) { 376 renesas_sdhi_reset_tuning(priv); 377 } 378 #endif 379 380 return ret; 381 } 382 383 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 384 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout) 385 { 386 int ret = -ETIMEDOUT; 387 bool dat0_high; 388 bool target_dat0_high = !!state; 389 struct tmio_sd_priv *priv = dev_get_priv(dev); 390 391 timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */ 392 while (timeout--) { 393 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0); 394 if (dat0_high == target_dat0_high) { 395 ret = 0; 396 break; 397 } 398 udelay(10); 399 } 400 401 return ret; 402 } 403 #endif 404 405 static const struct dm_mmc_ops renesas_sdhi_ops = { 406 .send_cmd = tmio_sd_send_cmd, 407 .set_ios = renesas_sdhi_set_ios, 408 .get_cd = tmio_sd_get_cd, 409 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ 410 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ 411 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 412 .execute_tuning = renesas_sdhi_execute_tuning, 413 #endif 414 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 415 .wait_dat0 = renesas_sdhi_wait_dat0, 416 #endif 417 }; 418 419 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2 420 #define RENESAS_GEN3_QUIRKS \ 421 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS 422 423 static const struct udevice_id renesas_sdhi_match[] = { 424 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS }, 425 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS }, 426 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS }, 427 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS }, 428 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS }, 429 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS }, 430 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS }, 431 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS }, 432 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS }, 433 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS }, 434 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS }, 435 { /* sentinel */ } 436 }; 437 438 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv) 439 { 440 return clk_get_rate(&priv->clk); 441 } 442 443 static void renesas_sdhi_filter_caps(struct udevice *dev) 444 { 445 struct tmio_sd_plat *plat = dev_get_platdata(dev); 446 struct tmio_sd_priv *priv = dev_get_priv(dev); 447 448 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3)) 449 return; 450 451 /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */ 452 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && 453 (rmobile_get_cpu_rev_integer() <= 1)) || 454 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && 455 (rmobile_get_cpu_rev_integer() == 1) && 456 (rmobile_get_cpu_rev_fraction() <= 1))) 457 plat->cfg.host_caps &= ~MMC_MODE_HS400; 458 459 /* H3 ES2.0 uses 4 tuning taps */ 460 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && 461 (rmobile_get_cpu_rev_integer() == 2)) 462 priv->nrtaps = 4; 463 else 464 priv->nrtaps = 8; 465 } 466 467 static int renesas_sdhi_probe(struct udevice *dev) 468 { 469 struct tmio_sd_priv *priv = dev_get_priv(dev); 470 u32 quirks = dev_get_driver_data(dev); 471 struct fdt_resource reg_res; 472 DECLARE_GLOBAL_DATA_PTR; 473 int ret; 474 475 priv->clk_get_rate = renesas_sdhi_clk_get_rate; 476 477 if (quirks == RENESAS_GEN2_QUIRKS) { 478 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), 479 "reg", 0, ®_res); 480 if (ret < 0) { 481 dev_err(dev, "\"reg\" resource not found, ret=%i\n", 482 ret); 483 return ret; 484 } 485 486 if (fdt_resource_size(®_res) == 0x100) 487 quirks |= TMIO_SD_CAP_16BIT; 488 } 489 490 ret = clk_get_by_index(dev, 0, &priv->clk); 491 if (ret < 0) { 492 dev_err(dev, "failed to get host clock\n"); 493 return ret; 494 } 495 496 /* set to max rate */ 497 ret = clk_set_rate(&priv->clk, 200000000); 498 if (ret < 0) { 499 dev_err(dev, "failed to set rate for host clock\n"); 500 clk_free(&priv->clk); 501 return ret; 502 } 503 504 ret = clk_enable(&priv->clk); 505 if (ret) { 506 dev_err(dev, "failed to enable host clock\n"); 507 return ret; 508 } 509 510 ret = tmio_sd_probe(dev, quirks); 511 512 renesas_sdhi_filter_caps(dev); 513 514 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ 515 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ 516 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 517 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS)) 518 renesas_sdhi_reset_tuning(priv); 519 #endif 520 return ret; 521 } 522 523 U_BOOT_DRIVER(renesas_sdhi) = { 524 .name = "renesas-sdhi", 525 .id = UCLASS_MMC, 526 .of_match = renesas_sdhi_match, 527 .bind = tmio_sd_bind, 528 .probe = renesas_sdhi_probe, 529 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv), 530 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat), 531 .ops = &renesas_sdhi_ops, 532 }; 533