1 /* 2 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 3 * 4 * Loosely based on the old code and Linux's PXA MMC driver 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include <config.h> 23 #include <common.h> 24 #include <malloc.h> 25 26 #include <mmc.h> 27 #include <asm/errno.h> 28 #include <asm/arch/hardware.h> 29 #include <asm/arch/regs-mmc.h> 30 #include <asm/io.h> 31 32 /* PXAMMC Generic default config for various CPUs */ 33 #if defined(CONFIG_CPU_PXA25X) 34 #define PXAMMC_FIFO_SIZE 1 35 #define PXAMMC_MIN_SPEED 312500 36 #define PXAMMC_MAX_SPEED 20000000 37 #define PXAMMC_HOST_CAPS (0) 38 #elif defined(CONFIG_CPU_PXA27X) 39 #define PXAMMC_CRC_SKIP 40 #define PXAMMC_FIFO_SIZE 32 41 #define PXAMMC_MIN_SPEED 304000 42 #define PXAMMC_MAX_SPEED 19500000 43 #define PXAMMC_HOST_CAPS (MMC_MODE_4BIT) 44 #elif defined(CONFIG_CPU_MONAHANS) 45 #define PXAMMC_FIFO_SIZE 32 46 #define PXAMMC_MIN_SPEED 304000 47 #define PXAMMC_MAX_SPEED 26000000 48 #define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS) 49 #else 50 #error "This CPU isn't supported by PXA MMC!" 51 #endif 52 53 #define MMC_STAT_ERRORS \ 54 (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \ 55 MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \ 56 MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR) 57 58 /* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */ 59 #define PXA_MMC_TIMEOUT 100 60 61 struct pxa_mmc_priv { 62 struct pxa_mmc_regs *regs; 63 }; 64 65 /* Wait for bit to be set */ 66 static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) 67 { 68 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 69 struct pxa_mmc_regs *regs = priv->regs; 70 unsigned int timeout = PXA_MMC_TIMEOUT; 71 72 /* Wait for bit to be set */ 73 while (--timeout) { 74 if (readl(®s->stat) & mask) 75 break; 76 udelay(10); 77 } 78 79 if (!timeout) 80 return -ETIMEDOUT; 81 82 return 0; 83 } 84 85 static int pxa_mmc_stop_clock(struct mmc *mmc) 86 { 87 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 88 struct pxa_mmc_regs *regs = priv->regs; 89 unsigned int timeout = PXA_MMC_TIMEOUT; 90 91 /* If the clock aren't running, exit */ 92 if (!(readl(®s->stat) & MMC_STAT_CLK_EN)) 93 return 0; 94 95 /* Tell the controller to turn off the clock */ 96 writel(MMC_STRPCL_STOP_CLK, ®s->strpcl); 97 98 /* Wait until the clock are off */ 99 while (--timeout) { 100 if (!(readl(®s->stat) & MMC_STAT_CLK_EN)) 101 break; 102 udelay(10); 103 } 104 105 /* The clock refused to stop, scream and die a painful death */ 106 if (!timeout) 107 return -ETIMEDOUT; 108 109 /* The clock stopped correctly */ 110 return 0; 111 } 112 113 static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 114 uint32_t cmdat) 115 { 116 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 117 struct pxa_mmc_regs *regs = priv->regs; 118 int ret; 119 120 /* The card can send a "busy" response */ 121 if (cmd->flags & MMC_RSP_BUSY) 122 cmdat |= MMC_CMDAT_BUSY; 123 124 /* Inform the controller about response type */ 125 switch (cmd->resp_type) { 126 case MMC_RSP_R1: 127 case MMC_RSP_R1b: 128 cmdat |= MMC_CMDAT_R1; 129 break; 130 case MMC_RSP_R2: 131 cmdat |= MMC_CMDAT_R2; 132 break; 133 case MMC_RSP_R3: 134 cmdat |= MMC_CMDAT_R3; 135 break; 136 default: 137 break; 138 } 139 140 /* Load command and it's arguments into the controller */ 141 writel(cmd->cmdidx, ®s->cmd); 142 writel(cmd->cmdarg >> 16, ®s->argh); 143 writel(cmd->cmdarg & 0xffff, ®s->argl); 144 writel(cmdat, ®s->cmdat); 145 146 /* Start the controller clock and wait until they are started */ 147 writel(MMC_STRPCL_START_CLK, ®s->strpcl); 148 149 ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN); 150 if (ret) 151 return ret; 152 153 /* Correct and happy end */ 154 return 0; 155 } 156 157 static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) 158 { 159 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 160 struct pxa_mmc_regs *regs = priv->regs; 161 uint32_t a, b, c; 162 int i; 163 int stat; 164 165 /* Read the controller status */ 166 stat = readl(®s->stat); 167 168 /* 169 * Linux says: 170 * Did I mention this is Sick. We always need to 171 * discard the upper 8 bits of the first 16-bit word. 172 */ 173 a = readl(®s->res) & 0xffff; 174 for (i = 0; i < 4; i++) { 175 b = readl(®s->res) & 0xffff; 176 c = readl(®s->res) & 0xffff; 177 cmd->response[i] = (a << 24) | (b << 8) | (c >> 8); 178 a = c; 179 } 180 181 /* The command response didn't arrive */ 182 if (stat & MMC_STAT_TIME_OUT_RESPONSE) 183 return -ETIMEDOUT; 184 else if (stat & MMC_STAT_RES_CRC_ERROR && cmd->flags & MMC_RSP_CRC) { 185 #ifdef PXAMMC_CRC_SKIP 186 if (cmd->flags & MMC_RSP_136 && cmd->response[0] & (1 << 31)) 187 printf("Ignoring CRC, this may be dangerous!\n"); 188 else 189 #endif 190 return -EILSEQ; 191 } 192 193 /* The command response was successfully read */ 194 return 0; 195 } 196 197 static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) 198 { 199 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 200 struct pxa_mmc_regs *regs = priv->regs; 201 uint32_t len; 202 uint32_t *buf = (uint32_t *)data->dest; 203 int size; 204 int ret; 205 206 len = data->blocks * data->blocksize; 207 208 while (len) { 209 /* The controller has data ready */ 210 if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) { 211 size = min(len, PXAMMC_FIFO_SIZE); 212 len -= size; 213 size /= 4; 214 215 /* Read data into the buffer */ 216 while (size--) 217 *buf++ = readl(®s->rxfifo); 218 219 } 220 221 if (readl(®s->stat) & MMC_STAT_ERRORS) 222 return -EIO; 223 } 224 225 /* Wait for the transmission-done interrupt */ 226 ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE); 227 if (ret) 228 return ret; 229 230 return 0; 231 } 232 233 static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) 234 { 235 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 236 struct pxa_mmc_regs *regs = priv->regs; 237 uint32_t len; 238 uint32_t *buf = (uint32_t *)data->src; 239 int size; 240 int ret; 241 242 len = data->blocks * data->blocksize; 243 244 while (len) { 245 /* The controller is ready to receive data */ 246 if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) { 247 size = min(len, PXAMMC_FIFO_SIZE); 248 len -= size; 249 size /= 4; 250 251 while (size--) 252 writel(*buf++, ®s->txfifo); 253 254 if (min(len, PXAMMC_FIFO_SIZE) < 32) 255 writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf); 256 } 257 258 if (readl(®s->stat) & MMC_STAT_ERRORS) 259 return -EIO; 260 } 261 262 /* Wait for the transmission-done interrupt */ 263 ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE); 264 if (ret) 265 return ret; 266 267 /* Wait until the data are really written to the card */ 268 ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE); 269 if (ret) 270 return ret; 271 272 return 0; 273 } 274 275 static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, 276 struct mmc_data *data) 277 { 278 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 279 struct pxa_mmc_regs *regs = priv->regs; 280 uint32_t cmdat = 0; 281 int ret; 282 283 /* Stop the controller */ 284 ret = pxa_mmc_stop_clock(mmc); 285 if (ret) 286 return ret; 287 288 /* If we're doing data transfer, configure the controller accordingly */ 289 if (data) { 290 writel(data->blocks, ®s->nob); 291 writel(data->blocksize, ®s->blklen); 292 /* This delay can be optimized, but stick with max value */ 293 writel(0xffff, ®s->rdto); 294 cmdat |= MMC_CMDAT_DATA_EN; 295 if (data->flags & MMC_DATA_WRITE) 296 cmdat |= MMC_CMDAT_WRITE; 297 } 298 299 /* Run in 4bit mode if the card can do it */ 300 if (mmc->bus_width == 4) 301 cmdat |= MMC_CMDAT_SD_4DAT; 302 303 /* Execute the command */ 304 ret = pxa_mmc_start_cmd(mmc, cmd, cmdat); 305 if (ret) 306 return ret; 307 308 /* Wait until the command completes */ 309 ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES); 310 if (ret) 311 return ret; 312 313 /* Read back the result */ 314 ret = pxa_mmc_cmd_done(mmc, cmd); 315 if (ret) 316 return ret; 317 318 /* In case there was a data transfer scheduled, do it */ 319 if (data) { 320 if (data->flags & MMC_DATA_WRITE) 321 pxa_mmc_do_write_xfer(mmc, data); 322 else 323 pxa_mmc_do_read_xfer(mmc, data); 324 } 325 326 return 0; 327 } 328 329 static void pxa_mmc_set_ios(struct mmc *mmc) 330 { 331 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 332 struct pxa_mmc_regs *regs = priv->regs; 333 uint32_t tmp; 334 uint32_t pxa_mmc_clock; 335 336 if (!mmc->clock) { 337 pxa_mmc_stop_clock(mmc); 338 return; 339 } 340 341 /* PXA3xx can do 26MHz with special settings. */ 342 if (mmc->clock == 26000000) { 343 writel(0x7, ®s->clkrt); 344 return; 345 } 346 347 /* Set clock to the card the usual way. */ 348 pxa_mmc_clock = 0; 349 tmp = mmc->f_max / mmc->clock; 350 tmp += tmp % 2; 351 352 while (tmp > 1) { 353 pxa_mmc_clock++; 354 tmp >>= 1; 355 } 356 357 writel(pxa_mmc_clock, ®s->clkrt); 358 } 359 360 static int pxa_mmc_init(struct mmc *mmc) 361 { 362 struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; 363 struct pxa_mmc_regs *regs = priv->regs; 364 365 /* Make sure the clock are stopped */ 366 pxa_mmc_stop_clock(mmc); 367 368 /* Turn off SPI mode */ 369 writel(0, ®s->spi); 370 371 /* Set up maximum timeout to wait for command response */ 372 writel(MMC_RES_TO_MAX_MASK, ®s->resto); 373 374 /* Mask all interrupts */ 375 writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ), 376 ®s->i_mask); 377 return 0; 378 } 379 380 int pxa_mmc_register(int card_index) 381 { 382 struct mmc *mmc; 383 struct pxa_mmc_priv *priv; 384 uint32_t reg; 385 int ret = -ENOMEM; 386 387 mmc = malloc(sizeof(struct mmc)); 388 if (!mmc) 389 goto err0; 390 391 priv = malloc(sizeof(struct pxa_mmc_priv)); 392 if (!priv) 393 goto err1; 394 395 switch (card_index) { 396 case 0: 397 priv->regs = (struct pxa_mmc_regs *)MMC0_BASE; 398 break; 399 case 1: 400 priv->regs = (struct pxa_mmc_regs *)MMC1_BASE; 401 break; 402 default: 403 printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n", 404 card_index); 405 goto err2; 406 } 407 408 mmc->priv = priv; 409 410 sprintf(mmc->name, "PXA MMC"); 411 mmc->send_cmd = pxa_mmc_request; 412 mmc->set_ios = pxa_mmc_set_ios; 413 mmc->init = pxa_mmc_init; 414 mmc->getcd = NULL; 415 416 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 417 mmc->f_max = PXAMMC_MAX_SPEED; 418 mmc->f_min = PXAMMC_MIN_SPEED; 419 mmc->host_caps = PXAMMC_HOST_CAPS; 420 421 mmc->b_max = 0; 422 423 #ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ 424 reg = readl(CKEN); 425 reg |= CKEN12_MMC; 426 writel(reg, CKEN); 427 #else /* PXA3xx */ 428 reg = readl(CKENA); 429 reg |= CKENA_12_MMC0 | CKENA_13_MMC1; 430 writel(reg, CKENA); 431 #endif 432 433 mmc_register(mmc); 434 435 return 0; 436 437 err2: 438 free(priv); 439 err1: 440 free(mmc); 441 err0: 442 return ret; 443 } 444