xref: /openbmc/u-boot/drivers/mmc/pxa_mmc_gen.c (revision 1ea2301f)
1 /*
2  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
3  *
4  * Loosely based on the old code and Linux's PXA MMC driver
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <config.h>
10 #include <common.h>
11 #include <malloc.h>
12 
13 #include <mmc.h>
14 #include <asm/errno.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/regs-mmc.h>
17 #include <asm/io.h>
18 
19 /* PXAMMC Generic default config for various CPUs */
20 #if defined(CONFIG_CPU_PXA25X)
21 #define PXAMMC_FIFO_SIZE	1
22 #define PXAMMC_MIN_SPEED	312500
23 #define PXAMMC_MAX_SPEED	20000000
24 #define PXAMMC_HOST_CAPS	(0)
25 #elif defined(CONFIG_CPU_PXA27X)
26 #define PXAMMC_CRC_SKIP
27 #define PXAMMC_FIFO_SIZE	32
28 #define PXAMMC_MIN_SPEED	304000
29 #define PXAMMC_MAX_SPEED	19500000
30 #define PXAMMC_HOST_CAPS	(MMC_MODE_4BIT)
31 #elif defined(CONFIG_CPU_MONAHANS)
32 #define PXAMMC_FIFO_SIZE	32
33 #define PXAMMC_MIN_SPEED	304000
34 #define PXAMMC_MAX_SPEED	26000000
35 #define PXAMMC_HOST_CAPS	(MMC_MODE_4BIT | MMC_MODE_HS)
36 #else
37 #error "This CPU isn't supported by PXA MMC!"
38 #endif
39 
40 #define MMC_STAT_ERRORS							\
41 	(MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN |	\
42 	MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE |		\
43 	MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
44 
45 /* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
46 #define PXA_MMC_TIMEOUT	100
47 
48 struct pxa_mmc_priv {
49 	struct pxa_mmc_regs *regs;
50 };
51 
52 /* Wait for bit to be set */
53 static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
54 {
55 	struct pxa_mmc_priv *priv = mmc->priv;
56 	struct pxa_mmc_regs *regs = priv->regs;
57 	unsigned int timeout = PXA_MMC_TIMEOUT;
58 
59 	/* Wait for bit to be set */
60 	while (--timeout) {
61 		if (readl(&regs->stat) & mask)
62 			break;
63 		udelay(10);
64 	}
65 
66 	if (!timeout)
67 		return -ETIMEDOUT;
68 
69 	return 0;
70 }
71 
72 static int pxa_mmc_stop_clock(struct mmc *mmc)
73 {
74 	struct pxa_mmc_priv *priv = mmc->priv;
75 	struct pxa_mmc_regs *regs = priv->regs;
76 	unsigned int timeout = PXA_MMC_TIMEOUT;
77 
78 	/* If the clock aren't running, exit */
79 	if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
80 		return 0;
81 
82 	/* Tell the controller to turn off the clock */
83 	writel(MMC_STRPCL_STOP_CLK, &regs->strpcl);
84 
85 	/* Wait until the clock are off */
86 	while (--timeout) {
87 		if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
88 			break;
89 		udelay(10);
90 	}
91 
92 	/* The clock refused to stop, scream and die a painful death */
93 	if (!timeout)
94 		return -ETIMEDOUT;
95 
96 	/* The clock stopped correctly */
97 	return 0;
98 }
99 
100 static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
101 				uint32_t cmdat)
102 {
103 	struct pxa_mmc_priv *priv = mmc->priv;
104 	struct pxa_mmc_regs *regs = priv->regs;
105 	int ret;
106 
107 	/* The card can send a "busy" response */
108 	if (cmd->resp_type & MMC_RSP_BUSY)
109 		cmdat |= MMC_CMDAT_BUSY;
110 
111 	/* Inform the controller about response type */
112 	switch (cmd->resp_type) {
113 	case MMC_RSP_R1:
114 	case MMC_RSP_R1b:
115 		cmdat |= MMC_CMDAT_R1;
116 		break;
117 	case MMC_RSP_R2:
118 		cmdat |= MMC_CMDAT_R2;
119 		break;
120 	case MMC_RSP_R3:
121 		cmdat |= MMC_CMDAT_R3;
122 		break;
123 	default:
124 		break;
125 	}
126 
127 	/* Load command and it's arguments into the controller */
128 	writel(cmd->cmdidx, &regs->cmd);
129 	writel(cmd->cmdarg >> 16, &regs->argh);
130 	writel(cmd->cmdarg & 0xffff, &regs->argl);
131 	writel(cmdat, &regs->cmdat);
132 
133 	/* Start the controller clock and wait until they are started */
134 	writel(MMC_STRPCL_START_CLK, &regs->strpcl);
135 
136 	ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
137 	if (ret)
138 		return ret;
139 
140 	/* Correct and happy end */
141 	return 0;
142 }
143 
144 static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
145 {
146 	struct pxa_mmc_priv *priv = mmc->priv;
147 	struct pxa_mmc_regs *regs = priv->regs;
148 	uint32_t a, b, c;
149 	int i;
150 	int stat;
151 
152 	/* Read the controller status */
153 	stat = readl(&regs->stat);
154 
155 	/*
156 	 * Linux says:
157 	 * Did I mention this is Sick.  We always need to
158 	 * discard the upper 8 bits of the first 16-bit word.
159 	 */
160 	a = readl(&regs->res) & 0xffff;
161 	for (i = 0; i < 4; i++) {
162 		b = readl(&regs->res) & 0xffff;
163 		c = readl(&regs->res) & 0xffff;
164 		cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
165 		a = c;
166 	}
167 
168 	/* The command response didn't arrive */
169 	if (stat & MMC_STAT_TIME_OUT_RESPONSE)
170 		return -ETIMEDOUT;
171 	else if (stat & MMC_STAT_RES_CRC_ERROR
172 			&& cmd->resp_type & MMC_RSP_CRC) {
173 #ifdef	PXAMMC_CRC_SKIP
174 		if (cmd->resp_type & MMC_RSP_136
175 				&& cmd->response[0] & (1 << 31))
176 			printf("Ignoring CRC, this may be dangerous!\n");
177 		else
178 #endif
179 		return -EILSEQ;
180 	}
181 
182 	/* The command response was successfully read */
183 	return 0;
184 }
185 
186 static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
187 {
188 	struct pxa_mmc_priv *priv = mmc->priv;
189 	struct pxa_mmc_regs *regs = priv->regs;
190 	uint32_t len;
191 	uint32_t *buf = (uint32_t *)data->dest;
192 	int size;
193 	int ret;
194 
195 	len = data->blocks * data->blocksize;
196 
197 	while (len) {
198 		/* The controller has data ready */
199 		if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
200 			size = min(len, PXAMMC_FIFO_SIZE);
201 			len -= size;
202 			size /= 4;
203 
204 			/* Read data into the buffer */
205 			while (size--)
206 				*buf++ = readl(&regs->rxfifo);
207 
208 		}
209 
210 		if (readl(&regs->stat) & MMC_STAT_ERRORS)
211 			return -EIO;
212 	}
213 
214 	/* Wait for the transmission-done interrupt */
215 	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
216 	if (ret)
217 		return ret;
218 
219 	return 0;
220 }
221 
222 static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
223 {
224 	struct pxa_mmc_priv *priv = mmc->priv;
225 	struct pxa_mmc_regs *regs = priv->regs;
226 	uint32_t len;
227 	uint32_t *buf = (uint32_t *)data->src;
228 	int size;
229 	int ret;
230 
231 	len = data->blocks * data->blocksize;
232 
233 	while (len) {
234 		/* The controller is ready to receive data */
235 		if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
236 			size = min(len, PXAMMC_FIFO_SIZE);
237 			len -= size;
238 			size /= 4;
239 
240 			while (size--)
241 				writel(*buf++, &regs->txfifo);
242 
243 			if (min(len, PXAMMC_FIFO_SIZE) < 32)
244 				writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf);
245 		}
246 
247 		if (readl(&regs->stat) & MMC_STAT_ERRORS)
248 			return -EIO;
249 	}
250 
251 	/* Wait for the transmission-done interrupt */
252 	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
253 	if (ret)
254 		return ret;
255 
256 	/* Wait until the data are really written to the card */
257 	ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
258 	if (ret)
259 		return ret;
260 
261 	return 0;
262 }
263 
264 static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
265 				struct mmc_data *data)
266 {
267 	struct pxa_mmc_priv *priv = mmc->priv;
268 	struct pxa_mmc_regs *regs = priv->regs;
269 	uint32_t cmdat = 0;
270 	int ret;
271 
272 	/* Stop the controller */
273 	ret = pxa_mmc_stop_clock(mmc);
274 	if (ret)
275 		return ret;
276 
277 	/* If we're doing data transfer, configure the controller accordingly */
278 	if (data) {
279 		writel(data->blocks, &regs->nob);
280 		writel(data->blocksize, &regs->blklen);
281 		/* This delay can be optimized, but stick with max value */
282 		writel(0xffff, &regs->rdto);
283 		cmdat |= MMC_CMDAT_DATA_EN;
284 		if (data->flags & MMC_DATA_WRITE)
285 			cmdat |= MMC_CMDAT_WRITE;
286 	}
287 
288 	/* Run in 4bit mode if the card can do it */
289 	if (mmc->bus_width == 4)
290 		cmdat |= MMC_CMDAT_SD_4DAT;
291 
292 	/* Execute the command */
293 	ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
294 	if (ret)
295 		return ret;
296 
297 	/* Wait until the command completes */
298 	ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
299 	if (ret)
300 		return ret;
301 
302 	/* Read back the result */
303 	ret = pxa_mmc_cmd_done(mmc, cmd);
304 	if (ret)
305 		return ret;
306 
307 	/* In case there was a data transfer scheduled, do it */
308 	if (data) {
309 		if (data->flags & MMC_DATA_WRITE)
310 			pxa_mmc_do_write_xfer(mmc, data);
311 		else
312 			pxa_mmc_do_read_xfer(mmc, data);
313 	}
314 
315 	return 0;
316 }
317 
318 static void pxa_mmc_set_ios(struct mmc *mmc)
319 {
320 	struct pxa_mmc_priv *priv = mmc->priv;
321 	struct pxa_mmc_regs *regs = priv->regs;
322 	uint32_t tmp;
323 	uint32_t pxa_mmc_clock;
324 
325 	if (!mmc->clock) {
326 		pxa_mmc_stop_clock(mmc);
327 		return;
328 	}
329 
330 	/* PXA3xx can do 26MHz with special settings. */
331 	if (mmc->clock == 26000000) {
332 		writel(0x7, &regs->clkrt);
333 		return;
334 	}
335 
336 	/* Set clock to the card the usual way. */
337 	pxa_mmc_clock = 0;
338 	tmp = mmc->cfg->f_max / mmc->clock;
339 	tmp += tmp % 2;
340 
341 	while (tmp > 1) {
342 		pxa_mmc_clock++;
343 		tmp >>= 1;
344 	}
345 
346 	writel(pxa_mmc_clock, &regs->clkrt);
347 }
348 
349 static int pxa_mmc_init(struct mmc *mmc)
350 {
351 	struct pxa_mmc_priv *priv = mmc->priv;
352 	struct pxa_mmc_regs *regs = priv->regs;
353 
354 	/* Make sure the clock are stopped */
355 	pxa_mmc_stop_clock(mmc);
356 
357 	/* Turn off SPI mode */
358 	writel(0, &regs->spi);
359 
360 	/* Set up maximum timeout to wait for command response */
361 	writel(MMC_RES_TO_MAX_MASK, &regs->resto);
362 
363 	/* Mask all interrupts */
364 	writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
365 		&regs->i_mask);
366 	return 0;
367 }
368 
369 static const struct mmc_ops pxa_mmc_ops = {
370 	.send_cmd	= pxa_mmc_request,
371 	.set_ios	= pxa_mmc_set_ios,
372 	.init		= pxa_mmc_init,
373 };
374 
375 static struct mmc_config pxa_mmc_cfg = {
376 	.name		= "PXA MMC",
377 	.ops		= &pxa_mmc_ops,
378 	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
379 	.f_max		= PXAMMC_MAX_SPEED,
380 	.f_min		= PXAMMC_MIN_SPEED,
381 	.host_caps	= PXAMMC_HOST_CAPS,
382 	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
383 };
384 
385 int pxa_mmc_register(int card_index)
386 {
387 	struct mmc *mmc;
388 	struct pxa_mmc_priv *priv;
389 	uint32_t reg;
390 	int ret = -ENOMEM;
391 
392 	priv = malloc(sizeof(struct pxa_mmc_priv));
393 	if (!priv)
394 		goto err0;
395 
396 	memset(priv, 0, sizeof(*priv));
397 
398 	switch (card_index) {
399 	case 0:
400 		priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
401 		break;
402 	case 1:
403 		priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
404 		break;
405 	default:
406 		ret = -EINVAL;
407 		printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
408 			card_index);
409 		goto err1;
410 	}
411 
412 #ifndef	CONFIG_CPU_MONAHANS	/* PXA2xx */
413 	reg = readl(CKEN);
414 	reg |= CKEN12_MMC;
415 	writel(reg, CKEN);
416 #else				/* PXA3xx */
417 	reg = readl(CKENA);
418 	reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
419 	writel(reg, CKENA);
420 #endif
421 
422 	mmc = mmc_create(&pxa_mmc_cfg, priv);
423 	if (mmc == NULL)
424 		goto err1;
425 
426 	return 0;
427 
428 err1:
429 	free(priv);
430 err0:
431 	return ret;
432 }
433