1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <malloc.h> 28 #include <mmc.h> 29 #include <part.h> 30 #include <i2c.h> 31 #include <twl4030.h> 32 #include <twl6030.h> 33 #include <palmas.h> 34 #include <asm/io.h> 35 #include <asm/arch/mmc_host_def.h> 36 #if !defined(CONFIG_SOC_KEYSTONE) 37 #include <asm/gpio.h> 38 #include <asm/arch/sys_proto.h> 39 #endif 40 #ifdef CONFIG_MMC_OMAP36XX_PINS 41 #include <asm/arch/mux.h> 42 #endif 43 #include <dm.h> 44 45 DECLARE_GLOBAL_DATA_PTR; 46 47 /* simplify defines to OMAP_HSMMC_USE_GPIO */ 48 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ 49 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) 50 #define OMAP_HSMMC_USE_GPIO 51 #else 52 #undef OMAP_HSMMC_USE_GPIO 53 #endif 54 55 /* common definitions for all OMAPs */ 56 #define SYSCTL_SRC (1 << 25) 57 #define SYSCTL_SRD (1 << 26) 58 59 struct omap2_mmc_platform_config { 60 u32 reg_offset; 61 }; 62 63 struct omap_hsmmc_data { 64 struct hsmmc *base_addr; 65 #ifndef CONFIG_DM_MMC 66 struct mmc_config cfg; 67 #endif 68 #ifdef OMAP_HSMMC_USE_GPIO 69 #ifdef CONFIG_DM_MMC 70 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 71 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 72 bool cd_inverted; 73 #else 74 int cd_gpio; 75 int wp_gpio; 76 #endif 77 #endif 78 }; 79 80 /* If we fail after 1 second wait, something is really bad */ 81 #define MAX_RETRY_MS 1000 82 83 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 84 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 85 unsigned int siz); 86 87 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) 88 { 89 #ifdef CONFIG_DM_MMC 90 return dev_get_priv(mmc->dev); 91 #else 92 return (struct omap_hsmmc_data *)mmc->priv; 93 #endif 94 } 95 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) 96 { 97 #ifdef CONFIG_DM_MMC 98 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); 99 return &plat->cfg; 100 #else 101 return &((struct omap_hsmmc_data *)mmc->priv)->cfg; 102 #endif 103 } 104 105 #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC) 106 static int omap_mmc_setup_gpio_in(int gpio, const char *label) 107 { 108 int ret; 109 110 #ifndef CONFIG_DM_GPIO 111 if (!gpio_is_valid(gpio)) 112 return -1; 113 #endif 114 ret = gpio_request(gpio, label); 115 if (ret) 116 return ret; 117 118 ret = gpio_direction_input(gpio); 119 if (ret) 120 return ret; 121 122 return gpio; 123 } 124 #endif 125 126 static unsigned char mmc_board_init(struct mmc *mmc) 127 { 128 #if defined(CONFIG_OMAP34XX) 129 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); 130 t2_t *t2_base = (t2_t *)T2_BASE; 131 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 132 u32 pbias_lite; 133 #ifdef CONFIG_MMC_OMAP36XX_PINS 134 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); 135 #endif 136 137 pbias_lite = readl(&t2_base->pbias_lite); 138 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 139 #ifdef CONFIG_TARGET_OMAP3_CAIRO 140 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ 141 pbias_lite &= ~PBIASLITEVMODE0; 142 #endif 143 #ifdef CONFIG_MMC_OMAP36XX_PINS 144 if (get_cpu_family() == CPU_OMAP36XX) { 145 /* Disable extended drain IO before changing PBIAS */ 146 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; 147 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); 148 } 149 #endif 150 writel(pbias_lite, &t2_base->pbias_lite); 151 152 writel(pbias_lite | PBIASLITEPWRDNZ1 | 153 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 154 &t2_base->pbias_lite); 155 156 #ifdef CONFIG_MMC_OMAP36XX_PINS 157 if (get_cpu_family() == CPU_OMAP36XX) 158 /* Enable extended drain IO after changing PBIAS */ 159 writel(wkup_ctrl | 160 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, 161 OMAP34XX_CTRL_WKUP_CTRL); 162 #endif 163 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 164 &t2_base->devconf0); 165 166 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 167 &t2_base->devconf1); 168 169 /* Change from default of 52MHz to 26MHz if necessary */ 170 if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) 171 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, 172 &t2_base->ctl_prog_io1); 173 174 writel(readl(&prcm_base->fclken1_core) | 175 EN_MMC1 | EN_MMC2 | EN_MMC3, 176 &prcm_base->fclken1_core); 177 178 writel(readl(&prcm_base->iclken1_core) | 179 EN_MMC1 | EN_MMC2 | EN_MMC3, 180 &prcm_base->iclken1_core); 181 #endif 182 183 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) 184 /* PBIAS config needed for MMC1 only */ 185 if (mmc_get_blk_desc(mmc)->devnum == 0) 186 vmmc_pbias_config(LDO_VOLT_3V0); 187 #endif 188 189 return 0; 190 } 191 192 void mmc_init_stream(struct hsmmc *mmc_base) 193 { 194 ulong start; 195 196 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 197 198 writel(MMC_CMD0, &mmc_base->cmd); 199 start = get_timer(0); 200 while (!(readl(&mmc_base->stat) & CC_MASK)) { 201 if (get_timer(0) - start > MAX_RETRY_MS) { 202 printf("%s: timedout waiting for cc!\n", __func__); 203 return; 204 } 205 } 206 writel(CC_MASK, &mmc_base->stat) 207 ; 208 writel(MMC_CMD0, &mmc_base->cmd) 209 ; 210 start = get_timer(0); 211 while (!(readl(&mmc_base->stat) & CC_MASK)) { 212 if (get_timer(0) - start > MAX_RETRY_MS) { 213 printf("%s: timedout waiting for cc2!\n", __func__); 214 return; 215 } 216 } 217 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 218 } 219 220 static int omap_hsmmc_init_setup(struct mmc *mmc) 221 { 222 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 223 struct hsmmc *mmc_base; 224 unsigned int reg_val; 225 unsigned int dsor; 226 ulong start; 227 228 mmc_base = priv->base_addr; 229 mmc_board_init(mmc); 230 231 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 232 &mmc_base->sysconfig); 233 start = get_timer(0); 234 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 235 if (get_timer(0) - start > MAX_RETRY_MS) { 236 printf("%s: timedout waiting for cc2!\n", __func__); 237 return -ETIMEDOUT; 238 } 239 } 240 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 241 start = get_timer(0); 242 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 243 if (get_timer(0) - start > MAX_RETRY_MS) { 244 printf("%s: timedout waiting for softresetall!\n", 245 __func__); 246 return -ETIMEDOUT; 247 } 248 } 249 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 250 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 251 &mmc_base->capa); 252 253 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 254 255 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 256 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 257 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 258 259 dsor = 240; 260 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 261 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 262 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 263 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 264 start = get_timer(0); 265 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 266 if (get_timer(0) - start > MAX_RETRY_MS) { 267 printf("%s: timedout waiting for ics!\n", __func__); 268 return -ETIMEDOUT; 269 } 270 } 271 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 272 273 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 274 275 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 276 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 277 &mmc_base->ie); 278 279 mmc_init_stream(mmc_base); 280 281 return 0; 282 } 283 284 /* 285 * MMC controller internal finite state machine reset 286 * 287 * Used to reset command or data internal state machines, using respectively 288 * SRC or SRD bit of SYSCTL register 289 */ 290 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 291 { 292 ulong start; 293 294 mmc_reg_out(&mmc_base->sysctl, bit, bit); 295 296 /* 297 * CMD(DAT) lines reset procedures are slightly different 298 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). 299 * According to OMAP3 TRM: 300 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it 301 * returns to 0x0. 302 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset 303 * procedure steps must be as follows: 304 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in 305 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). 306 * 2. Poll the SRC(SRD) bit until it is set to 0x1. 307 * 3. Wait until the SRC (SRD) bit returns to 0x0 308 * (reset procedure is completed). 309 */ 310 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 311 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) 312 if (!(readl(&mmc_base->sysctl) & bit)) { 313 start = get_timer(0); 314 while (!(readl(&mmc_base->sysctl) & bit)) { 315 if (get_timer(0) - start > MAX_RETRY_MS) 316 return; 317 } 318 } 319 #endif 320 start = get_timer(0); 321 while ((readl(&mmc_base->sysctl) & bit) != 0) { 322 if (get_timer(0) - start > MAX_RETRY_MS) { 323 printf("%s: timedout waiting for sysctl %x to clear\n", 324 __func__, bit); 325 return; 326 } 327 } 328 } 329 330 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 331 struct mmc_data *data) 332 { 333 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 334 struct hsmmc *mmc_base; 335 unsigned int flags, mmc_stat; 336 ulong start; 337 338 mmc_base = priv->base_addr; 339 start = get_timer(0); 340 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 341 if (get_timer(0) - start > MAX_RETRY_MS) { 342 printf("%s: timedout waiting on cmd inhibit to clear\n", 343 __func__); 344 return -ETIMEDOUT; 345 } 346 } 347 writel(0xFFFFFFFF, &mmc_base->stat); 348 start = get_timer(0); 349 while (readl(&mmc_base->stat)) { 350 if (get_timer(0) - start > MAX_RETRY_MS) { 351 printf("%s: timedout waiting for STAT (%x) to clear\n", 352 __func__, readl(&mmc_base->stat)); 353 return -ETIMEDOUT; 354 } 355 } 356 /* 357 * CMDREG 358 * CMDIDX[13:8] : Command index 359 * DATAPRNT[5] : Data Present Select 360 * ENCMDIDX[4] : Command Index Check Enable 361 * ENCMDCRC[3] : Command CRC Check Enable 362 * RSPTYP[1:0] 363 * 00 = No Response 364 * 01 = Length 136 365 * 10 = Length 48 366 * 11 = Length 48 Check busy after response 367 */ 368 /* Delay added before checking the status of frq change 369 * retry not supported by mmc.c(core file) 370 */ 371 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 372 udelay(50000); /* wait 50 ms */ 373 374 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 375 flags = 0; 376 else if (cmd->resp_type & MMC_RSP_136) 377 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 378 else if (cmd->resp_type & MMC_RSP_BUSY) 379 flags = RSP_TYPE_LGHT48B; 380 else 381 flags = RSP_TYPE_LGHT48; 382 383 /* enable default flags */ 384 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 385 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 386 387 if (cmd->resp_type & MMC_RSP_CRC) 388 flags |= CCCE_CHECK; 389 if (cmd->resp_type & MMC_RSP_OPCODE) 390 flags |= CICE_CHECK; 391 392 if (data) { 393 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 394 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 395 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 396 data->blocksize = 512; 397 writel(data->blocksize | (data->blocks << 16), 398 &mmc_base->blk); 399 } else 400 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 401 402 if (data->flags & MMC_DATA_READ) 403 flags |= (DP_DATA | DDIR_READ); 404 else 405 flags |= (DP_DATA | DDIR_WRITE); 406 } 407 408 writel(cmd->cmdarg, &mmc_base->arg); 409 udelay(20); /* To fix "No status update" error on eMMC */ 410 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 411 412 start = get_timer(0); 413 do { 414 mmc_stat = readl(&mmc_base->stat); 415 if (get_timer(0) - start > MAX_RETRY_MS) { 416 printf("%s : timeout: No status update\n", __func__); 417 return -ETIMEDOUT; 418 } 419 } while (!mmc_stat); 420 421 if ((mmc_stat & IE_CTO) != 0) { 422 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 423 return -ETIMEDOUT; 424 } else if ((mmc_stat & ERRI_MASK) != 0) 425 return -1; 426 427 if (mmc_stat & CC_MASK) { 428 writel(CC_MASK, &mmc_base->stat); 429 if (cmd->resp_type & MMC_RSP_PRESENT) { 430 if (cmd->resp_type & MMC_RSP_136) { 431 /* response type 2 */ 432 cmd->response[3] = readl(&mmc_base->rsp10); 433 cmd->response[2] = readl(&mmc_base->rsp32); 434 cmd->response[1] = readl(&mmc_base->rsp54); 435 cmd->response[0] = readl(&mmc_base->rsp76); 436 } else 437 /* response types 1, 1b, 3, 4, 5, 6 */ 438 cmd->response[0] = readl(&mmc_base->rsp10); 439 } 440 } 441 442 if (data && (data->flags & MMC_DATA_READ)) { 443 mmc_read_data(mmc_base, data->dest, 444 data->blocksize * data->blocks); 445 } else if (data && (data->flags & MMC_DATA_WRITE)) { 446 mmc_write_data(mmc_base, data->src, 447 data->blocksize * data->blocks); 448 } 449 return 0; 450 } 451 452 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 453 { 454 unsigned int *output_buf = (unsigned int *)buf; 455 unsigned int mmc_stat; 456 unsigned int count; 457 458 /* 459 * Start Polled Read 460 */ 461 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 462 count /= 4; 463 464 while (size) { 465 ulong start = get_timer(0); 466 do { 467 mmc_stat = readl(&mmc_base->stat); 468 if (get_timer(0) - start > MAX_RETRY_MS) { 469 printf("%s: timedout waiting for status!\n", 470 __func__); 471 return -ETIMEDOUT; 472 } 473 } while (mmc_stat == 0); 474 475 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 476 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 477 478 if ((mmc_stat & ERRI_MASK) != 0) 479 return 1; 480 481 if (mmc_stat & BRR_MASK) { 482 unsigned int k; 483 484 writel(readl(&mmc_base->stat) | BRR_MASK, 485 &mmc_base->stat); 486 for (k = 0; k < count; k++) { 487 *output_buf = readl(&mmc_base->data); 488 output_buf++; 489 } 490 size -= (count*4); 491 } 492 493 if (mmc_stat & BWR_MASK) 494 writel(readl(&mmc_base->stat) | BWR_MASK, 495 &mmc_base->stat); 496 497 if (mmc_stat & TC_MASK) { 498 writel(readl(&mmc_base->stat) | TC_MASK, 499 &mmc_base->stat); 500 break; 501 } 502 } 503 return 0; 504 } 505 506 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 507 unsigned int size) 508 { 509 unsigned int *input_buf = (unsigned int *)buf; 510 unsigned int mmc_stat; 511 unsigned int count; 512 513 /* 514 * Start Polled Write 515 */ 516 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 517 count /= 4; 518 519 while (size) { 520 ulong start = get_timer(0); 521 do { 522 mmc_stat = readl(&mmc_base->stat); 523 if (get_timer(0) - start > MAX_RETRY_MS) { 524 printf("%s: timedout waiting for status!\n", 525 __func__); 526 return -ETIMEDOUT; 527 } 528 } while (mmc_stat == 0); 529 530 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 531 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 532 533 if ((mmc_stat & ERRI_MASK) != 0) 534 return 1; 535 536 if (mmc_stat & BWR_MASK) { 537 unsigned int k; 538 539 writel(readl(&mmc_base->stat) | BWR_MASK, 540 &mmc_base->stat); 541 for (k = 0; k < count; k++) { 542 writel(*input_buf, &mmc_base->data); 543 input_buf++; 544 } 545 size -= (count*4); 546 } 547 548 if (mmc_stat & BRR_MASK) 549 writel(readl(&mmc_base->stat) | BRR_MASK, 550 &mmc_base->stat); 551 552 if (mmc_stat & TC_MASK) { 553 writel(readl(&mmc_base->stat) | TC_MASK, 554 &mmc_base->stat); 555 break; 556 } 557 } 558 return 0; 559 } 560 561 static int omap_hsmmc_set_ios(struct mmc *mmc) 562 { 563 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 564 struct hsmmc *mmc_base; 565 unsigned int dsor = 0; 566 ulong start; 567 568 mmc_base = priv->base_addr; 569 /* configue bus width */ 570 switch (mmc->bus_width) { 571 case 8: 572 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 573 &mmc_base->con); 574 break; 575 576 case 4: 577 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 578 &mmc_base->con); 579 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 580 &mmc_base->hctl); 581 break; 582 583 case 1: 584 default: 585 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 586 &mmc_base->con); 587 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 588 &mmc_base->hctl); 589 break; 590 } 591 592 /* configure clock with 96Mhz system clock. 593 */ 594 if (mmc->clock != 0) { 595 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 596 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 597 dsor++; 598 } 599 600 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 601 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 602 603 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 604 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 605 606 start = get_timer(0); 607 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 608 if (get_timer(0) - start > MAX_RETRY_MS) { 609 printf("%s: timedout waiting for ics!\n", __func__); 610 return -ETIMEDOUT; 611 } 612 } 613 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 614 615 return 0; 616 } 617 618 #ifdef OMAP_HSMMC_USE_GPIO 619 #ifdef CONFIG_DM_MMC 620 static int omap_hsmmc_getcd(struct mmc *mmc) 621 { 622 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 623 int value; 624 625 value = dm_gpio_get_value(&priv->cd_gpio); 626 /* if no CD return as 1 */ 627 if (value < 0) 628 return 1; 629 630 if (priv->cd_inverted) 631 return !value; 632 return value; 633 } 634 635 static int omap_hsmmc_getwp(struct mmc *mmc) 636 { 637 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 638 int value; 639 640 value = dm_gpio_get_value(&priv->wp_gpio); 641 /* if no WP return as 0 */ 642 if (value < 0) 643 return 0; 644 return value; 645 } 646 #else 647 static int omap_hsmmc_getcd(struct mmc *mmc) 648 { 649 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 650 int cd_gpio; 651 652 /* if no CD return as 1 */ 653 cd_gpio = priv->cd_gpio; 654 if (cd_gpio < 0) 655 return 1; 656 657 /* NOTE: assumes card detect signal is active-low */ 658 return !gpio_get_value(cd_gpio); 659 } 660 661 static int omap_hsmmc_getwp(struct mmc *mmc) 662 { 663 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 664 int wp_gpio; 665 666 /* if no WP return as 0 */ 667 wp_gpio = priv->wp_gpio; 668 if (wp_gpio < 0) 669 return 0; 670 671 /* NOTE: assumes write protect signal is active-high */ 672 return gpio_get_value(wp_gpio); 673 } 674 #endif 675 #endif 676 677 static const struct mmc_ops omap_hsmmc_ops = { 678 .send_cmd = omap_hsmmc_send_cmd, 679 .set_ios = omap_hsmmc_set_ios, 680 .init = omap_hsmmc_init_setup, 681 #ifdef OMAP_HSMMC_USE_GPIO 682 .getcd = omap_hsmmc_getcd, 683 .getwp = omap_hsmmc_getwp, 684 #endif 685 }; 686 687 #ifndef CONFIG_DM_MMC 688 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 689 int wp_gpio) 690 { 691 struct mmc *mmc; 692 struct omap_hsmmc_data *priv; 693 struct mmc_config *cfg; 694 uint host_caps_val; 695 696 priv = malloc(sizeof(*priv)); 697 if (priv == NULL) 698 return -1; 699 700 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; 701 702 switch (dev_index) { 703 case 0: 704 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 705 break; 706 #ifdef OMAP_HSMMC2_BASE 707 case 1: 708 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; 709 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 710 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ 711 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ 712 defined(CONFIG_HSMMC2_8BIT) 713 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ 714 host_caps_val |= MMC_MODE_8BIT; 715 #endif 716 break; 717 #endif 718 #ifdef OMAP_HSMMC3_BASE 719 case 2: 720 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; 721 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) 722 /* Enable 8-bit interface for eMMC on DRA7XX */ 723 host_caps_val |= MMC_MODE_8BIT; 724 #endif 725 break; 726 #endif 727 default: 728 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 729 return 1; 730 } 731 #ifdef OMAP_HSMMC_USE_GPIO 732 /* on error gpio values are set to -1, which is what we want */ 733 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); 734 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); 735 #endif 736 737 cfg = &priv->cfg; 738 739 cfg->name = "OMAP SD/MMC"; 740 cfg->ops = &omap_hsmmc_ops; 741 742 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 743 cfg->host_caps = host_caps_val & ~host_caps_mask; 744 745 cfg->f_min = 400000; 746 747 if (f_max != 0) 748 cfg->f_max = f_max; 749 else { 750 if (cfg->host_caps & MMC_MODE_HS) { 751 if (cfg->host_caps & MMC_MODE_HS_52MHz) 752 cfg->f_max = 52000000; 753 else 754 cfg->f_max = 26000000; 755 } else 756 cfg->f_max = 20000000; 757 } 758 759 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 760 761 #if defined(CONFIG_OMAP34XX) 762 /* 763 * Silicon revs 2.1 and older do not support multiblock transfers. 764 */ 765 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 766 cfg->b_max = 1; 767 #endif 768 mmc = mmc_create(cfg, priv); 769 if (mmc == NULL) 770 return -1; 771 772 return 0; 773 } 774 #else 775 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 776 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) 777 { 778 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 779 struct mmc_config *cfg = &plat->cfg; 780 struct omap2_mmc_platform_config *data = 781 (struct omap2_mmc_platform_config *)dev_get_driver_data(dev); 782 const void *fdt = gd->fdt_blob; 783 int node = dev_of_offset(dev); 784 int val; 785 786 plat->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *), 787 MAP_NOCACHE) + data->reg_offset; 788 789 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; 790 val = fdtdec_get_int(fdt, node, "bus-width", -1); 791 if (val < 0) { 792 printf("error: bus-width property missing\n"); 793 return -ENOENT; 794 } 795 796 switch (val) { 797 case 0x8: 798 cfg->host_caps |= MMC_MODE_8BIT; 799 case 0x4: 800 cfg->host_caps |= MMC_MODE_4BIT; 801 break; 802 default: 803 printf("error: invalid bus-width property\n"); 804 return -ENOENT; 805 } 806 807 cfg->f_min = 400000; 808 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); 809 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 810 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 811 812 #ifdef OMAP_HSMMC_USE_GPIO 813 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); 814 #endif 815 816 return 0; 817 } 818 #endif 819 820 #ifdef CONFIG_BLK 821 822 static int omap_hsmmc_bind(struct udevice *dev) 823 { 824 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 825 826 return mmc_bind(dev, &plat->mmc, &plat->cfg); 827 } 828 #endif 829 static int omap_hsmmc_probe(struct udevice *dev) 830 { 831 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 832 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 833 struct omap_hsmmc_data *priv = dev_get_priv(dev); 834 struct mmc_config *cfg = &plat->cfg; 835 struct mmc *mmc; 836 837 cfg->name = "OMAP SD/MMC"; 838 cfg->ops = &omap_hsmmc_ops; 839 priv->base_addr = plat->base_addr; 840 #ifdef OMAP_HSMMC_USE_GPIO 841 priv->cd_inverted = plat->cd_inverted; 842 #endif 843 844 #ifdef CONFIG_BLK 845 mmc = &plat->mmc; 846 #else 847 mmc = mmc_create(cfg, priv); 848 if (mmc == NULL) 849 return -1; 850 #endif 851 852 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL) 853 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); 854 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); 855 #endif 856 857 mmc->dev = dev; 858 upriv->mmc = mmc; 859 860 return 0; 861 } 862 863 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 864 static const struct omap2_mmc_platform_config omap3_mmc_pdata = { 865 .reg_offset = 0, 866 }; 867 868 static const struct omap2_mmc_platform_config am33xx_mmc_pdata = { 869 .reg_offset = 0x100, 870 }; 871 872 static const struct omap2_mmc_platform_config omap4_mmc_pdata = { 873 .reg_offset = 0x100, 874 }; 875 876 static const struct udevice_id omap_hsmmc_ids[] = { 877 { 878 .compatible = "ti,omap3-hsmmc", 879 .data = (ulong)&omap3_mmc_pdata 880 }, 881 { 882 .compatible = "ti,omap4-hsmmc", 883 .data = (ulong)&omap4_mmc_pdata 884 }, 885 { 886 .compatible = "ti,am33xx-hsmmc", 887 .data = (ulong)&am33xx_mmc_pdata 888 }, 889 { } 890 }; 891 #endif 892 893 U_BOOT_DRIVER(omap_hsmmc) = { 894 .name = "omap_hsmmc", 895 .id = UCLASS_MMC, 896 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 897 .of_match = omap_hsmmc_ids, 898 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, 899 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat), 900 #endif 901 #ifdef CONFIG_BLK 902 .bind = omap_hsmmc_bind, 903 #endif 904 .probe = omap_hsmmc_probe, 905 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), 906 .flags = DM_FLAG_PRE_RELOC, 907 }; 908 #endif 909