1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <twl6030.h> 32 #include <twl6035.h> 33 #include <asm/io.h> 34 #include <asm/arch/mmc_host_def.h> 35 #include <asm/arch/sys_proto.h> 36 37 /* common definitions for all OMAPs */ 38 #define SYSCTL_SRC (1 << 25) 39 #define SYSCTL_SRD (1 << 26) 40 41 /* If we fail after 1 second wait, something is really bad */ 42 #define MAX_RETRY_MS 1000 43 44 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 45 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 46 unsigned int siz); 47 static struct mmc hsmmc_dev[2]; 48 49 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 50 static void omap4_vmmc_pbias_config(struct mmc *mmc) 51 { 52 u32 value = 0; 53 struct omap_sys_ctrl_regs *const ctrl = 54 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; 55 56 57 value = readl(&ctrl->control_pbiaslite); 58 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); 59 writel(value, &ctrl->control_pbiaslite); 60 /* set VMMC to 3V */ 61 twl6030_power_mmc_init(); 62 value = readl(&ctrl->control_pbiaslite); 63 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; 64 writel(value, &ctrl->control_pbiaslite); 65 } 66 #endif 67 68 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER) 69 static void omap5_pbias_config(struct mmc *mmc) 70 { 71 u32 value = 0; 72 struct omap_sys_ctrl_regs *const ctrl = 73 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; 74 75 value = readl(&ctrl->control_pbias); 76 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); 77 value |= SDCARD_BIAS_HIZ_MODE; 78 writel(value, &ctrl->control_pbias); 79 80 twl6035_mmc1_poweron_ldo(); 81 82 value = readl(&ctrl->control_pbias); 83 value &= ~SDCARD_BIAS_HIZ_MODE; 84 value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; 85 writel(value, &ctrl->control_pbias); 86 87 value = readl(&ctrl->control_pbias); 88 if (value & (1 << 23)) { 89 value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); 90 value |= SDCARD_BIAS_HIZ_MODE; 91 writel(value, &ctrl->control_pbias); 92 } 93 } 94 #endif 95 96 unsigned char mmc_board_init(struct mmc *mmc) 97 { 98 #if defined(CONFIG_OMAP34XX) 99 t2_t *t2_base = (t2_t *)T2_BASE; 100 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 101 u32 pbias_lite; 102 103 pbias_lite = readl(&t2_base->pbias_lite); 104 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 105 writel(pbias_lite, &t2_base->pbias_lite); 106 #endif 107 #if defined(CONFIG_TWL4030_POWER) 108 twl4030_power_mmc_init(); 109 mdelay(100); /* ramp-up delay from Linux code */ 110 #endif 111 #if defined(CONFIG_OMAP34XX) 112 writel(pbias_lite | PBIASLITEPWRDNZ1 | 113 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 114 &t2_base->pbias_lite); 115 116 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 117 &t2_base->devconf0); 118 119 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 120 &t2_base->devconf1); 121 122 /* Change from default of 52MHz to 26MHz if necessary */ 123 if (!(mmc->host_caps & MMC_MODE_HS_52MHz)) 124 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, 125 &t2_base->ctl_prog_io1); 126 127 writel(readl(&prcm_base->fclken1_core) | 128 EN_MMC1 | EN_MMC2 | EN_MMC3, 129 &prcm_base->fclken1_core); 130 131 writel(readl(&prcm_base->iclken1_core) | 132 EN_MMC1 | EN_MMC2 | EN_MMC3, 133 &prcm_base->iclken1_core); 134 #endif 135 136 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 137 /* PBIAS config needed for MMC1 only */ 138 if (mmc->block_dev.dev == 0) 139 omap4_vmmc_pbias_config(mmc); 140 #endif 141 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER) 142 if (mmc->block_dev.dev == 0) 143 omap5_pbias_config(mmc); 144 #endif 145 146 return 0; 147 } 148 149 void mmc_init_stream(struct hsmmc *mmc_base) 150 { 151 ulong start; 152 153 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 154 155 writel(MMC_CMD0, &mmc_base->cmd); 156 start = get_timer(0); 157 while (!(readl(&mmc_base->stat) & CC_MASK)) { 158 if (get_timer(0) - start > MAX_RETRY_MS) { 159 printf("%s: timedout waiting for cc!\n", __func__); 160 return; 161 } 162 } 163 writel(CC_MASK, &mmc_base->stat) 164 ; 165 writel(MMC_CMD0, &mmc_base->cmd) 166 ; 167 start = get_timer(0); 168 while (!(readl(&mmc_base->stat) & CC_MASK)) { 169 if (get_timer(0) - start > MAX_RETRY_MS) { 170 printf("%s: timedout waiting for cc2!\n", __func__); 171 return; 172 } 173 } 174 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 175 } 176 177 178 static int mmc_init_setup(struct mmc *mmc) 179 { 180 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 181 unsigned int reg_val; 182 unsigned int dsor; 183 ulong start; 184 185 mmc_board_init(mmc); 186 187 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 188 &mmc_base->sysconfig); 189 start = get_timer(0); 190 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 191 if (get_timer(0) - start > MAX_RETRY_MS) { 192 printf("%s: timedout waiting for cc2!\n", __func__); 193 return TIMEOUT; 194 } 195 } 196 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 197 start = get_timer(0); 198 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 199 if (get_timer(0) - start > MAX_RETRY_MS) { 200 printf("%s: timedout waiting for softresetall!\n", 201 __func__); 202 return TIMEOUT; 203 } 204 } 205 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 206 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 207 &mmc_base->capa); 208 209 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 210 211 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 212 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 213 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 214 215 dsor = 240; 216 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 217 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 218 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 219 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 220 start = get_timer(0); 221 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 222 if (get_timer(0) - start > MAX_RETRY_MS) { 223 printf("%s: timedout waiting for ics!\n", __func__); 224 return TIMEOUT; 225 } 226 } 227 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 228 229 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 230 231 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 232 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 233 &mmc_base->ie); 234 235 mmc_init_stream(mmc_base); 236 237 return 0; 238 } 239 240 /* 241 * MMC controller internal finite state machine reset 242 * 243 * Used to reset command or data internal state machines, using respectively 244 * SRC or SRD bit of SYSCTL register 245 */ 246 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 247 { 248 ulong start; 249 250 mmc_reg_out(&mmc_base->sysctl, bit, bit); 251 252 start = get_timer(0); 253 while ((readl(&mmc_base->sysctl) & bit) != 0) { 254 if (get_timer(0) - start > MAX_RETRY_MS) { 255 printf("%s: timedout waiting for sysctl %x to clear\n", 256 __func__, bit); 257 return; 258 } 259 } 260 } 261 262 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 263 struct mmc_data *data) 264 { 265 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 266 unsigned int flags, mmc_stat; 267 ulong start; 268 269 start = get_timer(0); 270 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 271 if (get_timer(0) - start > MAX_RETRY_MS) { 272 printf("%s: timedout waiting on cmd inhibit to clear\n", 273 __func__); 274 return TIMEOUT; 275 } 276 } 277 writel(0xFFFFFFFF, &mmc_base->stat); 278 start = get_timer(0); 279 while (readl(&mmc_base->stat)) { 280 if (get_timer(0) - start > MAX_RETRY_MS) { 281 printf("%s: timedout waiting for STAT (%x) to clear\n", 282 __func__, readl(&mmc_base->stat)); 283 return TIMEOUT; 284 } 285 } 286 /* 287 * CMDREG 288 * CMDIDX[13:8] : Command index 289 * DATAPRNT[5] : Data Present Select 290 * ENCMDIDX[4] : Command Index Check Enable 291 * ENCMDCRC[3] : Command CRC Check Enable 292 * RSPTYP[1:0] 293 * 00 = No Response 294 * 01 = Length 136 295 * 10 = Length 48 296 * 11 = Length 48 Check busy after response 297 */ 298 /* Delay added before checking the status of frq change 299 * retry not supported by mmc.c(core file) 300 */ 301 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 302 udelay(50000); /* wait 50 ms */ 303 304 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 305 flags = 0; 306 else if (cmd->resp_type & MMC_RSP_136) 307 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 308 else if (cmd->resp_type & MMC_RSP_BUSY) 309 flags = RSP_TYPE_LGHT48B; 310 else 311 flags = RSP_TYPE_LGHT48; 312 313 /* enable default flags */ 314 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 315 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 316 317 if (cmd->resp_type & MMC_RSP_CRC) 318 flags |= CCCE_CHECK; 319 if (cmd->resp_type & MMC_RSP_OPCODE) 320 flags |= CICE_CHECK; 321 322 if (data) { 323 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 324 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 325 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 326 data->blocksize = 512; 327 writel(data->blocksize | (data->blocks << 16), 328 &mmc_base->blk); 329 } else 330 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 331 332 if (data->flags & MMC_DATA_READ) 333 flags |= (DP_DATA | DDIR_READ); 334 else 335 flags |= (DP_DATA | DDIR_WRITE); 336 } 337 338 writel(cmd->cmdarg, &mmc_base->arg); 339 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 340 341 start = get_timer(0); 342 do { 343 mmc_stat = readl(&mmc_base->stat); 344 if (get_timer(0) - start > MAX_RETRY_MS) { 345 printf("%s : timeout: No status update\n", __func__); 346 return TIMEOUT; 347 } 348 } while (!mmc_stat); 349 350 if ((mmc_stat & IE_CTO) != 0) { 351 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 352 return TIMEOUT; 353 } else if ((mmc_stat & ERRI_MASK) != 0) 354 return -1; 355 356 if (mmc_stat & CC_MASK) { 357 writel(CC_MASK, &mmc_base->stat); 358 if (cmd->resp_type & MMC_RSP_PRESENT) { 359 if (cmd->resp_type & MMC_RSP_136) { 360 /* response type 2 */ 361 cmd->response[3] = readl(&mmc_base->rsp10); 362 cmd->response[2] = readl(&mmc_base->rsp32); 363 cmd->response[1] = readl(&mmc_base->rsp54); 364 cmd->response[0] = readl(&mmc_base->rsp76); 365 } else 366 /* response types 1, 1b, 3, 4, 5, 6 */ 367 cmd->response[0] = readl(&mmc_base->rsp10); 368 } 369 } 370 371 if (data && (data->flags & MMC_DATA_READ)) { 372 mmc_read_data(mmc_base, data->dest, 373 data->blocksize * data->blocks); 374 } else if (data && (data->flags & MMC_DATA_WRITE)) { 375 mmc_write_data(mmc_base, data->src, 376 data->blocksize * data->blocks); 377 } 378 return 0; 379 } 380 381 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 382 { 383 unsigned int *output_buf = (unsigned int *)buf; 384 unsigned int mmc_stat; 385 unsigned int count; 386 387 /* 388 * Start Polled Read 389 */ 390 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 391 count /= 4; 392 393 while (size) { 394 ulong start = get_timer(0); 395 do { 396 mmc_stat = readl(&mmc_base->stat); 397 if (get_timer(0) - start > MAX_RETRY_MS) { 398 printf("%s: timedout waiting for status!\n", 399 __func__); 400 return TIMEOUT; 401 } 402 } while (mmc_stat == 0); 403 404 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 405 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 406 407 if ((mmc_stat & ERRI_MASK) != 0) 408 return 1; 409 410 if (mmc_stat & BRR_MASK) { 411 unsigned int k; 412 413 writel(readl(&mmc_base->stat) | BRR_MASK, 414 &mmc_base->stat); 415 for (k = 0; k < count; k++) { 416 *output_buf = readl(&mmc_base->data); 417 output_buf++; 418 } 419 size -= (count*4); 420 } 421 422 if (mmc_stat & BWR_MASK) 423 writel(readl(&mmc_base->stat) | BWR_MASK, 424 &mmc_base->stat); 425 426 if (mmc_stat & TC_MASK) { 427 writel(readl(&mmc_base->stat) | TC_MASK, 428 &mmc_base->stat); 429 break; 430 } 431 } 432 return 0; 433 } 434 435 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 436 unsigned int size) 437 { 438 unsigned int *input_buf = (unsigned int *)buf; 439 unsigned int mmc_stat; 440 unsigned int count; 441 442 /* 443 * Start Polled Read 444 */ 445 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 446 count /= 4; 447 448 while (size) { 449 ulong start = get_timer(0); 450 do { 451 mmc_stat = readl(&mmc_base->stat); 452 if (get_timer(0) - start > MAX_RETRY_MS) { 453 printf("%s: timedout waiting for status!\n", 454 __func__); 455 return TIMEOUT; 456 } 457 } while (mmc_stat == 0); 458 459 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 460 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 461 462 if ((mmc_stat & ERRI_MASK) != 0) 463 return 1; 464 465 if (mmc_stat & BWR_MASK) { 466 unsigned int k; 467 468 writel(readl(&mmc_base->stat) | BWR_MASK, 469 &mmc_base->stat); 470 for (k = 0; k < count; k++) { 471 writel(*input_buf, &mmc_base->data); 472 input_buf++; 473 } 474 size -= (count*4); 475 } 476 477 if (mmc_stat & BRR_MASK) 478 writel(readl(&mmc_base->stat) | BRR_MASK, 479 &mmc_base->stat); 480 481 if (mmc_stat & TC_MASK) { 482 writel(readl(&mmc_base->stat) | TC_MASK, 483 &mmc_base->stat); 484 break; 485 } 486 } 487 return 0; 488 } 489 490 static void mmc_set_ios(struct mmc *mmc) 491 { 492 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; 493 unsigned int dsor = 0; 494 ulong start; 495 496 /* configue bus width */ 497 switch (mmc->bus_width) { 498 case 8: 499 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 500 &mmc_base->con); 501 break; 502 503 case 4: 504 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 505 &mmc_base->con); 506 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 507 &mmc_base->hctl); 508 break; 509 510 case 1: 511 default: 512 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 513 &mmc_base->con); 514 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 515 &mmc_base->hctl); 516 break; 517 } 518 519 /* configure clock with 96Mhz system clock. 520 */ 521 if (mmc->clock != 0) { 522 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 523 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 524 dsor++; 525 } 526 527 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 528 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 529 530 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 531 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 532 533 start = get_timer(0); 534 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 535 if (get_timer(0) - start > MAX_RETRY_MS) { 536 printf("%s: timedout waiting for ics!\n", __func__); 537 return; 538 } 539 } 540 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 541 } 542 543 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max) 544 { 545 struct mmc *mmc; 546 547 mmc = &hsmmc_dev[dev_index]; 548 549 sprintf(mmc->name, "OMAP SD/MMC"); 550 mmc->send_cmd = mmc_send_cmd; 551 mmc->set_ios = mmc_set_ios; 552 mmc->init = mmc_init_setup; 553 mmc->getcd = NULL; 554 555 switch (dev_index) { 556 case 0: 557 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE; 558 break; 559 #ifdef OMAP_HSMMC2_BASE 560 case 1: 561 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE; 562 break; 563 #endif 564 #ifdef OMAP_HSMMC3_BASE 565 case 2: 566 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE; 567 break; 568 #endif 569 default: 570 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE; 571 return 1; 572 } 573 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 574 mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | 575 MMC_MODE_HC) & ~host_caps_mask; 576 577 mmc->f_min = 400000; 578 579 if (f_max != 0) 580 mmc->f_max = f_max; 581 else { 582 if (mmc->host_caps & MMC_MODE_HS) { 583 if (mmc->host_caps & MMC_MODE_HS_52MHz) 584 mmc->f_max = 52000000; 585 else 586 mmc->f_max = 26000000; 587 } else 588 mmc->f_max = 20000000; 589 } 590 591 mmc->b_max = 0; 592 593 #if defined(CONFIG_OMAP34XX) 594 /* 595 * Silicon revs 2.1 and older do not support multiblock transfers. 596 */ 597 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 598 mmc->b_max = 1; 599 #endif 600 601 mmc_register(mmc); 602 603 return 0; 604 } 605