1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <malloc.h> 28 #include <memalign.h> 29 #include <mmc.h> 30 #include <part.h> 31 #include <i2c.h> 32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) 33 #include <palmas.h> 34 #endif 35 #include <asm/io.h> 36 #include <asm/arch/mmc_host_def.h> 37 #ifdef CONFIG_OMAP54XX 38 #include <asm/arch/mux_dra7xx.h> 39 #include <asm/arch/dra7xx_iodelay.h> 40 #endif 41 #if !defined(CONFIG_SOC_KEYSTONE) 42 #include <asm/gpio.h> 43 #include <asm/arch/sys_proto.h> 44 #endif 45 #ifdef CONFIG_MMC_OMAP36XX_PINS 46 #include <asm/arch/mux.h> 47 #endif 48 #include <dm.h> 49 #include <power/regulator.h> 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 /* simplify defines to OMAP_HSMMC_USE_GPIO */ 54 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ 55 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) 56 #define OMAP_HSMMC_USE_GPIO 57 #else 58 #undef OMAP_HSMMC_USE_GPIO 59 #endif 60 61 /* common definitions for all OMAPs */ 62 #define SYSCTL_SRC (1 << 25) 63 #define SYSCTL_SRD (1 << 26) 64 65 #ifdef CONFIG_IODELAY_RECALIBRATION 66 struct omap_hsmmc_pinctrl_state { 67 struct pad_conf_entry *padconf; 68 int npads; 69 struct iodelay_cfg_entry *iodelay; 70 int niodelays; 71 }; 72 #endif 73 74 struct omap_hsmmc_data { 75 struct hsmmc *base_addr; 76 #if !CONFIG_IS_ENABLED(DM_MMC) 77 struct mmc_config cfg; 78 #endif 79 uint bus_width; 80 uint clock; 81 ushort last_cmd; 82 #ifdef OMAP_HSMMC_USE_GPIO 83 #if CONFIG_IS_ENABLED(DM_MMC) 84 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 85 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 86 bool cd_inverted; 87 #else 88 int cd_gpio; 89 int wp_gpio; 90 #endif 91 #endif 92 #if CONFIG_IS_ENABLED(DM_MMC) 93 enum bus_mode mode; 94 #endif 95 u8 controller_flags; 96 #ifdef CONFIG_MMC_OMAP_HS_ADMA 97 struct omap_hsmmc_adma_desc *adma_desc_table; 98 uint desc_slot; 99 #endif 100 const char *hw_rev; 101 struct udevice *pbias_supply; 102 uint signal_voltage; 103 #ifdef CONFIG_IODELAY_RECALIBRATION 104 struct omap_hsmmc_pinctrl_state *default_pinctrl_state; 105 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state; 106 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state; 107 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state; 108 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state; 109 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state; 110 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state; 111 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state; 112 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state; 113 #endif 114 }; 115 116 struct omap_mmc_of_data { 117 u8 controller_flags; 118 }; 119 120 #ifdef CONFIG_MMC_OMAP_HS_ADMA 121 struct omap_hsmmc_adma_desc { 122 u8 attr; 123 u8 reserved; 124 u16 len; 125 u32 addr; 126 }; 127 128 #define ADMA_MAX_LEN 63488 129 130 /* Decriptor table defines */ 131 #define ADMA_DESC_ATTR_VALID BIT(0) 132 #define ADMA_DESC_ATTR_END BIT(1) 133 #define ADMA_DESC_ATTR_INT BIT(2) 134 #define ADMA_DESC_ATTR_ACT1 BIT(4) 135 #define ADMA_DESC_ATTR_ACT2 BIT(5) 136 137 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 138 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) 139 #endif 140 141 /* If we fail after 1 second wait, something is really bad */ 142 #define MAX_RETRY_MS 1000 143 #define MMC_TIMEOUT_MS 20 144 145 /* DMA transfers can take a long time if a lot a data is transferred. 146 * The timeout must take in account the amount of data. Let's assume 147 * that the time will never exceed 333 ms per MB (in other word we assume 148 * that the bandwidth is always above 3MB/s). 149 */ 150 #define DMA_TIMEOUT_PER_MB 333 151 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) 152 #define OMAP_HSMMC_NO_1_8_V BIT(1) 153 #define OMAP_HSMMC_USE_ADMA BIT(2) 154 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) 155 156 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 157 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 158 unsigned int siz); 159 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base); 160 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base); 161 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit); 162 163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) 164 { 165 #if CONFIG_IS_ENABLED(DM_MMC) 166 return dev_get_priv(mmc->dev); 167 #else 168 return (struct omap_hsmmc_data *)mmc->priv; 169 #endif 170 } 171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) 172 { 173 #if CONFIG_IS_ENABLED(DM_MMC) 174 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); 175 return &plat->cfg; 176 #else 177 return &((struct omap_hsmmc_data *)mmc->priv)->cfg; 178 #endif 179 } 180 181 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC) 182 static int omap_mmc_setup_gpio_in(int gpio, const char *label) 183 { 184 int ret; 185 186 #ifndef CONFIG_DM_GPIO 187 if (!gpio_is_valid(gpio)) 188 return -1; 189 #endif 190 ret = gpio_request(gpio, label); 191 if (ret) 192 return ret; 193 194 ret = gpio_direction_input(gpio); 195 if (ret) 196 return ret; 197 198 return gpio; 199 } 200 #endif 201 202 static unsigned char mmc_board_init(struct mmc *mmc) 203 { 204 #if defined(CONFIG_OMAP34XX) 205 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); 206 t2_t *t2_base = (t2_t *)T2_BASE; 207 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 208 u32 pbias_lite; 209 #ifdef CONFIG_MMC_OMAP36XX_PINS 210 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); 211 #endif 212 213 pbias_lite = readl(&t2_base->pbias_lite); 214 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 215 #ifdef CONFIG_TARGET_OMAP3_CAIRO 216 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ 217 pbias_lite &= ~PBIASLITEVMODE0; 218 #endif 219 #ifdef CONFIG_TARGET_OMAP3_LOGIC 220 /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */ 221 pbias_lite &= ~PBIASLITEVMODE1; 222 #endif 223 #ifdef CONFIG_MMC_OMAP36XX_PINS 224 if (get_cpu_family() == CPU_OMAP36XX) { 225 /* Disable extended drain IO before changing PBIAS */ 226 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; 227 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); 228 } 229 #endif 230 writel(pbias_lite, &t2_base->pbias_lite); 231 232 writel(pbias_lite | PBIASLITEPWRDNZ1 | 233 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 234 &t2_base->pbias_lite); 235 236 #ifdef CONFIG_MMC_OMAP36XX_PINS 237 if (get_cpu_family() == CPU_OMAP36XX) 238 /* Enable extended drain IO after changing PBIAS */ 239 writel(wkup_ctrl | 240 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, 241 OMAP34XX_CTRL_WKUP_CTRL); 242 #endif 243 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 244 &t2_base->devconf0); 245 246 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 247 &t2_base->devconf1); 248 249 /* Change from default of 52MHz to 26MHz if necessary */ 250 if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) 251 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, 252 &t2_base->ctl_prog_io1); 253 254 writel(readl(&prcm_base->fclken1_core) | 255 EN_MMC1 | EN_MMC2 | EN_MMC3, 256 &prcm_base->fclken1_core); 257 258 writel(readl(&prcm_base->iclken1_core) | 259 EN_MMC1 | EN_MMC2 | EN_MMC3, 260 &prcm_base->iclken1_core); 261 #endif 262 263 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\ 264 !CONFIG_IS_ENABLED(DM_REGULATOR) 265 /* PBIAS config needed for MMC1 only */ 266 if (mmc_get_blk_desc(mmc)->devnum == 0) 267 vmmc_pbias_config(LDO_VOLT_3V0); 268 #endif 269 270 return 0; 271 } 272 273 void mmc_init_stream(struct hsmmc *mmc_base) 274 { 275 ulong start; 276 277 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 278 279 writel(MMC_CMD0, &mmc_base->cmd); 280 start = get_timer(0); 281 while (!(readl(&mmc_base->stat) & CC_MASK)) { 282 if (get_timer(0) - start > MAX_RETRY_MS) { 283 printf("%s: timedout waiting for cc!\n", __func__); 284 return; 285 } 286 } 287 writel(CC_MASK, &mmc_base->stat) 288 ; 289 writel(MMC_CMD0, &mmc_base->cmd) 290 ; 291 start = get_timer(0); 292 while (!(readl(&mmc_base->stat) & CC_MASK)) { 293 if (get_timer(0) - start > MAX_RETRY_MS) { 294 printf("%s: timedout waiting for cc2!\n", __func__); 295 return; 296 } 297 } 298 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 299 } 300 301 #if CONFIG_IS_ENABLED(DM_MMC) 302 #ifdef CONFIG_IODELAY_RECALIBRATION 303 static void omap_hsmmc_io_recalibrate(struct mmc *mmc) 304 { 305 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 306 struct omap_hsmmc_pinctrl_state *pinctrl_state; 307 308 switch (priv->mode) { 309 case MMC_HS_200: 310 pinctrl_state = priv->hs200_1_8v_pinctrl_state; 311 break; 312 case UHS_SDR104: 313 pinctrl_state = priv->sdr104_pinctrl_state; 314 break; 315 case UHS_SDR50: 316 pinctrl_state = priv->sdr50_pinctrl_state; 317 break; 318 case UHS_DDR50: 319 pinctrl_state = priv->ddr50_pinctrl_state; 320 break; 321 case UHS_SDR25: 322 pinctrl_state = priv->sdr25_pinctrl_state; 323 break; 324 case UHS_SDR12: 325 pinctrl_state = priv->sdr12_pinctrl_state; 326 break; 327 case SD_HS: 328 case MMC_HS: 329 case MMC_HS_52: 330 pinctrl_state = priv->hs_pinctrl_state; 331 break; 332 case MMC_DDR_52: 333 pinctrl_state = priv->ddr_1_8v_pinctrl_state; 334 default: 335 pinctrl_state = priv->default_pinctrl_state; 336 break; 337 } 338 339 if (!pinctrl_state) 340 pinctrl_state = priv->default_pinctrl_state; 341 342 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) { 343 if (pinctrl_state->iodelay) 344 late_recalibrate_iodelay(pinctrl_state->padconf, 345 pinctrl_state->npads, 346 pinctrl_state->iodelay, 347 pinctrl_state->niodelays); 348 else 349 do_set_mux32((*ctrl)->control_padconf_core_base, 350 pinctrl_state->padconf, 351 pinctrl_state->npads); 352 } 353 } 354 #endif 355 static void omap_hsmmc_set_timing(struct mmc *mmc) 356 { 357 u32 val; 358 struct hsmmc *mmc_base; 359 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 360 361 mmc_base = priv->base_addr; 362 363 omap_hsmmc_stop_clock(mmc_base); 364 val = readl(&mmc_base->ac12); 365 val &= ~AC12_UHSMC_MASK; 366 priv->mode = mmc->selected_mode; 367 368 if (mmc_is_mode_ddr(priv->mode)) 369 writel(readl(&mmc_base->con) | DDR, &mmc_base->con); 370 else 371 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); 372 373 switch (priv->mode) { 374 case MMC_HS_200: 375 case UHS_SDR104: 376 val |= AC12_UHSMC_SDR104; 377 break; 378 case UHS_SDR50: 379 val |= AC12_UHSMC_SDR50; 380 break; 381 case MMC_DDR_52: 382 case UHS_DDR50: 383 val |= AC12_UHSMC_DDR50; 384 break; 385 case SD_HS: 386 case MMC_HS_52: 387 case UHS_SDR25: 388 val |= AC12_UHSMC_SDR25; 389 break; 390 case MMC_LEGACY: 391 case MMC_HS: 392 case SD_LEGACY: 393 case UHS_SDR12: 394 val |= AC12_UHSMC_SDR12; 395 break; 396 default: 397 val |= AC12_UHSMC_RES; 398 break; 399 } 400 writel(val, &mmc_base->ac12); 401 402 #ifdef CONFIG_IODELAY_RECALIBRATION 403 omap_hsmmc_io_recalibrate(mmc); 404 #endif 405 omap_hsmmc_start_clock(mmc_base); 406 } 407 408 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage) 409 { 410 struct hsmmc *mmc_base; 411 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 412 u32 hctl, ac12; 413 414 mmc_base = priv->base_addr; 415 416 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK; 417 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN; 418 419 switch (signal_voltage) { 420 case MMC_SIGNAL_VOLTAGE_330: 421 hctl |= SDVS_3V0; 422 break; 423 case MMC_SIGNAL_VOLTAGE_180: 424 hctl |= SDVS_1V8; 425 ac12 |= AC12_V1V8_SIGEN; 426 break; 427 } 428 429 writel(hctl, &mmc_base->hctl); 430 writel(ac12, &mmc_base->ac12); 431 } 432 433 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 434 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout) 435 { 436 int ret = -ETIMEDOUT; 437 u32 con; 438 bool dat0_high; 439 bool target_dat0_high = !!state; 440 struct omap_hsmmc_data *priv = dev_get_priv(dev); 441 struct hsmmc *mmc_base = priv->base_addr; 442 443 con = readl(&mmc_base->con); 444 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con); 445 446 timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */ 447 while (timeout--) { 448 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0); 449 if (dat0_high == target_dat0_high) { 450 ret = 0; 451 break; 452 } 453 udelay(10); 454 } 455 writel(con, &mmc_base->con); 456 457 return ret; 458 } 459 #endif 460 461 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) 462 #if CONFIG_IS_ENABLED(DM_REGULATOR) 463 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV) 464 { 465 int ret = 0; 466 int uV = mV * 1000; 467 468 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 469 470 if (!mmc->vqmmc_supply) 471 return 0; 472 473 /* Disable PBIAS */ 474 ret = regulator_set_enable(priv->pbias_supply, false); 475 if (ret && ret != -ENOSYS) 476 return ret; 477 478 /* Turn off IO voltage */ 479 ret = regulator_set_enable(mmc->vqmmc_supply, false); 480 if (ret && ret != -ENOSYS) 481 return ret; 482 /* Program a new IO voltage value */ 483 ret = regulator_set_value(mmc->vqmmc_supply, uV); 484 if (ret) 485 return ret; 486 /* Turn on IO voltage */ 487 ret = regulator_set_enable(mmc->vqmmc_supply, true); 488 if (ret && ret != -ENOSYS) 489 return ret; 490 491 /* Program PBIAS voltage*/ 492 ret = regulator_set_value(priv->pbias_supply, uV); 493 if (ret && ret != -ENOSYS) 494 return ret; 495 /* Enable PBIAS */ 496 ret = regulator_set_enable(priv->pbias_supply, true); 497 if (ret && ret != -ENOSYS) 498 return ret; 499 500 return 0; 501 } 502 #endif 503 504 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc) 505 { 506 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 507 struct hsmmc *mmc_base = priv->base_addr; 508 int mv = mmc_voltage_to_mv(mmc->signal_voltage); 509 u32 capa_mask; 510 __maybe_unused u8 palmas_ldo_volt; 511 u32 val; 512 513 if (mv < 0) 514 return -EINVAL; 515 516 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 517 /* Use 3.0V rather than 3.3V */ 518 mv = 3000; 519 capa_mask = VS30_3V0SUP; 520 palmas_ldo_volt = LDO_VOLT_3V0; 521 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 522 capa_mask = VS18_1V8SUP; 523 palmas_ldo_volt = LDO_VOLT_1V8; 524 } else { 525 return -EOPNOTSUPP; 526 } 527 528 val = readl(&mmc_base->capa); 529 if (!(val & capa_mask)) 530 return -EOPNOTSUPP; 531 532 priv->signal_voltage = mmc->signal_voltage; 533 534 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage); 535 536 #if CONFIG_IS_ENABLED(DM_REGULATOR) 537 return omap_hsmmc_set_io_regulator(mmc, mv); 538 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \ 539 defined(CONFIG_PALMAS_POWER) 540 if (mmc_get_blk_desc(mmc)->devnum == 0) 541 vmmc_pbias_config(palmas_ldo_volt); 542 return 0; 543 #else 544 return 0; 545 #endif 546 } 547 #endif 548 549 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc) 550 { 551 struct hsmmc *mmc_base; 552 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 553 u32 val; 554 555 mmc_base = priv->base_addr; 556 val = readl(&mmc_base->capa); 557 558 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 559 val |= (VS30_3V0SUP | VS18_1V8SUP); 560 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) { 561 val |= VS30_3V0SUP; 562 val &= ~VS18_1V8SUP; 563 } else { 564 val |= VS18_1V8SUP; 565 val &= ~VS30_3V0SUP; 566 } 567 568 writel(val, &mmc_base->capa); 569 570 return val; 571 } 572 573 #ifdef MMC_SUPPORTS_TUNING 574 static void omap_hsmmc_disable_tuning(struct mmc *mmc) 575 { 576 struct hsmmc *mmc_base; 577 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 578 u32 val; 579 580 mmc_base = priv->base_addr; 581 val = readl(&mmc_base->ac12); 582 val &= ~(AC12_SCLK_SEL); 583 writel(val, &mmc_base->ac12); 584 585 val = readl(&mmc_base->dll); 586 val &= ~(DLL_FORCE_VALUE | DLL_SWT); 587 writel(val, &mmc_base->dll); 588 } 589 590 static void omap_hsmmc_set_dll(struct mmc *mmc, int count) 591 { 592 int i; 593 struct hsmmc *mmc_base; 594 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 595 u32 val; 596 597 mmc_base = priv->base_addr; 598 val = readl(&mmc_base->dll); 599 val |= DLL_FORCE_VALUE; 600 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT); 601 val |= (count << DLL_FORCE_SR_C_SHIFT); 602 writel(val, &mmc_base->dll); 603 604 val |= DLL_CALIB; 605 writel(val, &mmc_base->dll); 606 for (i = 0; i < 1000; i++) { 607 if (readl(&mmc_base->dll) & DLL_CALIB) 608 break; 609 } 610 val &= ~DLL_CALIB; 611 writel(val, &mmc_base->dll); 612 } 613 614 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) 615 { 616 struct omap_hsmmc_data *priv = dev_get_priv(dev); 617 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 618 struct mmc *mmc = upriv->mmc; 619 struct hsmmc *mmc_base; 620 u32 val; 621 u8 cur_match, prev_match = 0; 622 int ret; 623 u32 phase_delay = 0; 624 u32 start_window = 0, max_window = 0; 625 u32 length = 0, max_len = 0; 626 627 mmc_base = priv->base_addr; 628 val = readl(&mmc_base->capa2); 629 630 /* clock tuning is not needed for upto 52MHz */ 631 if (!((mmc->selected_mode == MMC_HS_200) || 632 (mmc->selected_mode == UHS_SDR104) || 633 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) 634 return 0; 635 636 val = readl(&mmc_base->dll); 637 val |= DLL_SWT; 638 writel(val, &mmc_base->dll); 639 while (phase_delay <= MAX_PHASE_DELAY) { 640 omap_hsmmc_set_dll(mmc, phase_delay); 641 642 cur_match = !mmc_send_tuning(mmc, opcode, NULL); 643 644 if (cur_match) { 645 if (prev_match) { 646 length++; 647 } else { 648 start_window = phase_delay; 649 length = 1; 650 } 651 } 652 653 if (length > max_len) { 654 max_window = start_window; 655 max_len = length; 656 } 657 658 prev_match = cur_match; 659 phase_delay += 4; 660 } 661 662 if (!max_len) { 663 ret = -EIO; 664 goto tuning_error; 665 } 666 667 val = readl(&mmc_base->ac12); 668 if (!(val & AC12_SCLK_SEL)) { 669 ret = -EIO; 670 goto tuning_error; 671 } 672 673 phase_delay = max_window + 4 * ((3 * max_len) >> 2); 674 omap_hsmmc_set_dll(mmc, phase_delay); 675 676 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 677 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 678 679 return 0; 680 681 tuning_error: 682 683 omap_hsmmc_disable_tuning(mmc); 684 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 685 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 686 687 return ret; 688 } 689 #endif 690 691 static void omap_hsmmc_send_init_stream(struct udevice *dev) 692 { 693 struct omap_hsmmc_data *priv = dev_get_priv(dev); 694 struct hsmmc *mmc_base = priv->base_addr; 695 696 mmc_init_stream(mmc_base); 697 } 698 #endif 699 700 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) 701 { 702 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 703 struct hsmmc *mmc_base = priv->base_addr; 704 u32 irq_mask = INT_EN_MASK; 705 706 /* 707 * TODO: Errata i802 indicates only DCRC interrupts can occur during 708 * tuning procedure and DCRC should be disabled. But see occurences 709 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These 710 * interrupts occur along with BRR, so the data is actually in the 711 * buffer. It has to be debugged why these interrutps occur 712 */ 713 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx)) 714 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC); 715 716 writel(irq_mask, &mmc_base->ie); 717 } 718 719 static int omap_hsmmc_init_setup(struct mmc *mmc) 720 { 721 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 722 struct hsmmc *mmc_base; 723 unsigned int reg_val; 724 unsigned int dsor; 725 ulong start; 726 727 mmc_base = priv->base_addr; 728 mmc_board_init(mmc); 729 730 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 731 &mmc_base->sysconfig); 732 start = get_timer(0); 733 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 734 if (get_timer(0) - start > MAX_RETRY_MS) { 735 printf("%s: timedout waiting for cc2!\n", __func__); 736 return -ETIMEDOUT; 737 } 738 } 739 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 740 start = get_timer(0); 741 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 742 if (get_timer(0) - start > MAX_RETRY_MS) { 743 printf("%s: timedout waiting for softresetall!\n", 744 __func__); 745 return -ETIMEDOUT; 746 } 747 } 748 #ifdef CONFIG_MMC_OMAP_HS_ADMA 749 reg_val = readl(&mmc_base->hl_hwinfo); 750 if (reg_val & MADMA_EN) 751 priv->controller_flags |= OMAP_HSMMC_USE_ADMA; 752 #endif 753 754 #if CONFIG_IS_ENABLED(DM_MMC) 755 reg_val = omap_hsmmc_set_capabilities(mmc); 756 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS30_3V0SUP) ? 757 MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180); 758 #else 759 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 760 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 761 &mmc_base->capa); 762 #endif 763 764 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 765 766 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 767 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 768 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 769 770 dsor = 240; 771 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 772 (ICE_STOP | DTO_15THDTO)); 773 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 774 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 775 start = get_timer(0); 776 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 777 if (get_timer(0) - start > MAX_RETRY_MS) { 778 printf("%s: timedout waiting for ics!\n", __func__); 779 return -ETIMEDOUT; 780 } 781 } 782 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 783 784 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 785 786 mmc_enable_irq(mmc, NULL); 787 788 #if !CONFIG_IS_ENABLED(DM_MMC) 789 mmc_init_stream(mmc_base); 790 #endif 791 792 return 0; 793 } 794 795 /* 796 * MMC controller internal finite state machine reset 797 * 798 * Used to reset command or data internal state machines, using respectively 799 * SRC or SRD bit of SYSCTL register 800 */ 801 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 802 { 803 ulong start; 804 805 mmc_reg_out(&mmc_base->sysctl, bit, bit); 806 807 /* 808 * CMD(DAT) lines reset procedures are slightly different 809 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). 810 * According to OMAP3 TRM: 811 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it 812 * returns to 0x0. 813 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset 814 * procedure steps must be as follows: 815 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in 816 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). 817 * 2. Poll the SRC(SRD) bit until it is set to 0x1. 818 * 3. Wait until the SRC (SRD) bit returns to 0x0 819 * (reset procedure is completed). 820 */ 821 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 822 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) 823 if (!(readl(&mmc_base->sysctl) & bit)) { 824 start = get_timer(0); 825 while (!(readl(&mmc_base->sysctl) & bit)) { 826 if (get_timer(0) - start > MMC_TIMEOUT_MS) 827 return; 828 } 829 } 830 #endif 831 start = get_timer(0); 832 while ((readl(&mmc_base->sysctl) & bit) != 0) { 833 if (get_timer(0) - start > MAX_RETRY_MS) { 834 printf("%s: timedout waiting for sysctl %x to clear\n", 835 __func__, bit); 836 return; 837 } 838 } 839 } 840 841 #ifdef CONFIG_MMC_OMAP_HS_ADMA 842 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end) 843 { 844 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 845 struct omap_hsmmc_adma_desc *desc; 846 u8 attr; 847 848 desc = &priv->adma_desc_table[priv->desc_slot]; 849 850 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; 851 if (!end) 852 priv->desc_slot++; 853 else 854 attr |= ADMA_DESC_ATTR_END; 855 856 desc->len = len; 857 desc->addr = (u32)buf; 858 desc->reserved = 0; 859 desc->attr = attr; 860 } 861 862 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc, 863 struct mmc_data *data) 864 { 865 uint total_len = data->blocksize * data->blocks; 866 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN); 867 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 868 int i = desc_count; 869 char *buf; 870 871 priv->desc_slot = 0; 872 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *) 873 memalign(ARCH_DMA_MINALIGN, desc_count * 874 sizeof(struct omap_hsmmc_adma_desc)); 875 876 if (data->flags & MMC_DATA_READ) 877 buf = data->dest; 878 else 879 buf = (char *)data->src; 880 881 while (--i) { 882 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false); 883 buf += ADMA_MAX_LEN; 884 total_len -= ADMA_MAX_LEN; 885 } 886 887 omap_hsmmc_adma_desc(mmc, buf, total_len, true); 888 889 flush_dcache_range((long)priv->adma_desc_table, 890 (long)priv->adma_desc_table + 891 ROUND(desc_count * 892 sizeof(struct omap_hsmmc_adma_desc), 893 ARCH_DMA_MINALIGN)); 894 } 895 896 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data) 897 { 898 struct hsmmc *mmc_base; 899 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 900 u32 val; 901 char *buf; 902 903 mmc_base = priv->base_addr; 904 omap_hsmmc_prepare_adma_table(mmc, data); 905 906 if (data->flags & MMC_DATA_READ) 907 buf = data->dest; 908 else 909 buf = (char *)data->src; 910 911 val = readl(&mmc_base->hctl); 912 val |= DMA_SELECT; 913 writel(val, &mmc_base->hctl); 914 915 val = readl(&mmc_base->con); 916 val |= DMA_MASTER; 917 writel(val, &mmc_base->con); 918 919 writel((u32)priv->adma_desc_table, &mmc_base->admasal); 920 921 flush_dcache_range((u32)buf, 922 (u32)buf + 923 ROUND(data->blocksize * data->blocks, 924 ARCH_DMA_MINALIGN)); 925 } 926 927 static void omap_hsmmc_dma_cleanup(struct mmc *mmc) 928 { 929 struct hsmmc *mmc_base; 930 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 931 u32 val; 932 933 mmc_base = priv->base_addr; 934 935 val = readl(&mmc_base->con); 936 val &= ~DMA_MASTER; 937 writel(val, &mmc_base->con); 938 939 val = readl(&mmc_base->hctl); 940 val &= ~DMA_SELECT; 941 writel(val, &mmc_base->hctl); 942 943 kfree(priv->adma_desc_table); 944 } 945 #else 946 #define omap_hsmmc_adma_desc 947 #define omap_hsmmc_prepare_adma_table 948 #define omap_hsmmc_prepare_data 949 #define omap_hsmmc_dma_cleanup 950 #endif 951 952 #if !CONFIG_IS_ENABLED(DM_MMC) 953 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 954 struct mmc_data *data) 955 { 956 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 957 #else 958 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 959 struct mmc_data *data) 960 { 961 struct omap_hsmmc_data *priv = dev_get_priv(dev); 962 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 963 struct mmc *mmc = upriv->mmc; 964 #endif 965 struct hsmmc *mmc_base; 966 unsigned int flags, mmc_stat; 967 ulong start; 968 priv->last_cmd = cmd->cmdidx; 969 970 mmc_base = priv->base_addr; 971 972 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 973 return 0; 974 975 start = get_timer(0); 976 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 977 if (get_timer(0) - start > MAX_RETRY_MS) { 978 printf("%s: timedout waiting on cmd inhibit to clear\n", 979 __func__); 980 return -ETIMEDOUT; 981 } 982 } 983 writel(0xFFFFFFFF, &mmc_base->stat); 984 start = get_timer(0); 985 while (readl(&mmc_base->stat)) { 986 if (get_timer(0) - start > MAX_RETRY_MS) { 987 printf("%s: timedout waiting for STAT (%x) to clear\n", 988 __func__, readl(&mmc_base->stat)); 989 return -ETIMEDOUT; 990 } 991 } 992 /* 993 * CMDREG 994 * CMDIDX[13:8] : Command index 995 * DATAPRNT[5] : Data Present Select 996 * ENCMDIDX[4] : Command Index Check Enable 997 * ENCMDCRC[3] : Command CRC Check Enable 998 * RSPTYP[1:0] 999 * 00 = No Response 1000 * 01 = Length 136 1001 * 10 = Length 48 1002 * 11 = Length 48 Check busy after response 1003 */ 1004 /* Delay added before checking the status of frq change 1005 * retry not supported by mmc.c(core file) 1006 */ 1007 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 1008 udelay(50000); /* wait 50 ms */ 1009 1010 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 1011 flags = 0; 1012 else if (cmd->resp_type & MMC_RSP_136) 1013 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 1014 else if (cmd->resp_type & MMC_RSP_BUSY) 1015 flags = RSP_TYPE_LGHT48B; 1016 else 1017 flags = RSP_TYPE_LGHT48; 1018 1019 /* enable default flags */ 1020 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 1021 MSBS_SGLEBLK); 1022 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE); 1023 1024 if (cmd->resp_type & MMC_RSP_CRC) 1025 flags |= CCCE_CHECK; 1026 if (cmd->resp_type & MMC_RSP_OPCODE) 1027 flags |= CICE_CHECK; 1028 1029 if (data) { 1030 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 1031 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 1032 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE); 1033 data->blocksize = 512; 1034 writel(data->blocksize | (data->blocks << 16), 1035 &mmc_base->blk); 1036 } else 1037 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 1038 1039 if (data->flags & MMC_DATA_READ) 1040 flags |= (DP_DATA | DDIR_READ); 1041 else 1042 flags |= (DP_DATA | DDIR_WRITE); 1043 1044 #ifdef CONFIG_MMC_OMAP_HS_ADMA 1045 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && 1046 !mmc_is_tuning_cmd(cmd->cmdidx)) { 1047 omap_hsmmc_prepare_data(mmc, data); 1048 flags |= DE_ENABLE; 1049 } 1050 #endif 1051 } 1052 1053 mmc_enable_irq(mmc, cmd); 1054 1055 writel(cmd->cmdarg, &mmc_base->arg); 1056 udelay(20); /* To fix "No status update" error on eMMC */ 1057 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 1058 1059 start = get_timer(0); 1060 do { 1061 mmc_stat = readl(&mmc_base->stat); 1062 if (get_timer(start) > MAX_RETRY_MS) { 1063 printf("%s : timeout: No status update\n", __func__); 1064 return -ETIMEDOUT; 1065 } 1066 } while (!mmc_stat); 1067 1068 if ((mmc_stat & IE_CTO) != 0) { 1069 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 1070 return -ETIMEDOUT; 1071 } else if ((mmc_stat & ERRI_MASK) != 0) 1072 return -1; 1073 1074 if (mmc_stat & CC_MASK) { 1075 writel(CC_MASK, &mmc_base->stat); 1076 if (cmd->resp_type & MMC_RSP_PRESENT) { 1077 if (cmd->resp_type & MMC_RSP_136) { 1078 /* response type 2 */ 1079 cmd->response[3] = readl(&mmc_base->rsp10); 1080 cmd->response[2] = readl(&mmc_base->rsp32); 1081 cmd->response[1] = readl(&mmc_base->rsp54); 1082 cmd->response[0] = readl(&mmc_base->rsp76); 1083 } else 1084 /* response types 1, 1b, 3, 4, 5, 6 */ 1085 cmd->response[0] = readl(&mmc_base->rsp10); 1086 } 1087 } 1088 1089 #ifdef CONFIG_MMC_OMAP_HS_ADMA 1090 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data && 1091 !mmc_is_tuning_cmd(cmd->cmdidx)) { 1092 u32 sz_mb, timeout; 1093 1094 if (mmc_stat & IE_ADMAE) { 1095 omap_hsmmc_dma_cleanup(mmc); 1096 return -EIO; 1097 } 1098 1099 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20); 1100 timeout = sz_mb * DMA_TIMEOUT_PER_MB; 1101 if (timeout < MAX_RETRY_MS) 1102 timeout = MAX_RETRY_MS; 1103 1104 start = get_timer(0); 1105 do { 1106 mmc_stat = readl(&mmc_base->stat); 1107 if (mmc_stat & TC_MASK) { 1108 writel(readl(&mmc_base->stat) | TC_MASK, 1109 &mmc_base->stat); 1110 break; 1111 } 1112 if (get_timer(start) > timeout) { 1113 printf("%s : DMA timeout: No status update\n", 1114 __func__); 1115 return -ETIMEDOUT; 1116 } 1117 } while (1); 1118 1119 omap_hsmmc_dma_cleanup(mmc); 1120 return 0; 1121 } 1122 #endif 1123 1124 if (data && (data->flags & MMC_DATA_READ)) { 1125 mmc_read_data(mmc_base, data->dest, 1126 data->blocksize * data->blocks); 1127 } else if (data && (data->flags & MMC_DATA_WRITE)) { 1128 mmc_write_data(mmc_base, data->src, 1129 data->blocksize * data->blocks); 1130 } 1131 return 0; 1132 } 1133 1134 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 1135 { 1136 unsigned int *output_buf = (unsigned int *)buf; 1137 unsigned int mmc_stat; 1138 unsigned int count; 1139 1140 /* 1141 * Start Polled Read 1142 */ 1143 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 1144 count /= 4; 1145 1146 while (size) { 1147 ulong start = get_timer(0); 1148 do { 1149 mmc_stat = readl(&mmc_base->stat); 1150 if (get_timer(0) - start > MAX_RETRY_MS) { 1151 printf("%s: timedout waiting for status!\n", 1152 __func__); 1153 return -ETIMEDOUT; 1154 } 1155 } while (mmc_stat == 0); 1156 1157 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 1158 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 1159 1160 if ((mmc_stat & ERRI_MASK) != 0) 1161 return 1; 1162 1163 if (mmc_stat & BRR_MASK) { 1164 unsigned int k; 1165 1166 writel(readl(&mmc_base->stat) | BRR_MASK, 1167 &mmc_base->stat); 1168 for (k = 0; k < count; k++) { 1169 *output_buf = readl(&mmc_base->data); 1170 output_buf++; 1171 } 1172 size -= (count*4); 1173 } 1174 1175 if (mmc_stat & BWR_MASK) 1176 writel(readl(&mmc_base->stat) | BWR_MASK, 1177 &mmc_base->stat); 1178 1179 if (mmc_stat & TC_MASK) { 1180 writel(readl(&mmc_base->stat) | TC_MASK, 1181 &mmc_base->stat); 1182 break; 1183 } 1184 } 1185 return 0; 1186 } 1187 1188 #if CONFIG_IS_ENABLED(MMC_WRITE) 1189 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 1190 unsigned int size) 1191 { 1192 unsigned int *input_buf = (unsigned int *)buf; 1193 unsigned int mmc_stat; 1194 unsigned int count; 1195 1196 /* 1197 * Start Polled Write 1198 */ 1199 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 1200 count /= 4; 1201 1202 while (size) { 1203 ulong start = get_timer(0); 1204 do { 1205 mmc_stat = readl(&mmc_base->stat); 1206 if (get_timer(0) - start > MAX_RETRY_MS) { 1207 printf("%s: timedout waiting for status!\n", 1208 __func__); 1209 return -ETIMEDOUT; 1210 } 1211 } while (mmc_stat == 0); 1212 1213 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 1214 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 1215 1216 if ((mmc_stat & ERRI_MASK) != 0) 1217 return 1; 1218 1219 if (mmc_stat & BWR_MASK) { 1220 unsigned int k; 1221 1222 writel(readl(&mmc_base->stat) | BWR_MASK, 1223 &mmc_base->stat); 1224 for (k = 0; k < count; k++) { 1225 writel(*input_buf, &mmc_base->data); 1226 input_buf++; 1227 } 1228 size -= (count*4); 1229 } 1230 1231 if (mmc_stat & BRR_MASK) 1232 writel(readl(&mmc_base->stat) | BRR_MASK, 1233 &mmc_base->stat); 1234 1235 if (mmc_stat & TC_MASK) { 1236 writel(readl(&mmc_base->stat) | TC_MASK, 1237 &mmc_base->stat); 1238 break; 1239 } 1240 } 1241 return 0; 1242 } 1243 #else 1244 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 1245 unsigned int size) 1246 { 1247 return -ENOTSUPP; 1248 } 1249 #endif 1250 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base) 1251 { 1252 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl); 1253 } 1254 1255 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base) 1256 { 1257 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 1258 } 1259 1260 static void omap_hsmmc_set_clock(struct mmc *mmc) 1261 { 1262 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1263 struct hsmmc *mmc_base; 1264 unsigned int dsor = 0; 1265 ulong start; 1266 1267 mmc_base = priv->base_addr; 1268 omap_hsmmc_stop_clock(mmc_base); 1269 1270 /* TODO: Is setting DTO required here? */ 1271 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK), 1272 (ICE_STOP | DTO_15THDTO)); 1273 1274 if (mmc->clock != 0) { 1275 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock); 1276 if (dsor > CLKD_MAX) 1277 dsor = CLKD_MAX; 1278 } else { 1279 dsor = CLKD_MAX; 1280 } 1281 1282 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 1283 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 1284 1285 start = get_timer(0); 1286 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 1287 if (get_timer(0) - start > MAX_RETRY_MS) { 1288 printf("%s: timedout waiting for ics!\n", __func__); 1289 return; 1290 } 1291 } 1292 1293 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor; 1294 mmc->clock = priv->clock; 1295 omap_hsmmc_start_clock(mmc_base); 1296 } 1297 1298 static void omap_hsmmc_set_bus_width(struct mmc *mmc) 1299 { 1300 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1301 struct hsmmc *mmc_base; 1302 1303 mmc_base = priv->base_addr; 1304 /* configue bus width */ 1305 switch (mmc->bus_width) { 1306 case 8: 1307 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 1308 &mmc_base->con); 1309 break; 1310 1311 case 4: 1312 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 1313 &mmc_base->con); 1314 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 1315 &mmc_base->hctl); 1316 break; 1317 1318 case 1: 1319 default: 1320 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 1321 &mmc_base->con); 1322 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 1323 &mmc_base->hctl); 1324 break; 1325 } 1326 1327 priv->bus_width = mmc->bus_width; 1328 } 1329 1330 #if !CONFIG_IS_ENABLED(DM_MMC) 1331 static int omap_hsmmc_set_ios(struct mmc *mmc) 1332 { 1333 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1334 #else 1335 static int omap_hsmmc_set_ios(struct udevice *dev) 1336 { 1337 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1338 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1339 struct mmc *mmc = upriv->mmc; 1340 #endif 1341 struct hsmmc *mmc_base = priv->base_addr; 1342 int ret = 0; 1343 1344 if (priv->bus_width != mmc->bus_width) 1345 omap_hsmmc_set_bus_width(mmc); 1346 1347 if (priv->clock != mmc->clock) 1348 omap_hsmmc_set_clock(mmc); 1349 1350 if (mmc->clk_disable) 1351 omap_hsmmc_stop_clock(mmc_base); 1352 else 1353 omap_hsmmc_start_clock(mmc_base); 1354 1355 #if CONFIG_IS_ENABLED(DM_MMC) 1356 if (priv->mode != mmc->selected_mode) 1357 omap_hsmmc_set_timing(mmc); 1358 1359 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) 1360 if (priv->signal_voltage != mmc->signal_voltage) 1361 ret = omap_hsmmc_set_signal_voltage(mmc); 1362 #endif 1363 #endif 1364 return ret; 1365 } 1366 1367 #ifdef OMAP_HSMMC_USE_GPIO 1368 #if CONFIG_IS_ENABLED(DM_MMC) 1369 static int omap_hsmmc_getcd(struct udevice *dev) 1370 { 1371 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1372 int value = -1; 1373 #if CONFIG_IS_ENABLED(DM_GPIO) 1374 value = dm_gpio_get_value(&priv->cd_gpio); 1375 #endif 1376 /* if no CD return as 1 */ 1377 if (value < 0) 1378 return 1; 1379 1380 if (priv->cd_inverted) 1381 return !value; 1382 return value; 1383 } 1384 1385 static int omap_hsmmc_getwp(struct udevice *dev) 1386 { 1387 int value = 0; 1388 #if CONFIG_IS_ENABLED(DM_GPIO) 1389 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1390 value = dm_gpio_get_value(&priv->wp_gpio); 1391 #endif 1392 /* if no WP return as 0 */ 1393 if (value < 0) 1394 return 0; 1395 return value; 1396 } 1397 #else 1398 static int omap_hsmmc_getcd(struct mmc *mmc) 1399 { 1400 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1401 int cd_gpio; 1402 1403 /* if no CD return as 1 */ 1404 cd_gpio = priv->cd_gpio; 1405 if (cd_gpio < 0) 1406 return 1; 1407 1408 /* NOTE: assumes card detect signal is active-low */ 1409 return !gpio_get_value(cd_gpio); 1410 } 1411 1412 static int omap_hsmmc_getwp(struct mmc *mmc) 1413 { 1414 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1415 int wp_gpio; 1416 1417 /* if no WP return as 0 */ 1418 wp_gpio = priv->wp_gpio; 1419 if (wp_gpio < 0) 1420 return 0; 1421 1422 /* NOTE: assumes write protect signal is active-high */ 1423 return gpio_get_value(wp_gpio); 1424 } 1425 #endif 1426 #endif 1427 1428 #if CONFIG_IS_ENABLED(DM_MMC) 1429 static const struct dm_mmc_ops omap_hsmmc_ops = { 1430 .send_cmd = omap_hsmmc_send_cmd, 1431 .set_ios = omap_hsmmc_set_ios, 1432 #ifdef OMAP_HSMMC_USE_GPIO 1433 .get_cd = omap_hsmmc_getcd, 1434 .get_wp = omap_hsmmc_getwp, 1435 #endif 1436 #ifdef MMC_SUPPORTS_TUNING 1437 .execute_tuning = omap_hsmmc_execute_tuning, 1438 #endif 1439 .send_init_stream = omap_hsmmc_send_init_stream, 1440 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1441 .wait_dat0 = omap_hsmmc_wait_dat0, 1442 #endif 1443 }; 1444 #else 1445 static const struct mmc_ops omap_hsmmc_ops = { 1446 .send_cmd = omap_hsmmc_send_cmd, 1447 .set_ios = omap_hsmmc_set_ios, 1448 .init = omap_hsmmc_init_setup, 1449 #ifdef OMAP_HSMMC_USE_GPIO 1450 .getcd = omap_hsmmc_getcd, 1451 .getwp = omap_hsmmc_getwp, 1452 #endif 1453 }; 1454 #endif 1455 1456 #if !CONFIG_IS_ENABLED(DM_MMC) 1457 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 1458 int wp_gpio) 1459 { 1460 struct mmc *mmc; 1461 struct omap_hsmmc_data *priv; 1462 struct mmc_config *cfg; 1463 uint host_caps_val; 1464 1465 priv = calloc(1, sizeof(*priv)); 1466 if (priv == NULL) 1467 return -1; 1468 1469 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; 1470 1471 switch (dev_index) { 1472 case 0: 1473 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 1474 break; 1475 #ifdef OMAP_HSMMC2_BASE 1476 case 1: 1477 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; 1478 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 1479 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ 1480 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ 1481 defined(CONFIG_HSMMC2_8BIT) 1482 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ 1483 host_caps_val |= MMC_MODE_8BIT; 1484 #endif 1485 break; 1486 #endif 1487 #ifdef OMAP_HSMMC3_BASE 1488 case 2: 1489 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; 1490 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) 1491 /* Enable 8-bit interface for eMMC on DRA7XX */ 1492 host_caps_val |= MMC_MODE_8BIT; 1493 #endif 1494 break; 1495 #endif 1496 default: 1497 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 1498 return 1; 1499 } 1500 #ifdef OMAP_HSMMC_USE_GPIO 1501 /* on error gpio values are set to -1, which is what we want */ 1502 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); 1503 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); 1504 #endif 1505 1506 cfg = &priv->cfg; 1507 1508 cfg->name = "OMAP SD/MMC"; 1509 cfg->ops = &omap_hsmmc_ops; 1510 1511 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1512 cfg->host_caps = host_caps_val & ~host_caps_mask; 1513 1514 cfg->f_min = 400000; 1515 1516 if (f_max != 0) 1517 cfg->f_max = f_max; 1518 else { 1519 if (cfg->host_caps & MMC_MODE_HS) { 1520 if (cfg->host_caps & MMC_MODE_HS_52MHz) 1521 cfg->f_max = 52000000; 1522 else 1523 cfg->f_max = 26000000; 1524 } else 1525 cfg->f_max = 20000000; 1526 } 1527 1528 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1529 1530 #if defined(CONFIG_OMAP34XX) 1531 /* 1532 * Silicon revs 2.1 and older do not support multiblock transfers. 1533 */ 1534 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 1535 cfg->b_max = 1; 1536 #endif 1537 1538 mmc = mmc_create(cfg, priv); 1539 if (mmc == NULL) 1540 return -1; 1541 1542 return 0; 1543 } 1544 #else 1545 1546 #ifdef CONFIG_IODELAY_RECALIBRATION 1547 static struct pad_conf_entry * 1548 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count) 1549 { 1550 int index = 0; 1551 struct pad_conf_entry *padconf; 1552 1553 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count); 1554 if (!padconf) { 1555 debug("failed to allocate memory\n"); 1556 return 0; 1557 } 1558 1559 while (index < count) { 1560 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]); 1561 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]); 1562 index++; 1563 } 1564 1565 return padconf; 1566 } 1567 1568 static struct iodelay_cfg_entry * 1569 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count) 1570 { 1571 int index = 0; 1572 struct iodelay_cfg_entry *iodelay; 1573 1574 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count); 1575 if (!iodelay) { 1576 debug("failed to allocate memory\n"); 1577 return 0; 1578 } 1579 1580 while (index < count) { 1581 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]); 1582 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]); 1583 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]); 1584 index++; 1585 } 1586 1587 return iodelay; 1588 } 1589 1590 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle, 1591 const char *name, int *len) 1592 { 1593 const void *fdt = gd->fdt_blob; 1594 int offset; 1595 const fdt32_t *pinctrl; 1596 1597 offset = fdt_node_offset_by_phandle(fdt, phandle); 1598 if (offset < 0) { 1599 debug("failed to get pinctrl node %s.\n", 1600 fdt_strerror(offset)); 1601 return 0; 1602 } 1603 1604 pinctrl = fdt_getprop(fdt, offset, name, len); 1605 if (!pinctrl) { 1606 debug("failed to get property %s\n", name); 1607 return 0; 1608 } 1609 1610 return pinctrl; 1611 } 1612 1613 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc, 1614 char *prop_name) 1615 { 1616 const void *fdt = gd->fdt_blob; 1617 const __be32 *phandle; 1618 int node = dev_of_offset(mmc->dev); 1619 1620 phandle = fdt_getprop(fdt, node, prop_name, NULL); 1621 if (!phandle) { 1622 debug("failed to get property %s\n", prop_name); 1623 return 0; 1624 } 1625 1626 return fdt32_to_cpu(*phandle); 1627 } 1628 1629 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc, 1630 char *prop_name) 1631 { 1632 const void *fdt = gd->fdt_blob; 1633 const __be32 *phandle; 1634 int len; 1635 int count; 1636 int node = dev_of_offset(mmc->dev); 1637 1638 phandle = fdt_getprop(fdt, node, prop_name, &len); 1639 if (!phandle) { 1640 debug("failed to get property %s\n", prop_name); 1641 return 0; 1642 } 1643 1644 /* No manual mode iodelay values if count < 2 */ 1645 count = len / sizeof(*phandle); 1646 if (count < 2) 1647 return 0; 1648 1649 return fdt32_to_cpu(*(phandle + 1)); 1650 } 1651 1652 static struct pad_conf_entry * 1653 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads) 1654 { 1655 int len; 1656 int count; 1657 struct pad_conf_entry *padconf; 1658 u32 phandle; 1659 const fdt32_t *pinctrl; 1660 1661 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name); 1662 if (!phandle) 1663 return ERR_PTR(-EINVAL); 1664 1665 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins", 1666 &len); 1667 if (!pinctrl) 1668 return ERR_PTR(-EINVAL); 1669 1670 count = (len / sizeof(*pinctrl)) / 2; 1671 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count); 1672 if (!padconf) 1673 return ERR_PTR(-EINVAL); 1674 1675 *npads = count; 1676 1677 return padconf; 1678 } 1679 1680 static struct iodelay_cfg_entry * 1681 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay) 1682 { 1683 int len; 1684 int count; 1685 struct iodelay_cfg_entry *iodelay; 1686 u32 phandle; 1687 const fdt32_t *pinctrl; 1688 1689 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name); 1690 /* Not all modes have manual mode iodelay values. So its not fatal */ 1691 if (!phandle) 1692 return 0; 1693 1694 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array", 1695 &len); 1696 if (!pinctrl) 1697 return ERR_PTR(-EINVAL); 1698 1699 count = (len / sizeof(*pinctrl)) / 3; 1700 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count); 1701 if (!iodelay) 1702 return ERR_PTR(-EINVAL); 1703 1704 *niodelay = count; 1705 1706 return iodelay; 1707 } 1708 1709 static struct omap_hsmmc_pinctrl_state * 1710 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode) 1711 { 1712 int index; 1713 int npads = 0; 1714 int niodelays = 0; 1715 const void *fdt = gd->fdt_blob; 1716 int node = dev_of_offset(mmc->dev); 1717 char prop_name[11]; 1718 struct omap_hsmmc_pinctrl_state *pinctrl_state; 1719 1720 pinctrl_state = (struct omap_hsmmc_pinctrl_state *) 1721 malloc(sizeof(*pinctrl_state)); 1722 if (!pinctrl_state) { 1723 debug("failed to allocate memory\n"); 1724 return 0; 1725 } 1726 1727 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode); 1728 if (index < 0) { 1729 debug("fail to find %s mode %s\n", mode, fdt_strerror(index)); 1730 goto err_pinctrl_state; 1731 } 1732 1733 sprintf(prop_name, "pinctrl-%d", index); 1734 1735 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name, 1736 &npads); 1737 if (IS_ERR(pinctrl_state->padconf)) 1738 goto err_pinctrl_state; 1739 pinctrl_state->npads = npads; 1740 1741 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name, 1742 &niodelays); 1743 if (IS_ERR(pinctrl_state->iodelay)) 1744 goto err_padconf; 1745 pinctrl_state->niodelays = niodelays; 1746 1747 return pinctrl_state; 1748 1749 err_padconf: 1750 kfree(pinctrl_state->padconf); 1751 1752 err_pinctrl_state: 1753 kfree(pinctrl_state); 1754 return 0; 1755 } 1756 1757 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \ 1758 do { \ 1759 struct omap_hsmmc_pinctrl_state *s = NULL; \ 1760 char str[20]; \ 1761 if (!(cfg->host_caps & capmask)) \ 1762 break; \ 1763 \ 1764 if (priv->hw_rev) { \ 1765 sprintf(str, "%s-%s", #mode, priv->hw_rev); \ 1766 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \ 1767 } \ 1768 \ 1769 if (!s) \ 1770 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ 1771 \ 1772 if (!s && !optional) { \ 1773 debug("%s: no pinctrl for %s\n", \ 1774 mmc->dev->name, #mode); \ 1775 cfg->host_caps &= ~(capmask); \ 1776 } else { \ 1777 priv->mode##_pinctrl_state = s; \ 1778 } \ 1779 } while (0) 1780 1781 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) 1782 { 1783 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1784 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); 1785 struct omap_hsmmc_pinctrl_state *default_pinctrl; 1786 1787 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) 1788 return 0; 1789 1790 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default"); 1791 if (!default_pinctrl) { 1792 printf("no pinctrl state for default mode\n"); 1793 return -EINVAL; 1794 } 1795 1796 priv->default_pinctrl_state = default_pinctrl; 1797 1798 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false); 1799 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false); 1800 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false); 1801 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false); 1802 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false); 1803 1804 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false); 1805 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false); 1806 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true); 1807 1808 return 0; 1809 } 1810 #endif 1811 1812 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1813 #ifdef CONFIG_OMAP54XX 1814 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) 1815 { 1816 return NULL; 1817 } 1818 #endif 1819 1820 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) 1821 { 1822 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 1823 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev); 1824 1825 struct mmc_config *cfg = &plat->cfg; 1826 #ifdef CONFIG_OMAP54XX 1827 const struct mmc_platform_fixups *fixups; 1828 #endif 1829 const void *fdt = gd->fdt_blob; 1830 int node = dev_of_offset(dev); 1831 int ret; 1832 1833 plat->base_addr = map_physmem(devfdt_get_addr(dev), 1834 sizeof(struct hsmmc *), 1835 MAP_NOCACHE); 1836 1837 ret = mmc_of_parse(dev, cfg); 1838 if (ret < 0) 1839 return ret; 1840 1841 if (!cfg->f_max) 1842 cfg->f_max = 52000000; 1843 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 1844 cfg->f_min = 400000; 1845 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1846 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1847 if (fdtdec_get_bool(fdt, node, "ti,dual-volt")) 1848 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1849 if (fdtdec_get_bool(fdt, node, "no-1-8-v")) 1850 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V; 1851 if (of_data) 1852 plat->controller_flags |= of_data->controller_flags; 1853 1854 #ifdef CONFIG_OMAP54XX 1855 fixups = platform_fixups_mmc(devfdt_get_addr(dev)); 1856 if (fixups) { 1857 plat->hw_rev = fixups->hw_rev; 1858 cfg->host_caps &= ~fixups->unsupported_caps; 1859 cfg->f_max = fixups->max_freq; 1860 } 1861 #endif 1862 1863 #ifdef OMAP_HSMMC_USE_GPIO 1864 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); 1865 #endif 1866 1867 return 0; 1868 } 1869 #endif 1870 1871 #ifdef CONFIG_BLK 1872 1873 static int omap_hsmmc_bind(struct udevice *dev) 1874 { 1875 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 1876 plat->mmc = calloc(1, sizeof(struct mmc)); 1877 return mmc_bind(dev, plat->mmc, &plat->cfg); 1878 } 1879 #endif 1880 static int omap_hsmmc_probe(struct udevice *dev) 1881 { 1882 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 1883 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1884 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1885 struct mmc_config *cfg = &plat->cfg; 1886 struct mmc *mmc; 1887 #ifdef CONFIG_IODELAY_RECALIBRATION 1888 int ret; 1889 #endif 1890 1891 cfg->name = "OMAP SD/MMC"; 1892 priv->base_addr = plat->base_addr; 1893 priv->controller_flags = plat->controller_flags; 1894 priv->hw_rev = plat->hw_rev; 1895 #ifdef OMAP_HSMMC_USE_GPIO 1896 priv->cd_inverted = plat->cd_inverted; 1897 #endif 1898 1899 #ifdef CONFIG_BLK 1900 mmc = plat->mmc; 1901 #else 1902 mmc = mmc_create(cfg, priv); 1903 if (mmc == NULL) 1904 return -1; 1905 #endif 1906 #if CONFIG_IS_ENABLED(DM_REGULATOR) 1907 device_get_supply_regulator(dev, "pbias-supply", 1908 &priv->pbias_supply); 1909 #endif 1910 #if defined(OMAP_HSMMC_USE_GPIO) 1911 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO) 1912 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); 1913 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); 1914 #endif 1915 #endif 1916 1917 mmc->dev = dev; 1918 upriv->mmc = mmc; 1919 1920 #ifdef CONFIG_IODELAY_RECALIBRATION 1921 ret = omap_hsmmc_get_pinctrl_state(mmc); 1922 /* 1923 * disable high speed modes for the platforms that require IO delay 1924 * and for which we don't have this information 1925 */ 1926 if ((ret < 0) && 1927 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) { 1928 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY; 1929 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) | 1930 UHS_CAPS); 1931 } 1932 #endif 1933 1934 return omap_hsmmc_init_setup(mmc); 1935 } 1936 1937 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1938 1939 static const struct omap_mmc_of_data dra7_mmc_of_data = { 1940 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY, 1941 }; 1942 1943 static const struct udevice_id omap_hsmmc_ids[] = { 1944 { .compatible = "ti,omap3-hsmmc" }, 1945 { .compatible = "ti,omap4-hsmmc" }, 1946 { .compatible = "ti,am33xx-hsmmc" }, 1947 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data }, 1948 { } 1949 }; 1950 #endif 1951 1952 U_BOOT_DRIVER(omap_hsmmc) = { 1953 .name = "omap_hsmmc", 1954 .id = UCLASS_MMC, 1955 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1956 .of_match = omap_hsmmc_ids, 1957 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, 1958 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat), 1959 #endif 1960 #ifdef CONFIG_BLK 1961 .bind = omap_hsmmc_bind, 1962 #endif 1963 .ops = &omap_hsmmc_ops, 1964 .probe = omap_hsmmc_probe, 1965 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), 1966 .flags = DM_FLAG_PRE_RELOC, 1967 }; 1968 #endif 1969