1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <malloc.h> 28 #include <memalign.h> 29 #include <mmc.h> 30 #include <part.h> 31 #include <i2c.h> 32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) 33 #include <palmas.h> 34 #endif 35 #include <asm/io.h> 36 #include <asm/arch/mmc_host_def.h> 37 #ifdef CONFIG_OMAP54XX 38 #include <asm/arch/mux_dra7xx.h> 39 #include <asm/arch/dra7xx_iodelay.h> 40 #endif 41 #if !defined(CONFIG_SOC_KEYSTONE) 42 #include <asm/gpio.h> 43 #include <asm/arch/sys_proto.h> 44 #endif 45 #ifdef CONFIG_MMC_OMAP36XX_PINS 46 #include <asm/arch/mux.h> 47 #endif 48 #include <dm.h> 49 #include <power/regulator.h> 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 /* simplify defines to OMAP_HSMMC_USE_GPIO */ 54 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ 55 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) 56 #define OMAP_HSMMC_USE_GPIO 57 #else 58 #undef OMAP_HSMMC_USE_GPIO 59 #endif 60 61 /* common definitions for all OMAPs */ 62 #define SYSCTL_SRC (1 << 25) 63 #define SYSCTL_SRD (1 << 26) 64 65 #ifdef CONFIG_IODELAY_RECALIBRATION 66 struct omap_hsmmc_pinctrl_state { 67 struct pad_conf_entry *padconf; 68 int npads; 69 struct iodelay_cfg_entry *iodelay; 70 int niodelays; 71 }; 72 #endif 73 74 struct omap_hsmmc_data { 75 struct hsmmc *base_addr; 76 #if !CONFIG_IS_ENABLED(DM_MMC) 77 struct mmc_config cfg; 78 #endif 79 uint bus_width; 80 uint clock; 81 #ifdef OMAP_HSMMC_USE_GPIO 82 #if CONFIG_IS_ENABLED(DM_MMC) 83 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 84 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 85 bool cd_inverted; 86 #else 87 int cd_gpio; 88 int wp_gpio; 89 #endif 90 #endif 91 #if CONFIG_IS_ENABLED(DM_MMC) 92 uint iov; 93 enum bus_mode mode; 94 #endif 95 u8 controller_flags; 96 #ifndef CONFIG_OMAP34XX 97 struct omap_hsmmc_adma_desc *adma_desc_table; 98 uint desc_slot; 99 #endif 100 const char *hw_rev; 101 #ifdef CONFIG_IODELAY_RECALIBRATION 102 struct omap_hsmmc_pinctrl_state *default_pinctrl_state; 103 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state; 104 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state; 105 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state; 106 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state; 107 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state; 108 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state; 109 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state; 110 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state; 111 #endif 112 }; 113 114 struct omap_mmc_of_data { 115 u8 controller_flags; 116 }; 117 118 #ifndef CONFIG_OMAP34XX 119 struct omap_hsmmc_adma_desc { 120 u8 attr; 121 u8 reserved; 122 u16 len; 123 u32 addr; 124 }; 125 126 #define ADMA_MAX_LEN 63488 127 128 /* Decriptor table defines */ 129 #define ADMA_DESC_ATTR_VALID BIT(0) 130 #define ADMA_DESC_ATTR_END BIT(1) 131 #define ADMA_DESC_ATTR_INT BIT(2) 132 #define ADMA_DESC_ATTR_ACT1 BIT(4) 133 #define ADMA_DESC_ATTR_ACT2 BIT(5) 134 135 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 136 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) 137 #endif 138 139 /* If we fail after 1 second wait, something is really bad */ 140 #define MAX_RETRY_MS 1000 141 #define MMC_TIMEOUT_MS 20 142 143 /* DMA transfers can take a long time if a lot a data is transferred. 144 * The timeout must take in account the amount of data. Let's assume 145 * that the time will never exceed 333 ms per MB (in other word we assume 146 * that the bandwidth is always above 3MB/s). 147 */ 148 #define DMA_TIMEOUT_PER_MB 333 149 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) 150 #define OMAP_HSMMC_NO_1_8_V BIT(1) 151 #define OMAP_HSMMC_USE_ADMA BIT(2) 152 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) 153 154 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 155 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 156 unsigned int siz); 157 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base); 158 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base); 159 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit); 160 161 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) 162 { 163 #if CONFIG_IS_ENABLED(DM_MMC) 164 return dev_get_priv(mmc->dev); 165 #else 166 return (struct omap_hsmmc_data *)mmc->priv; 167 #endif 168 } 169 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) 170 { 171 #if CONFIG_IS_ENABLED(DM_MMC) 172 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); 173 return &plat->cfg; 174 #else 175 return &((struct omap_hsmmc_data *)mmc->priv)->cfg; 176 #endif 177 } 178 179 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC) 180 static int omap_mmc_setup_gpio_in(int gpio, const char *label) 181 { 182 int ret; 183 184 #ifndef CONFIG_DM_GPIO 185 if (!gpio_is_valid(gpio)) 186 return -1; 187 #endif 188 ret = gpio_request(gpio, label); 189 if (ret) 190 return ret; 191 192 ret = gpio_direction_input(gpio); 193 if (ret) 194 return ret; 195 196 return gpio; 197 } 198 #endif 199 200 static unsigned char mmc_board_init(struct mmc *mmc) 201 { 202 #if defined(CONFIG_OMAP34XX) 203 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); 204 t2_t *t2_base = (t2_t *)T2_BASE; 205 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 206 u32 pbias_lite; 207 #ifdef CONFIG_MMC_OMAP36XX_PINS 208 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); 209 #endif 210 211 pbias_lite = readl(&t2_base->pbias_lite); 212 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 213 #ifdef CONFIG_TARGET_OMAP3_CAIRO 214 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ 215 pbias_lite &= ~PBIASLITEVMODE0; 216 #endif 217 #ifdef CONFIG_MMC_OMAP36XX_PINS 218 if (get_cpu_family() == CPU_OMAP36XX) { 219 /* Disable extended drain IO before changing PBIAS */ 220 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; 221 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); 222 } 223 #endif 224 writel(pbias_lite, &t2_base->pbias_lite); 225 226 writel(pbias_lite | PBIASLITEPWRDNZ1 | 227 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 228 &t2_base->pbias_lite); 229 230 #ifdef CONFIG_MMC_OMAP36XX_PINS 231 if (get_cpu_family() == CPU_OMAP36XX) 232 /* Enable extended drain IO after changing PBIAS */ 233 writel(wkup_ctrl | 234 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, 235 OMAP34XX_CTRL_WKUP_CTRL); 236 #endif 237 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 238 &t2_base->devconf0); 239 240 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 241 &t2_base->devconf1); 242 243 /* Change from default of 52MHz to 26MHz if necessary */ 244 if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) 245 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, 246 &t2_base->ctl_prog_io1); 247 248 writel(readl(&prcm_base->fclken1_core) | 249 EN_MMC1 | EN_MMC2 | EN_MMC3, 250 &prcm_base->fclken1_core); 251 252 writel(readl(&prcm_base->iclken1_core) | 253 EN_MMC1 | EN_MMC2 | EN_MMC3, 254 &prcm_base->iclken1_core); 255 #endif 256 257 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) 258 /* PBIAS config needed for MMC1 only */ 259 if (mmc_get_blk_desc(mmc)->devnum == 0) 260 vmmc_pbias_config(LDO_VOLT_3V0); 261 #endif 262 263 return 0; 264 } 265 266 void mmc_init_stream(struct hsmmc *mmc_base) 267 { 268 ulong start; 269 270 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 271 272 writel(MMC_CMD0, &mmc_base->cmd); 273 start = get_timer(0); 274 while (!(readl(&mmc_base->stat) & CC_MASK)) { 275 if (get_timer(0) - start > MAX_RETRY_MS) { 276 printf("%s: timedout waiting for cc!\n", __func__); 277 return; 278 } 279 } 280 writel(CC_MASK, &mmc_base->stat) 281 ; 282 writel(MMC_CMD0, &mmc_base->cmd) 283 ; 284 start = get_timer(0); 285 while (!(readl(&mmc_base->stat) & CC_MASK)) { 286 if (get_timer(0) - start > MAX_RETRY_MS) { 287 printf("%s: timedout waiting for cc2!\n", __func__); 288 return; 289 } 290 } 291 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 292 } 293 294 #if CONFIG_IS_ENABLED(DM_MMC) 295 #ifdef CONFIG_IODELAY_RECALIBRATION 296 static void omap_hsmmc_io_recalibrate(struct mmc *mmc) 297 { 298 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 299 struct omap_hsmmc_pinctrl_state *pinctrl_state; 300 301 switch (priv->mode) { 302 case MMC_HS_200: 303 pinctrl_state = priv->hs200_1_8v_pinctrl_state; 304 break; 305 case UHS_SDR104: 306 pinctrl_state = priv->sdr104_pinctrl_state; 307 break; 308 case UHS_SDR50: 309 pinctrl_state = priv->sdr50_pinctrl_state; 310 break; 311 case UHS_DDR50: 312 pinctrl_state = priv->ddr50_pinctrl_state; 313 break; 314 case UHS_SDR25: 315 pinctrl_state = priv->sdr25_pinctrl_state; 316 break; 317 case UHS_SDR12: 318 pinctrl_state = priv->sdr12_pinctrl_state; 319 break; 320 case SD_HS: 321 case MMC_HS: 322 case MMC_HS_52: 323 pinctrl_state = priv->hs_pinctrl_state; 324 break; 325 case MMC_DDR_52: 326 pinctrl_state = priv->ddr_1_8v_pinctrl_state; 327 default: 328 pinctrl_state = priv->default_pinctrl_state; 329 break; 330 } 331 332 if (!pinctrl_state) 333 pinctrl_state = priv->default_pinctrl_state; 334 335 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) { 336 if (pinctrl_state->iodelay) 337 late_recalibrate_iodelay(pinctrl_state->padconf, 338 pinctrl_state->npads, 339 pinctrl_state->iodelay, 340 pinctrl_state->niodelays); 341 else 342 do_set_mux32((*ctrl)->control_padconf_core_base, 343 pinctrl_state->padconf, 344 pinctrl_state->npads); 345 } 346 } 347 #endif 348 static void omap_hsmmc_set_timing(struct mmc *mmc) 349 { 350 u32 val; 351 struct hsmmc *mmc_base; 352 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 353 354 mmc_base = priv->base_addr; 355 356 omap_hsmmc_stop_clock(mmc_base); 357 val = readl(&mmc_base->ac12); 358 val &= ~AC12_UHSMC_MASK; 359 priv->mode = mmc->selected_mode; 360 361 if (mmc_is_mode_ddr(priv->mode)) 362 writel(readl(&mmc_base->con) | DDR, &mmc_base->con); 363 else 364 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); 365 366 switch (priv->mode) { 367 case MMC_HS_200: 368 case UHS_SDR104: 369 val |= AC12_UHSMC_SDR104; 370 break; 371 case UHS_SDR50: 372 val |= AC12_UHSMC_SDR50; 373 break; 374 case MMC_DDR_52: 375 case UHS_DDR50: 376 val |= AC12_UHSMC_DDR50; 377 break; 378 case SD_HS: 379 case MMC_HS_52: 380 case UHS_SDR25: 381 val |= AC12_UHSMC_SDR25; 382 break; 383 case MMC_LEGACY: 384 case MMC_HS: 385 case SD_LEGACY: 386 case UHS_SDR12: 387 val |= AC12_UHSMC_SDR12; 388 break; 389 default: 390 val |= AC12_UHSMC_RES; 391 break; 392 } 393 writel(val, &mmc_base->ac12); 394 395 #ifdef CONFIG_IODELAY_RECALIBRATION 396 omap_hsmmc_io_recalibrate(mmc); 397 #endif 398 omap_hsmmc_start_clock(mmc_base); 399 } 400 401 static void omap_hsmmc_conf_bus_power(struct mmc *mmc) 402 { 403 struct hsmmc *mmc_base; 404 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 405 u32 val; 406 407 mmc_base = priv->base_addr; 408 409 val = readl(&mmc_base->hctl) & ~SDVS_MASK; 410 411 switch (priv->iov) { 412 case IOV_3V3: 413 val |= SDVS_3V3; 414 break; 415 case IOV_3V0: 416 val |= SDVS_3V0; 417 break; 418 case IOV_1V8: 419 val |= SDVS_1V8; 420 break; 421 } 422 423 writel(val, &mmc_base->hctl); 424 } 425 426 static void omap_hsmmc_set_capabilities(struct mmc *mmc) 427 { 428 struct hsmmc *mmc_base; 429 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 430 u32 val; 431 432 mmc_base = priv->base_addr; 433 val = readl(&mmc_base->capa); 434 435 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 436 val |= (VS30_3V0SUP | VS18_1V8SUP); 437 priv->iov = IOV_3V0; 438 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) { 439 val |= VS30_3V0SUP; 440 val &= ~VS18_1V8SUP; 441 priv->iov = IOV_3V0; 442 } else { 443 val |= VS18_1V8SUP; 444 val &= ~VS30_3V0SUP; 445 priv->iov = IOV_1V8; 446 } 447 448 writel(val, &mmc_base->capa); 449 } 450 451 #ifdef MMC_SUPPORTS_TUNING 452 static void omap_hsmmc_disable_tuning(struct mmc *mmc) 453 { 454 struct hsmmc *mmc_base; 455 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 456 u32 val; 457 458 mmc_base = priv->base_addr; 459 val = readl(&mmc_base->ac12); 460 val &= ~(AC12_SCLK_SEL); 461 writel(val, &mmc_base->ac12); 462 463 val = readl(&mmc_base->dll); 464 val &= ~(DLL_FORCE_VALUE | DLL_SWT); 465 writel(val, &mmc_base->dll); 466 } 467 468 static void omap_hsmmc_set_dll(struct mmc *mmc, int count) 469 { 470 int i; 471 struct hsmmc *mmc_base; 472 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 473 u32 val; 474 475 mmc_base = priv->base_addr; 476 val = readl(&mmc_base->dll); 477 val |= DLL_FORCE_VALUE; 478 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT); 479 val |= (count << DLL_FORCE_SR_C_SHIFT); 480 writel(val, &mmc_base->dll); 481 482 val |= DLL_CALIB; 483 writel(val, &mmc_base->dll); 484 for (i = 0; i < 1000; i++) { 485 if (readl(&mmc_base->dll) & DLL_CALIB) 486 break; 487 } 488 val &= ~DLL_CALIB; 489 writel(val, &mmc_base->dll); 490 } 491 492 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) 493 { 494 struct omap_hsmmc_data *priv = dev_get_priv(dev); 495 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 496 struct mmc *mmc = upriv->mmc; 497 struct hsmmc *mmc_base; 498 u32 val; 499 u8 cur_match, prev_match = 0; 500 int ret; 501 u32 phase_delay = 0; 502 u32 start_window = 0, max_window = 0; 503 u32 length = 0, max_len = 0; 504 505 mmc_base = priv->base_addr; 506 val = readl(&mmc_base->capa2); 507 508 /* clock tuning is not needed for upto 52MHz */ 509 if (!((mmc->selected_mode == MMC_HS_200) || 510 (mmc->selected_mode == UHS_SDR104) || 511 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) 512 return 0; 513 514 val = readl(&mmc_base->dll); 515 val |= DLL_SWT; 516 writel(val, &mmc_base->dll); 517 while (phase_delay <= MAX_PHASE_DELAY) { 518 omap_hsmmc_set_dll(mmc, phase_delay); 519 520 cur_match = !mmc_send_tuning(mmc, opcode, NULL); 521 522 if (cur_match) { 523 if (prev_match) { 524 length++; 525 } else { 526 start_window = phase_delay; 527 length = 1; 528 } 529 } 530 531 if (length > max_len) { 532 max_window = start_window; 533 max_len = length; 534 } 535 536 prev_match = cur_match; 537 phase_delay += 4; 538 } 539 540 if (!max_len) { 541 ret = -EIO; 542 goto tuning_error; 543 } 544 545 val = readl(&mmc_base->ac12); 546 if (!(val & AC12_SCLK_SEL)) { 547 ret = -EIO; 548 goto tuning_error; 549 } 550 551 phase_delay = max_window + 4 * ((3 * max_len) >> 2); 552 omap_hsmmc_set_dll(mmc, phase_delay); 553 554 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 555 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 556 557 return 0; 558 559 tuning_error: 560 561 omap_hsmmc_disable_tuning(mmc); 562 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 563 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 564 565 return ret; 566 } 567 #endif 568 569 static void omap_hsmmc_send_init_stream(struct udevice *dev) 570 { 571 struct omap_hsmmc_data *priv = dev_get_priv(dev); 572 struct hsmmc *mmc_base = priv->base_addr; 573 574 mmc_init_stream(mmc_base); 575 } 576 #endif 577 578 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) 579 { 580 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 581 struct hsmmc *mmc_base = priv->base_addr; 582 u32 irq_mask = INT_EN_MASK; 583 584 /* 585 * TODO: Errata i802 indicates only DCRC interrupts can occur during 586 * tuning procedure and DCRC should be disabled. But see occurences 587 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These 588 * interrupts occur along with BRR, so the data is actually in the 589 * buffer. It has to be debugged why these interrutps occur 590 */ 591 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx)) 592 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC); 593 594 writel(irq_mask, &mmc_base->ie); 595 } 596 597 static int omap_hsmmc_init_setup(struct mmc *mmc) 598 { 599 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 600 struct hsmmc *mmc_base; 601 unsigned int reg_val; 602 unsigned int dsor; 603 ulong start; 604 605 mmc_base = priv->base_addr; 606 mmc_board_init(mmc); 607 608 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 609 &mmc_base->sysconfig); 610 start = get_timer(0); 611 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 612 if (get_timer(0) - start > MAX_RETRY_MS) { 613 printf("%s: timedout waiting for cc2!\n", __func__); 614 return -ETIMEDOUT; 615 } 616 } 617 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 618 start = get_timer(0); 619 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 620 if (get_timer(0) - start > MAX_RETRY_MS) { 621 printf("%s: timedout waiting for softresetall!\n", 622 __func__); 623 return -ETIMEDOUT; 624 } 625 } 626 #ifndef CONFIG_OMAP34XX 627 reg_val = readl(&mmc_base->hl_hwinfo); 628 if (reg_val & MADMA_EN) 629 priv->controller_flags |= OMAP_HSMMC_USE_ADMA; 630 #endif 631 632 #if CONFIG_IS_ENABLED(DM_MMC) 633 omap_hsmmc_set_capabilities(mmc); 634 omap_hsmmc_conf_bus_power(mmc); 635 #else 636 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 637 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 638 &mmc_base->capa); 639 #endif 640 641 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 642 643 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 644 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 645 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 646 647 dsor = 240; 648 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 649 (ICE_STOP | DTO_15THDTO)); 650 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 651 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 652 start = get_timer(0); 653 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 654 if (get_timer(0) - start > MAX_RETRY_MS) { 655 printf("%s: timedout waiting for ics!\n", __func__); 656 return -ETIMEDOUT; 657 } 658 } 659 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 660 661 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 662 663 mmc_enable_irq(mmc, NULL); 664 665 #if !CONFIG_IS_ENABLED(DM_MMC) 666 mmc_init_stream(mmc_base); 667 #endif 668 669 return 0; 670 } 671 672 /* 673 * MMC controller internal finite state machine reset 674 * 675 * Used to reset command or data internal state machines, using respectively 676 * SRC or SRD bit of SYSCTL register 677 */ 678 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 679 { 680 ulong start; 681 682 mmc_reg_out(&mmc_base->sysctl, bit, bit); 683 684 /* 685 * CMD(DAT) lines reset procedures are slightly different 686 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). 687 * According to OMAP3 TRM: 688 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it 689 * returns to 0x0. 690 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset 691 * procedure steps must be as follows: 692 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in 693 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). 694 * 2. Poll the SRC(SRD) bit until it is set to 0x1. 695 * 3. Wait until the SRC (SRD) bit returns to 0x0 696 * (reset procedure is completed). 697 */ 698 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 699 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) 700 if (!(readl(&mmc_base->sysctl) & bit)) { 701 start = get_timer(0); 702 while (!(readl(&mmc_base->sysctl) & bit)) { 703 if (get_timer(0) - start > MMC_TIMEOUT_MS) 704 return; 705 } 706 } 707 #endif 708 start = get_timer(0); 709 while ((readl(&mmc_base->sysctl) & bit) != 0) { 710 if (get_timer(0) - start > MAX_RETRY_MS) { 711 printf("%s: timedout waiting for sysctl %x to clear\n", 712 __func__, bit); 713 return; 714 } 715 } 716 } 717 718 #ifndef CONFIG_OMAP34XX 719 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end) 720 { 721 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 722 struct omap_hsmmc_adma_desc *desc; 723 u8 attr; 724 725 desc = &priv->adma_desc_table[priv->desc_slot]; 726 727 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; 728 if (!end) 729 priv->desc_slot++; 730 else 731 attr |= ADMA_DESC_ATTR_END; 732 733 desc->len = len; 734 desc->addr = (u32)buf; 735 desc->reserved = 0; 736 desc->attr = attr; 737 } 738 739 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc, 740 struct mmc_data *data) 741 { 742 uint total_len = data->blocksize * data->blocks; 743 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN); 744 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 745 int i = desc_count; 746 char *buf; 747 748 priv->desc_slot = 0; 749 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *) 750 memalign(ARCH_DMA_MINALIGN, desc_count * 751 sizeof(struct omap_hsmmc_adma_desc)); 752 753 if (data->flags & MMC_DATA_READ) 754 buf = data->dest; 755 else 756 buf = (char *)data->src; 757 758 while (--i) { 759 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false); 760 buf += ADMA_MAX_LEN; 761 total_len -= ADMA_MAX_LEN; 762 } 763 764 omap_hsmmc_adma_desc(mmc, buf, total_len, true); 765 766 flush_dcache_range((long)priv->adma_desc_table, 767 (long)priv->adma_desc_table + 768 ROUND(desc_count * 769 sizeof(struct omap_hsmmc_adma_desc), 770 ARCH_DMA_MINALIGN)); 771 } 772 773 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data) 774 { 775 struct hsmmc *mmc_base; 776 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 777 u32 val; 778 char *buf; 779 780 mmc_base = priv->base_addr; 781 omap_hsmmc_prepare_adma_table(mmc, data); 782 783 if (data->flags & MMC_DATA_READ) 784 buf = data->dest; 785 else 786 buf = (char *)data->src; 787 788 val = readl(&mmc_base->hctl); 789 val |= DMA_SELECT; 790 writel(val, &mmc_base->hctl); 791 792 val = readl(&mmc_base->con); 793 val |= DMA_MASTER; 794 writel(val, &mmc_base->con); 795 796 writel((u32)priv->adma_desc_table, &mmc_base->admasal); 797 798 flush_dcache_range((u32)buf, 799 (u32)buf + 800 ROUND(data->blocksize * data->blocks, 801 ARCH_DMA_MINALIGN)); 802 } 803 804 static void omap_hsmmc_dma_cleanup(struct mmc *mmc) 805 { 806 struct hsmmc *mmc_base; 807 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 808 u32 val; 809 810 mmc_base = priv->base_addr; 811 812 val = readl(&mmc_base->con); 813 val &= ~DMA_MASTER; 814 writel(val, &mmc_base->con); 815 816 val = readl(&mmc_base->hctl); 817 val &= ~DMA_SELECT; 818 writel(val, &mmc_base->hctl); 819 820 kfree(priv->adma_desc_table); 821 } 822 #else 823 #define omap_hsmmc_adma_desc 824 #define omap_hsmmc_prepare_adma_table 825 #define omap_hsmmc_prepare_data 826 #define omap_hsmmc_dma_cleanup 827 #endif 828 829 #if !CONFIG_IS_ENABLED(DM_MMC) 830 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 831 struct mmc_data *data) 832 { 833 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 834 #else 835 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 836 struct mmc_data *data) 837 { 838 struct omap_hsmmc_data *priv = dev_get_priv(dev); 839 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 840 struct mmc *mmc = upriv->mmc; 841 #endif 842 struct hsmmc *mmc_base; 843 unsigned int flags, mmc_stat; 844 ulong start; 845 846 mmc_base = priv->base_addr; 847 848 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 849 return 0; 850 851 start = get_timer(0); 852 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 853 if (get_timer(0) - start > MAX_RETRY_MS) { 854 printf("%s: timedout waiting on cmd inhibit to clear\n", 855 __func__); 856 return -ETIMEDOUT; 857 } 858 } 859 writel(0xFFFFFFFF, &mmc_base->stat); 860 start = get_timer(0); 861 while (readl(&mmc_base->stat)) { 862 if (get_timer(0) - start > MAX_RETRY_MS) { 863 printf("%s: timedout waiting for STAT (%x) to clear\n", 864 __func__, readl(&mmc_base->stat)); 865 return -ETIMEDOUT; 866 } 867 } 868 /* 869 * CMDREG 870 * CMDIDX[13:8] : Command index 871 * DATAPRNT[5] : Data Present Select 872 * ENCMDIDX[4] : Command Index Check Enable 873 * ENCMDCRC[3] : Command CRC Check Enable 874 * RSPTYP[1:0] 875 * 00 = No Response 876 * 01 = Length 136 877 * 10 = Length 48 878 * 11 = Length 48 Check busy after response 879 */ 880 /* Delay added before checking the status of frq change 881 * retry not supported by mmc.c(core file) 882 */ 883 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 884 udelay(50000); /* wait 50 ms */ 885 886 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 887 flags = 0; 888 else if (cmd->resp_type & MMC_RSP_136) 889 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 890 else if (cmd->resp_type & MMC_RSP_BUSY) 891 flags = RSP_TYPE_LGHT48B; 892 else 893 flags = RSP_TYPE_LGHT48; 894 895 /* enable default flags */ 896 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 897 MSBS_SGLEBLK); 898 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE); 899 900 if (cmd->resp_type & MMC_RSP_CRC) 901 flags |= CCCE_CHECK; 902 if (cmd->resp_type & MMC_RSP_OPCODE) 903 flags |= CICE_CHECK; 904 905 if (data) { 906 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 907 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 908 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE); 909 data->blocksize = 512; 910 writel(data->blocksize | (data->blocks << 16), 911 &mmc_base->blk); 912 } else 913 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 914 915 if (data->flags & MMC_DATA_READ) 916 flags |= (DP_DATA | DDIR_READ); 917 else 918 flags |= (DP_DATA | DDIR_WRITE); 919 920 #ifndef CONFIG_OMAP34XX 921 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && 922 !mmc_is_tuning_cmd(cmd->cmdidx)) { 923 omap_hsmmc_prepare_data(mmc, data); 924 flags |= DE_ENABLE; 925 } 926 #endif 927 } 928 929 mmc_enable_irq(mmc, cmd); 930 931 writel(cmd->cmdarg, &mmc_base->arg); 932 udelay(20); /* To fix "No status update" error on eMMC */ 933 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 934 935 start = get_timer(0); 936 do { 937 mmc_stat = readl(&mmc_base->stat); 938 if (get_timer(start) > MAX_RETRY_MS) { 939 printf("%s : timeout: No status update\n", __func__); 940 return -ETIMEDOUT; 941 } 942 } while (!mmc_stat); 943 944 if ((mmc_stat & IE_CTO) != 0) { 945 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 946 return -ETIMEDOUT; 947 } else if ((mmc_stat & ERRI_MASK) != 0) 948 return -1; 949 950 if (mmc_stat & CC_MASK) { 951 writel(CC_MASK, &mmc_base->stat); 952 if (cmd->resp_type & MMC_RSP_PRESENT) { 953 if (cmd->resp_type & MMC_RSP_136) { 954 /* response type 2 */ 955 cmd->response[3] = readl(&mmc_base->rsp10); 956 cmd->response[2] = readl(&mmc_base->rsp32); 957 cmd->response[1] = readl(&mmc_base->rsp54); 958 cmd->response[0] = readl(&mmc_base->rsp76); 959 } else 960 /* response types 1, 1b, 3, 4, 5, 6 */ 961 cmd->response[0] = readl(&mmc_base->rsp10); 962 } 963 } 964 965 #ifndef CONFIG_OMAP34XX 966 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data && 967 !mmc_is_tuning_cmd(cmd->cmdidx)) { 968 u32 sz_mb, timeout; 969 970 if (mmc_stat & IE_ADMAE) { 971 omap_hsmmc_dma_cleanup(mmc); 972 return -EIO; 973 } 974 975 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20); 976 timeout = sz_mb * DMA_TIMEOUT_PER_MB; 977 if (timeout < MAX_RETRY_MS) 978 timeout = MAX_RETRY_MS; 979 980 start = get_timer(0); 981 do { 982 mmc_stat = readl(&mmc_base->stat); 983 if (mmc_stat & TC_MASK) { 984 writel(readl(&mmc_base->stat) | TC_MASK, 985 &mmc_base->stat); 986 break; 987 } 988 if (get_timer(start) > timeout) { 989 printf("%s : DMA timeout: No status update\n", 990 __func__); 991 return -ETIMEDOUT; 992 } 993 } while (1); 994 995 omap_hsmmc_dma_cleanup(mmc); 996 return 0; 997 } 998 #endif 999 1000 if (data && (data->flags & MMC_DATA_READ)) { 1001 mmc_read_data(mmc_base, data->dest, 1002 data->blocksize * data->blocks); 1003 } else if (data && (data->flags & MMC_DATA_WRITE)) { 1004 mmc_write_data(mmc_base, data->src, 1005 data->blocksize * data->blocks); 1006 } 1007 return 0; 1008 } 1009 1010 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 1011 { 1012 unsigned int *output_buf = (unsigned int *)buf; 1013 unsigned int mmc_stat; 1014 unsigned int count; 1015 1016 /* 1017 * Start Polled Read 1018 */ 1019 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 1020 count /= 4; 1021 1022 while (size) { 1023 ulong start = get_timer(0); 1024 do { 1025 mmc_stat = readl(&mmc_base->stat); 1026 if (get_timer(0) - start > MAX_RETRY_MS) { 1027 printf("%s: timedout waiting for status!\n", 1028 __func__); 1029 return -ETIMEDOUT; 1030 } 1031 } while (mmc_stat == 0); 1032 1033 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 1034 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 1035 1036 if ((mmc_stat & ERRI_MASK) != 0) 1037 return 1; 1038 1039 if (mmc_stat & BRR_MASK) { 1040 unsigned int k; 1041 1042 writel(readl(&mmc_base->stat) | BRR_MASK, 1043 &mmc_base->stat); 1044 for (k = 0; k < count; k++) { 1045 *output_buf = readl(&mmc_base->data); 1046 output_buf++; 1047 } 1048 size -= (count*4); 1049 } 1050 1051 if (mmc_stat & BWR_MASK) 1052 writel(readl(&mmc_base->stat) | BWR_MASK, 1053 &mmc_base->stat); 1054 1055 if (mmc_stat & TC_MASK) { 1056 writel(readl(&mmc_base->stat) | TC_MASK, 1057 &mmc_base->stat); 1058 break; 1059 } 1060 } 1061 return 0; 1062 } 1063 1064 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 1065 unsigned int size) 1066 { 1067 unsigned int *input_buf = (unsigned int *)buf; 1068 unsigned int mmc_stat; 1069 unsigned int count; 1070 1071 /* 1072 * Start Polled Write 1073 */ 1074 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 1075 count /= 4; 1076 1077 while (size) { 1078 ulong start = get_timer(0); 1079 do { 1080 mmc_stat = readl(&mmc_base->stat); 1081 if (get_timer(0) - start > MAX_RETRY_MS) { 1082 printf("%s: timedout waiting for status!\n", 1083 __func__); 1084 return -ETIMEDOUT; 1085 } 1086 } while (mmc_stat == 0); 1087 1088 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 1089 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 1090 1091 if ((mmc_stat & ERRI_MASK) != 0) 1092 return 1; 1093 1094 if (mmc_stat & BWR_MASK) { 1095 unsigned int k; 1096 1097 writel(readl(&mmc_base->stat) | BWR_MASK, 1098 &mmc_base->stat); 1099 for (k = 0; k < count; k++) { 1100 writel(*input_buf, &mmc_base->data); 1101 input_buf++; 1102 } 1103 size -= (count*4); 1104 } 1105 1106 if (mmc_stat & BRR_MASK) 1107 writel(readl(&mmc_base->stat) | BRR_MASK, 1108 &mmc_base->stat); 1109 1110 if (mmc_stat & TC_MASK) { 1111 writel(readl(&mmc_base->stat) | TC_MASK, 1112 &mmc_base->stat); 1113 break; 1114 } 1115 } 1116 return 0; 1117 } 1118 1119 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base) 1120 { 1121 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl); 1122 } 1123 1124 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base) 1125 { 1126 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 1127 } 1128 1129 static void omap_hsmmc_set_clock(struct mmc *mmc) 1130 { 1131 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1132 struct hsmmc *mmc_base; 1133 unsigned int dsor = 0; 1134 ulong start; 1135 1136 mmc_base = priv->base_addr; 1137 omap_hsmmc_stop_clock(mmc_base); 1138 1139 /* TODO: Is setting DTO required here? */ 1140 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK), 1141 (ICE_STOP | DTO_15THDTO)); 1142 1143 if (mmc->clock != 0) { 1144 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock); 1145 if (dsor > CLKD_MAX) 1146 dsor = CLKD_MAX; 1147 } else { 1148 dsor = CLKD_MAX; 1149 } 1150 1151 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 1152 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 1153 1154 start = get_timer(0); 1155 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 1156 if (get_timer(0) - start > MAX_RETRY_MS) { 1157 printf("%s: timedout waiting for ics!\n", __func__); 1158 return; 1159 } 1160 } 1161 1162 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor; 1163 mmc->clock = priv->clock; 1164 omap_hsmmc_start_clock(mmc_base); 1165 } 1166 1167 static void omap_hsmmc_set_bus_width(struct mmc *mmc) 1168 { 1169 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1170 struct hsmmc *mmc_base; 1171 1172 mmc_base = priv->base_addr; 1173 /* configue bus width */ 1174 switch (mmc->bus_width) { 1175 case 8: 1176 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 1177 &mmc_base->con); 1178 break; 1179 1180 case 4: 1181 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 1182 &mmc_base->con); 1183 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 1184 &mmc_base->hctl); 1185 break; 1186 1187 case 1: 1188 default: 1189 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 1190 &mmc_base->con); 1191 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 1192 &mmc_base->hctl); 1193 break; 1194 } 1195 1196 priv->bus_width = mmc->bus_width; 1197 } 1198 1199 #if !CONFIG_IS_ENABLED(DM_MMC) 1200 static int omap_hsmmc_set_ios(struct mmc *mmc) 1201 { 1202 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1203 #else 1204 static int omap_hsmmc_set_ios(struct udevice *dev) 1205 { 1206 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1207 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1208 struct mmc *mmc = upriv->mmc; 1209 #endif 1210 struct hsmmc *mmc_base = priv->base_addr; 1211 1212 if (priv->bus_width != mmc->bus_width) 1213 omap_hsmmc_set_bus_width(mmc); 1214 1215 if (priv->clock != mmc->clock) 1216 omap_hsmmc_set_clock(mmc); 1217 1218 if (mmc->clk_disable) 1219 omap_hsmmc_stop_clock(mmc_base); 1220 else 1221 omap_hsmmc_start_clock(mmc_base); 1222 1223 #if CONFIG_IS_ENABLED(DM_MMC) 1224 if (priv->mode != mmc->selected_mode) 1225 omap_hsmmc_set_timing(mmc); 1226 #endif 1227 return 0; 1228 } 1229 1230 #ifdef OMAP_HSMMC_USE_GPIO 1231 #if CONFIG_IS_ENABLED(DM_MMC) 1232 static int omap_hsmmc_getcd(struct udevice *dev) 1233 { 1234 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1235 int value; 1236 1237 value = dm_gpio_get_value(&priv->cd_gpio); 1238 /* if no CD return as 1 */ 1239 if (value < 0) 1240 return 1; 1241 1242 if (priv->cd_inverted) 1243 return !value; 1244 return value; 1245 } 1246 1247 static int omap_hsmmc_getwp(struct udevice *dev) 1248 { 1249 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1250 int value; 1251 1252 value = dm_gpio_get_value(&priv->wp_gpio); 1253 /* if no WP return as 0 */ 1254 if (value < 0) 1255 return 0; 1256 return value; 1257 } 1258 #else 1259 static int omap_hsmmc_getcd(struct mmc *mmc) 1260 { 1261 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1262 int cd_gpio; 1263 1264 /* if no CD return as 1 */ 1265 cd_gpio = priv->cd_gpio; 1266 if (cd_gpio < 0) 1267 return 1; 1268 1269 /* NOTE: assumes card detect signal is active-low */ 1270 return !gpio_get_value(cd_gpio); 1271 } 1272 1273 static int omap_hsmmc_getwp(struct mmc *mmc) 1274 { 1275 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1276 int wp_gpio; 1277 1278 /* if no WP return as 0 */ 1279 wp_gpio = priv->wp_gpio; 1280 if (wp_gpio < 0) 1281 return 0; 1282 1283 /* NOTE: assumes write protect signal is active-high */ 1284 return gpio_get_value(wp_gpio); 1285 } 1286 #endif 1287 #endif 1288 1289 #if CONFIG_IS_ENABLED(DM_MMC) 1290 static const struct dm_mmc_ops omap_hsmmc_ops = { 1291 .send_cmd = omap_hsmmc_send_cmd, 1292 .set_ios = omap_hsmmc_set_ios, 1293 #ifdef OMAP_HSMMC_USE_GPIO 1294 .get_cd = omap_hsmmc_getcd, 1295 .get_wp = omap_hsmmc_getwp, 1296 #endif 1297 #ifdef MMC_SUPPORTS_TUNING 1298 .execute_tuning = omap_hsmmc_execute_tuning, 1299 #endif 1300 .send_init_stream = omap_hsmmc_send_init_stream, 1301 }; 1302 #else 1303 static const struct mmc_ops omap_hsmmc_ops = { 1304 .send_cmd = omap_hsmmc_send_cmd, 1305 .set_ios = omap_hsmmc_set_ios, 1306 .init = omap_hsmmc_init_setup, 1307 #ifdef OMAP_HSMMC_USE_GPIO 1308 .getcd = omap_hsmmc_getcd, 1309 .getwp = omap_hsmmc_getwp, 1310 #endif 1311 }; 1312 #endif 1313 1314 #if !CONFIG_IS_ENABLED(DM_MMC) 1315 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 1316 int wp_gpio) 1317 { 1318 struct mmc *mmc; 1319 struct omap_hsmmc_data *priv; 1320 struct mmc_config *cfg; 1321 uint host_caps_val; 1322 1323 priv = malloc(sizeof(*priv)); 1324 if (priv == NULL) 1325 return -1; 1326 1327 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; 1328 1329 switch (dev_index) { 1330 case 0: 1331 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 1332 break; 1333 #ifdef OMAP_HSMMC2_BASE 1334 case 1: 1335 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; 1336 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 1337 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ 1338 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ 1339 defined(CONFIG_HSMMC2_8BIT) 1340 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ 1341 host_caps_val |= MMC_MODE_8BIT; 1342 #endif 1343 break; 1344 #endif 1345 #ifdef OMAP_HSMMC3_BASE 1346 case 2: 1347 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; 1348 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) 1349 /* Enable 8-bit interface for eMMC on DRA7XX */ 1350 host_caps_val |= MMC_MODE_8BIT; 1351 #endif 1352 break; 1353 #endif 1354 default: 1355 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 1356 return 1; 1357 } 1358 #ifdef OMAP_HSMMC_USE_GPIO 1359 /* on error gpio values are set to -1, which is what we want */ 1360 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); 1361 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); 1362 #endif 1363 1364 cfg = &priv->cfg; 1365 1366 cfg->name = "OMAP SD/MMC"; 1367 cfg->ops = &omap_hsmmc_ops; 1368 1369 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1370 cfg->host_caps = host_caps_val & ~host_caps_mask; 1371 1372 cfg->f_min = 400000; 1373 1374 if (f_max != 0) 1375 cfg->f_max = f_max; 1376 else { 1377 if (cfg->host_caps & MMC_MODE_HS) { 1378 if (cfg->host_caps & MMC_MODE_HS_52MHz) 1379 cfg->f_max = 52000000; 1380 else 1381 cfg->f_max = 26000000; 1382 } else 1383 cfg->f_max = 20000000; 1384 } 1385 1386 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1387 1388 #if defined(CONFIG_OMAP34XX) 1389 /* 1390 * Silicon revs 2.1 and older do not support multiblock transfers. 1391 */ 1392 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 1393 cfg->b_max = 1; 1394 #endif 1395 1396 mmc = mmc_create(cfg, priv); 1397 if (mmc == NULL) 1398 return -1; 1399 1400 return 0; 1401 } 1402 #else 1403 1404 #ifdef CONFIG_IODELAY_RECALIBRATION 1405 static struct pad_conf_entry * 1406 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count) 1407 { 1408 int index = 0; 1409 struct pad_conf_entry *padconf; 1410 1411 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count); 1412 if (!padconf) { 1413 debug("failed to allocate memory\n"); 1414 return 0; 1415 } 1416 1417 while (index < count) { 1418 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]); 1419 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]); 1420 index++; 1421 } 1422 1423 return padconf; 1424 } 1425 1426 static struct iodelay_cfg_entry * 1427 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count) 1428 { 1429 int index = 0; 1430 struct iodelay_cfg_entry *iodelay; 1431 1432 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count); 1433 if (!iodelay) { 1434 debug("failed to allocate memory\n"); 1435 return 0; 1436 } 1437 1438 while (index < count) { 1439 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]); 1440 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]); 1441 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]); 1442 index++; 1443 } 1444 1445 return iodelay; 1446 } 1447 1448 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle, 1449 const char *name, int *len) 1450 { 1451 const void *fdt = gd->fdt_blob; 1452 int offset; 1453 const fdt32_t *pinctrl; 1454 1455 offset = fdt_node_offset_by_phandle(fdt, phandle); 1456 if (offset < 0) { 1457 debug("failed to get pinctrl node %s.\n", 1458 fdt_strerror(offset)); 1459 return 0; 1460 } 1461 1462 pinctrl = fdt_getprop(fdt, offset, name, len); 1463 if (!pinctrl) { 1464 debug("failed to get property %s\n", name); 1465 return 0; 1466 } 1467 1468 return pinctrl; 1469 } 1470 1471 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc, 1472 char *prop_name) 1473 { 1474 const void *fdt = gd->fdt_blob; 1475 const __be32 *phandle; 1476 int node = dev_of_offset(mmc->dev); 1477 1478 phandle = fdt_getprop(fdt, node, prop_name, NULL); 1479 if (!phandle) { 1480 debug("failed to get property %s\n", prop_name); 1481 return 0; 1482 } 1483 1484 return fdt32_to_cpu(*phandle); 1485 } 1486 1487 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc, 1488 char *prop_name) 1489 { 1490 const void *fdt = gd->fdt_blob; 1491 const __be32 *phandle; 1492 int len; 1493 int count; 1494 int node = dev_of_offset(mmc->dev); 1495 1496 phandle = fdt_getprop(fdt, node, prop_name, &len); 1497 if (!phandle) { 1498 debug("failed to get property %s\n", prop_name); 1499 return 0; 1500 } 1501 1502 /* No manual mode iodelay values if count < 2 */ 1503 count = len / sizeof(*phandle); 1504 if (count < 2) 1505 return 0; 1506 1507 return fdt32_to_cpu(*(phandle + 1)); 1508 } 1509 1510 static struct pad_conf_entry * 1511 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads) 1512 { 1513 int len; 1514 int count; 1515 struct pad_conf_entry *padconf; 1516 u32 phandle; 1517 const fdt32_t *pinctrl; 1518 1519 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name); 1520 if (!phandle) 1521 return ERR_PTR(-EINVAL); 1522 1523 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins", 1524 &len); 1525 if (!pinctrl) 1526 return ERR_PTR(-EINVAL); 1527 1528 count = (len / sizeof(*pinctrl)) / 2; 1529 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count); 1530 if (!padconf) 1531 return ERR_PTR(-EINVAL); 1532 1533 *npads = count; 1534 1535 return padconf; 1536 } 1537 1538 static struct iodelay_cfg_entry * 1539 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay) 1540 { 1541 int len; 1542 int count; 1543 struct iodelay_cfg_entry *iodelay; 1544 u32 phandle; 1545 const fdt32_t *pinctrl; 1546 1547 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name); 1548 /* Not all modes have manual mode iodelay values. So its not fatal */ 1549 if (!phandle) 1550 return 0; 1551 1552 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array", 1553 &len); 1554 if (!pinctrl) 1555 return ERR_PTR(-EINVAL); 1556 1557 count = (len / sizeof(*pinctrl)) / 3; 1558 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count); 1559 if (!iodelay) 1560 return ERR_PTR(-EINVAL); 1561 1562 *niodelay = count; 1563 1564 return iodelay; 1565 } 1566 1567 static struct omap_hsmmc_pinctrl_state * 1568 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode) 1569 { 1570 int index; 1571 int npads = 0; 1572 int niodelays = 0; 1573 const void *fdt = gd->fdt_blob; 1574 int node = dev_of_offset(mmc->dev); 1575 char prop_name[11]; 1576 struct omap_hsmmc_pinctrl_state *pinctrl_state; 1577 1578 pinctrl_state = (struct omap_hsmmc_pinctrl_state *) 1579 malloc(sizeof(*pinctrl_state)); 1580 if (!pinctrl_state) { 1581 debug("failed to allocate memory\n"); 1582 return 0; 1583 } 1584 1585 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode); 1586 if (index < 0) { 1587 debug("fail to find %s mode %s\n", mode, fdt_strerror(index)); 1588 goto err_pinctrl_state; 1589 } 1590 1591 sprintf(prop_name, "pinctrl-%d", index); 1592 1593 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name, 1594 &npads); 1595 if (IS_ERR(pinctrl_state->padconf)) 1596 goto err_pinctrl_state; 1597 pinctrl_state->npads = npads; 1598 1599 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name, 1600 &niodelays); 1601 if (IS_ERR(pinctrl_state->iodelay)) 1602 goto err_padconf; 1603 pinctrl_state->niodelays = niodelays; 1604 1605 return pinctrl_state; 1606 1607 err_padconf: 1608 kfree(pinctrl_state->padconf); 1609 1610 err_pinctrl_state: 1611 kfree(pinctrl_state); 1612 return 0; 1613 } 1614 1615 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \ 1616 do { \ 1617 struct omap_hsmmc_pinctrl_state *s = NULL; \ 1618 char str[20]; \ 1619 if (!(cfg->host_caps & capmask)) \ 1620 break; \ 1621 \ 1622 if (priv->hw_rev) { \ 1623 sprintf(str, "%s-%s", #mode, priv->hw_rev); \ 1624 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \ 1625 } \ 1626 \ 1627 if (!s) \ 1628 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ 1629 \ 1630 if (!s && !optional) { \ 1631 debug("%s: no pinctrl for %s\n", \ 1632 mmc->dev->name, #mode); \ 1633 cfg->host_caps &= ~(capmask); \ 1634 } else { \ 1635 priv->mode##_pinctrl_state = s; \ 1636 } \ 1637 } while (0) 1638 1639 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) 1640 { 1641 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); 1642 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); 1643 struct omap_hsmmc_pinctrl_state *default_pinctrl; 1644 1645 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) 1646 return 0; 1647 1648 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default"); 1649 if (!default_pinctrl) { 1650 printf("no pinctrl state for default mode\n"); 1651 return -EINVAL; 1652 } 1653 1654 priv->default_pinctrl_state = default_pinctrl; 1655 1656 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false); 1657 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false); 1658 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false); 1659 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false); 1660 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false); 1661 1662 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false); 1663 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false); 1664 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true); 1665 1666 return 0; 1667 } 1668 #endif 1669 1670 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1671 #ifdef CONFIG_OMAP54XX 1672 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) 1673 { 1674 return NULL; 1675 } 1676 #endif 1677 1678 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) 1679 { 1680 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 1681 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev); 1682 1683 struct mmc_config *cfg = &plat->cfg; 1684 #ifdef CONFIG_OMAP54XX 1685 const struct mmc_platform_fixups *fixups; 1686 #endif 1687 const void *fdt = gd->fdt_blob; 1688 int node = dev_of_offset(dev); 1689 int ret; 1690 1691 plat->base_addr = map_physmem(devfdt_get_addr(dev), 1692 sizeof(struct hsmmc *), 1693 MAP_NOCACHE); 1694 1695 ret = mmc_of_parse(dev, cfg); 1696 if (ret < 0) 1697 return ret; 1698 1699 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 1700 cfg->f_min = 400000; 1701 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1702 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1703 if (fdtdec_get_bool(fdt, node, "ti,dual-volt")) 1704 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1705 if (fdtdec_get_bool(fdt, node, "no-1-8-v")) 1706 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V; 1707 if (of_data) 1708 plat->controller_flags |= of_data->controller_flags; 1709 1710 #ifdef CONFIG_OMAP54XX 1711 fixups = platform_fixups_mmc(devfdt_get_addr(dev)); 1712 if (fixups) { 1713 plat->hw_rev = fixups->hw_rev; 1714 cfg->host_caps &= ~fixups->unsupported_caps; 1715 cfg->f_max = fixups->max_freq; 1716 } 1717 #endif 1718 1719 #ifdef OMAP_HSMMC_USE_GPIO 1720 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); 1721 #endif 1722 1723 return 0; 1724 } 1725 #endif 1726 1727 #ifdef CONFIG_BLK 1728 1729 static int omap_hsmmc_bind(struct udevice *dev) 1730 { 1731 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 1732 1733 return mmc_bind(dev, &plat->mmc, &plat->cfg); 1734 } 1735 #endif 1736 static int omap_hsmmc_probe(struct udevice *dev) 1737 { 1738 struct omap_hsmmc_plat *plat = dev_get_platdata(dev); 1739 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1740 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1741 struct mmc_config *cfg = &plat->cfg; 1742 struct mmc *mmc; 1743 #ifdef CONFIG_IODELAY_RECALIBRATION 1744 int ret; 1745 #endif 1746 1747 cfg->name = "OMAP SD/MMC"; 1748 priv->base_addr = plat->base_addr; 1749 priv->controller_flags = plat->controller_flags; 1750 priv->hw_rev = plat->hw_rev; 1751 #ifdef OMAP_HSMMC_USE_GPIO 1752 priv->cd_inverted = plat->cd_inverted; 1753 #endif 1754 1755 #ifdef CONFIG_BLK 1756 mmc = &plat->mmc; 1757 #else 1758 mmc = mmc_create(cfg, priv); 1759 if (mmc == NULL) 1760 return -1; 1761 #endif 1762 1763 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL) 1764 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); 1765 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); 1766 #endif 1767 1768 mmc->dev = dev; 1769 upriv->mmc = mmc; 1770 1771 #ifdef CONFIG_IODELAY_RECALIBRATION 1772 ret = omap_hsmmc_get_pinctrl_state(mmc); 1773 /* 1774 * disable high speed modes for the platforms that require IO delay 1775 * and for which we don't have this information 1776 */ 1777 if ((ret < 0) && 1778 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) { 1779 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY; 1780 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) | 1781 UHS_CAPS); 1782 } 1783 #endif 1784 1785 return omap_hsmmc_init_setup(mmc); 1786 } 1787 1788 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1789 1790 static const struct omap_mmc_of_data dra7_mmc_of_data = { 1791 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY, 1792 }; 1793 1794 static const struct udevice_id omap_hsmmc_ids[] = { 1795 { .compatible = "ti,omap3-hsmmc" }, 1796 { .compatible = "ti,omap4-hsmmc" }, 1797 { .compatible = "ti,am33xx-hsmmc" }, 1798 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data }, 1799 { } 1800 }; 1801 #endif 1802 1803 U_BOOT_DRIVER(omap_hsmmc) = { 1804 .name = "omap_hsmmc", 1805 .id = UCLASS_MMC, 1806 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1807 .of_match = omap_hsmmc_ids, 1808 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, 1809 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat), 1810 #endif 1811 #ifdef CONFIG_BLK 1812 .bind = omap_hsmmc_bind, 1813 #endif 1814 .ops = &omap_hsmmc_ops, 1815 .probe = omap_hsmmc_probe, 1816 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), 1817 .flags = DM_FLAG_PRE_RELOC, 1818 }; 1819 #endif 1820