1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <malloc.h> 28 #include <mmc.h> 29 #include <part.h> 30 #include <i2c.h> 31 #include <twl4030.h> 32 #include <twl6030.h> 33 #include <palmas.h> 34 #include <asm/gpio.h> 35 #include <asm/io.h> 36 #include <asm/arch/mmc_host_def.h> 37 #include <asm/arch/sys_proto.h> 38 39 /* simplify defines to OMAP_HSMMC_USE_GPIO */ 40 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ 41 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) 42 #define OMAP_HSMMC_USE_GPIO 43 #else 44 #undef OMAP_HSMMC_USE_GPIO 45 #endif 46 47 /* common definitions for all OMAPs */ 48 #define SYSCTL_SRC (1 << 25) 49 #define SYSCTL_SRD (1 << 26) 50 51 struct omap_hsmmc_data { 52 struct hsmmc *base_addr; 53 struct mmc_config cfg; 54 #ifdef OMAP_HSMMC_USE_GPIO 55 int cd_gpio; 56 int wp_gpio; 57 #endif 58 }; 59 60 /* If we fail after 1 second wait, something is really bad */ 61 #define MAX_RETRY_MS 1000 62 63 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 64 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 65 unsigned int siz); 66 67 #ifdef OMAP_HSMMC_USE_GPIO 68 static int omap_mmc_setup_gpio_in(int gpio, const char *label) 69 { 70 int ret; 71 72 #ifndef CONFIG_DM_GPIO 73 if (!gpio_is_valid(gpio)) 74 return -1; 75 #endif 76 ret = gpio_request(gpio, label); 77 if (ret) 78 return ret; 79 80 ret = gpio_direction_input(gpio); 81 if (ret) 82 return ret; 83 84 return gpio; 85 } 86 #endif 87 88 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 89 static void omap4_vmmc_pbias_config(struct mmc *mmc) 90 { 91 u32 value = 0; 92 93 value = readl((*ctrl)->control_pbiaslite); 94 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); 95 writel(value, (*ctrl)->control_pbiaslite); 96 /* set VMMC to 3V */ 97 twl6030_power_mmc_init(); 98 value = readl((*ctrl)->control_pbiaslite); 99 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; 100 writel(value, (*ctrl)->control_pbiaslite); 101 } 102 #endif 103 104 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) 105 static void omap5_pbias_config(struct mmc *mmc) 106 { 107 u32 value = 0; 108 109 value = readl((*ctrl)->control_pbias); 110 value &= ~SDCARD_PWRDNZ; 111 writel(value, (*ctrl)->control_pbias); 112 udelay(10); /* wait 10 us */ 113 value &= ~SDCARD_BIAS_PWRDNZ; 114 writel(value, (*ctrl)->control_pbias); 115 116 palmas_mmc1_poweron_ldo(); 117 118 value = readl((*ctrl)->control_pbias); 119 value |= SDCARD_BIAS_PWRDNZ; 120 writel(value, (*ctrl)->control_pbias); 121 udelay(150); /* wait 150 us */ 122 value |= SDCARD_PWRDNZ; 123 writel(value, (*ctrl)->control_pbias); 124 udelay(150); /* wait 150 us */ 125 } 126 #endif 127 128 static unsigned char mmc_board_init(struct mmc *mmc) 129 { 130 #if defined(CONFIG_OMAP34XX) 131 t2_t *t2_base = (t2_t *)T2_BASE; 132 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 133 u32 pbias_lite; 134 135 pbias_lite = readl(&t2_base->pbias_lite); 136 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 137 writel(pbias_lite, &t2_base->pbias_lite); 138 #endif 139 #if defined(CONFIG_TWL4030_POWER) 140 twl4030_power_mmc_init(); 141 mdelay(100); /* ramp-up delay from Linux code */ 142 #endif 143 #if defined(CONFIG_OMAP34XX) 144 writel(pbias_lite | PBIASLITEPWRDNZ1 | 145 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 146 &t2_base->pbias_lite); 147 148 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 149 &t2_base->devconf0); 150 151 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 152 &t2_base->devconf1); 153 154 /* Change from default of 52MHz to 26MHz if necessary */ 155 if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz)) 156 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, 157 &t2_base->ctl_prog_io1); 158 159 writel(readl(&prcm_base->fclken1_core) | 160 EN_MMC1 | EN_MMC2 | EN_MMC3, 161 &prcm_base->fclken1_core); 162 163 writel(readl(&prcm_base->iclken1_core) | 164 EN_MMC1 | EN_MMC2 | EN_MMC3, 165 &prcm_base->iclken1_core); 166 #endif 167 168 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 169 /* PBIAS config needed for MMC1 only */ 170 if (mmc->block_dev.dev == 0) 171 omap4_vmmc_pbias_config(mmc); 172 #endif 173 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) 174 if (mmc->block_dev.dev == 0) 175 omap5_pbias_config(mmc); 176 #endif 177 178 return 0; 179 } 180 181 void mmc_init_stream(struct hsmmc *mmc_base) 182 { 183 ulong start; 184 185 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 186 187 writel(MMC_CMD0, &mmc_base->cmd); 188 start = get_timer(0); 189 while (!(readl(&mmc_base->stat) & CC_MASK)) { 190 if (get_timer(0) - start > MAX_RETRY_MS) { 191 printf("%s: timedout waiting for cc!\n", __func__); 192 return; 193 } 194 } 195 writel(CC_MASK, &mmc_base->stat) 196 ; 197 writel(MMC_CMD0, &mmc_base->cmd) 198 ; 199 start = get_timer(0); 200 while (!(readl(&mmc_base->stat) & CC_MASK)) { 201 if (get_timer(0) - start > MAX_RETRY_MS) { 202 printf("%s: timedout waiting for cc2!\n", __func__); 203 return; 204 } 205 } 206 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 207 } 208 209 210 static int omap_hsmmc_init_setup(struct mmc *mmc) 211 { 212 struct hsmmc *mmc_base; 213 unsigned int reg_val; 214 unsigned int dsor; 215 ulong start; 216 217 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 218 mmc_board_init(mmc); 219 220 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 221 &mmc_base->sysconfig); 222 start = get_timer(0); 223 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 224 if (get_timer(0) - start > MAX_RETRY_MS) { 225 printf("%s: timedout waiting for cc2!\n", __func__); 226 return TIMEOUT; 227 } 228 } 229 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 230 start = get_timer(0); 231 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 232 if (get_timer(0) - start > MAX_RETRY_MS) { 233 printf("%s: timedout waiting for softresetall!\n", 234 __func__); 235 return TIMEOUT; 236 } 237 } 238 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 239 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 240 &mmc_base->capa); 241 242 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 243 244 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 245 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 246 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 247 248 dsor = 240; 249 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 250 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 251 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 252 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 253 start = get_timer(0); 254 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 255 if (get_timer(0) - start > MAX_RETRY_MS) { 256 printf("%s: timedout waiting for ics!\n", __func__); 257 return TIMEOUT; 258 } 259 } 260 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 261 262 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 263 264 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 265 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 266 &mmc_base->ie); 267 268 mmc_init_stream(mmc_base); 269 270 return 0; 271 } 272 273 /* 274 * MMC controller internal finite state machine reset 275 * 276 * Used to reset command or data internal state machines, using respectively 277 * SRC or SRD bit of SYSCTL register 278 */ 279 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 280 { 281 ulong start; 282 283 mmc_reg_out(&mmc_base->sysctl, bit, bit); 284 285 /* 286 * CMD(DAT) lines reset procedures are slightly different 287 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). 288 * According to OMAP3 TRM: 289 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it 290 * returns to 0x0. 291 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset 292 * procedure steps must be as follows: 293 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in 294 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). 295 * 2. Poll the SRC(SRD) bit until it is set to 0x1. 296 * 3. Wait until the SRC (SRD) bit returns to 0x0 297 * (reset procedure is completed). 298 */ 299 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 300 defined(CONFIG_AM33XX) 301 if (!(readl(&mmc_base->sysctl) & bit)) { 302 start = get_timer(0); 303 while (!(readl(&mmc_base->sysctl) & bit)) { 304 if (get_timer(0) - start > MAX_RETRY_MS) 305 return; 306 } 307 } 308 #endif 309 start = get_timer(0); 310 while ((readl(&mmc_base->sysctl) & bit) != 0) { 311 if (get_timer(0) - start > MAX_RETRY_MS) { 312 printf("%s: timedout waiting for sysctl %x to clear\n", 313 __func__, bit); 314 return; 315 } 316 } 317 } 318 319 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 320 struct mmc_data *data) 321 { 322 struct hsmmc *mmc_base; 323 unsigned int flags, mmc_stat; 324 ulong start; 325 326 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 327 start = get_timer(0); 328 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 329 if (get_timer(0) - start > MAX_RETRY_MS) { 330 printf("%s: timedout waiting on cmd inhibit to clear\n", 331 __func__); 332 return TIMEOUT; 333 } 334 } 335 writel(0xFFFFFFFF, &mmc_base->stat); 336 start = get_timer(0); 337 while (readl(&mmc_base->stat)) { 338 if (get_timer(0) - start > MAX_RETRY_MS) { 339 printf("%s: timedout waiting for STAT (%x) to clear\n", 340 __func__, readl(&mmc_base->stat)); 341 return TIMEOUT; 342 } 343 } 344 /* 345 * CMDREG 346 * CMDIDX[13:8] : Command index 347 * DATAPRNT[5] : Data Present Select 348 * ENCMDIDX[4] : Command Index Check Enable 349 * ENCMDCRC[3] : Command CRC Check Enable 350 * RSPTYP[1:0] 351 * 00 = No Response 352 * 01 = Length 136 353 * 10 = Length 48 354 * 11 = Length 48 Check busy after response 355 */ 356 /* Delay added before checking the status of frq change 357 * retry not supported by mmc.c(core file) 358 */ 359 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 360 udelay(50000); /* wait 50 ms */ 361 362 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 363 flags = 0; 364 else if (cmd->resp_type & MMC_RSP_136) 365 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 366 else if (cmd->resp_type & MMC_RSP_BUSY) 367 flags = RSP_TYPE_LGHT48B; 368 else 369 flags = RSP_TYPE_LGHT48; 370 371 /* enable default flags */ 372 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 373 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 374 375 if (cmd->resp_type & MMC_RSP_CRC) 376 flags |= CCCE_CHECK; 377 if (cmd->resp_type & MMC_RSP_OPCODE) 378 flags |= CICE_CHECK; 379 380 if (data) { 381 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 382 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 383 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 384 data->blocksize = 512; 385 writel(data->blocksize | (data->blocks << 16), 386 &mmc_base->blk); 387 } else 388 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 389 390 if (data->flags & MMC_DATA_READ) 391 flags |= (DP_DATA | DDIR_READ); 392 else 393 flags |= (DP_DATA | DDIR_WRITE); 394 } 395 396 writel(cmd->cmdarg, &mmc_base->arg); 397 udelay(20); /* To fix "No status update" error on eMMC */ 398 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 399 400 start = get_timer(0); 401 do { 402 mmc_stat = readl(&mmc_base->stat); 403 if (get_timer(0) - start > MAX_RETRY_MS) { 404 printf("%s : timeout: No status update\n", __func__); 405 return TIMEOUT; 406 } 407 } while (!mmc_stat); 408 409 if ((mmc_stat & IE_CTO) != 0) { 410 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 411 return TIMEOUT; 412 } else if ((mmc_stat & ERRI_MASK) != 0) 413 return -1; 414 415 if (mmc_stat & CC_MASK) { 416 writel(CC_MASK, &mmc_base->stat); 417 if (cmd->resp_type & MMC_RSP_PRESENT) { 418 if (cmd->resp_type & MMC_RSP_136) { 419 /* response type 2 */ 420 cmd->response[3] = readl(&mmc_base->rsp10); 421 cmd->response[2] = readl(&mmc_base->rsp32); 422 cmd->response[1] = readl(&mmc_base->rsp54); 423 cmd->response[0] = readl(&mmc_base->rsp76); 424 } else 425 /* response types 1, 1b, 3, 4, 5, 6 */ 426 cmd->response[0] = readl(&mmc_base->rsp10); 427 } 428 } 429 430 if (data && (data->flags & MMC_DATA_READ)) { 431 mmc_read_data(mmc_base, data->dest, 432 data->blocksize * data->blocks); 433 } else if (data && (data->flags & MMC_DATA_WRITE)) { 434 mmc_write_data(mmc_base, data->src, 435 data->blocksize * data->blocks); 436 } 437 return 0; 438 } 439 440 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 441 { 442 unsigned int *output_buf = (unsigned int *)buf; 443 unsigned int mmc_stat; 444 unsigned int count; 445 446 /* 447 * Start Polled Read 448 */ 449 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 450 count /= 4; 451 452 while (size) { 453 ulong start = get_timer(0); 454 do { 455 mmc_stat = readl(&mmc_base->stat); 456 if (get_timer(0) - start > MAX_RETRY_MS) { 457 printf("%s: timedout waiting for status!\n", 458 __func__); 459 return TIMEOUT; 460 } 461 } while (mmc_stat == 0); 462 463 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 464 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 465 466 if ((mmc_stat & ERRI_MASK) != 0) 467 return 1; 468 469 if (mmc_stat & BRR_MASK) { 470 unsigned int k; 471 472 writel(readl(&mmc_base->stat) | BRR_MASK, 473 &mmc_base->stat); 474 for (k = 0; k < count; k++) { 475 *output_buf = readl(&mmc_base->data); 476 output_buf++; 477 } 478 size -= (count*4); 479 } 480 481 if (mmc_stat & BWR_MASK) 482 writel(readl(&mmc_base->stat) | BWR_MASK, 483 &mmc_base->stat); 484 485 if (mmc_stat & TC_MASK) { 486 writel(readl(&mmc_base->stat) | TC_MASK, 487 &mmc_base->stat); 488 break; 489 } 490 } 491 return 0; 492 } 493 494 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 495 unsigned int size) 496 { 497 unsigned int *input_buf = (unsigned int *)buf; 498 unsigned int mmc_stat; 499 unsigned int count; 500 501 /* 502 * Start Polled Write 503 */ 504 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 505 count /= 4; 506 507 while (size) { 508 ulong start = get_timer(0); 509 do { 510 mmc_stat = readl(&mmc_base->stat); 511 if (get_timer(0) - start > MAX_RETRY_MS) { 512 printf("%s: timedout waiting for status!\n", 513 __func__); 514 return TIMEOUT; 515 } 516 } while (mmc_stat == 0); 517 518 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 519 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 520 521 if ((mmc_stat & ERRI_MASK) != 0) 522 return 1; 523 524 if (mmc_stat & BWR_MASK) { 525 unsigned int k; 526 527 writel(readl(&mmc_base->stat) | BWR_MASK, 528 &mmc_base->stat); 529 for (k = 0; k < count; k++) { 530 writel(*input_buf, &mmc_base->data); 531 input_buf++; 532 } 533 size -= (count*4); 534 } 535 536 if (mmc_stat & BRR_MASK) 537 writel(readl(&mmc_base->stat) | BRR_MASK, 538 &mmc_base->stat); 539 540 if (mmc_stat & TC_MASK) { 541 writel(readl(&mmc_base->stat) | TC_MASK, 542 &mmc_base->stat); 543 break; 544 } 545 } 546 return 0; 547 } 548 549 static void omap_hsmmc_set_ios(struct mmc *mmc) 550 { 551 struct hsmmc *mmc_base; 552 unsigned int dsor = 0; 553 ulong start; 554 555 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 556 /* configue bus width */ 557 switch (mmc->bus_width) { 558 case 8: 559 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 560 &mmc_base->con); 561 break; 562 563 case 4: 564 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 565 &mmc_base->con); 566 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 567 &mmc_base->hctl); 568 break; 569 570 case 1: 571 default: 572 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 573 &mmc_base->con); 574 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 575 &mmc_base->hctl); 576 break; 577 } 578 579 /* configure clock with 96Mhz system clock. 580 */ 581 if (mmc->clock != 0) { 582 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 583 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 584 dsor++; 585 } 586 587 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 588 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 589 590 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 591 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 592 593 start = get_timer(0); 594 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 595 if (get_timer(0) - start > MAX_RETRY_MS) { 596 printf("%s: timedout waiting for ics!\n", __func__); 597 return; 598 } 599 } 600 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 601 } 602 603 #ifdef OMAP_HSMMC_USE_GPIO 604 static int omap_hsmmc_getcd(struct mmc *mmc) 605 { 606 struct omap_hsmmc_data *priv_data = mmc->priv; 607 int cd_gpio; 608 609 /* if no CD return as 1 */ 610 cd_gpio = priv_data->cd_gpio; 611 if (cd_gpio < 0) 612 return 1; 613 614 /* NOTE: assumes card detect signal is active-low */ 615 return !gpio_get_value(cd_gpio); 616 } 617 618 static int omap_hsmmc_getwp(struct mmc *mmc) 619 { 620 struct omap_hsmmc_data *priv_data = mmc->priv; 621 int wp_gpio; 622 623 /* if no WP return as 0 */ 624 wp_gpio = priv_data->wp_gpio; 625 if (wp_gpio < 0) 626 return 0; 627 628 /* NOTE: assumes write protect signal is active-high */ 629 return gpio_get_value(wp_gpio); 630 } 631 #endif 632 633 static const struct mmc_ops omap_hsmmc_ops = { 634 .send_cmd = omap_hsmmc_send_cmd, 635 .set_ios = omap_hsmmc_set_ios, 636 .init = omap_hsmmc_init_setup, 637 #ifdef OMAP_HSMMC_USE_GPIO 638 .getcd = omap_hsmmc_getcd, 639 .getwp = omap_hsmmc_getwp, 640 #endif 641 }; 642 643 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 644 int wp_gpio) 645 { 646 struct mmc *mmc; 647 struct omap_hsmmc_data *priv_data; 648 struct mmc_config *cfg; 649 uint host_caps_val; 650 651 priv_data = malloc(sizeof(*priv_data)); 652 if (priv_data == NULL) 653 return -1; 654 655 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | 656 MMC_MODE_HC; 657 658 switch (dev_index) { 659 case 0: 660 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 661 break; 662 #ifdef OMAP_HSMMC2_BASE 663 case 1: 664 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; 665 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 666 defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT) 667 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ 668 host_caps_val |= MMC_MODE_8BIT; 669 #endif 670 break; 671 #endif 672 #ifdef OMAP_HSMMC3_BASE 673 case 2: 674 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; 675 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) 676 /* Enable 8-bit interface for eMMC on DRA7XX */ 677 host_caps_val |= MMC_MODE_8BIT; 678 #endif 679 break; 680 #endif 681 default: 682 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 683 return 1; 684 } 685 #ifdef OMAP_HSMMC_USE_GPIO 686 /* on error gpio values are set to -1, which is what we want */ 687 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); 688 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); 689 #endif 690 691 cfg = &priv_data->cfg; 692 693 cfg->name = "OMAP SD/MMC"; 694 cfg->ops = &omap_hsmmc_ops; 695 696 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 697 cfg->host_caps = host_caps_val & ~host_caps_mask; 698 699 cfg->f_min = 400000; 700 701 if (f_max != 0) 702 cfg->f_max = f_max; 703 else { 704 if (cfg->host_caps & MMC_MODE_HS) { 705 if (cfg->host_caps & MMC_MODE_HS_52MHz) 706 cfg->f_max = 52000000; 707 else 708 cfg->f_max = 26000000; 709 } else 710 cfg->f_max = 20000000; 711 } 712 713 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 714 715 #if defined(CONFIG_OMAP34XX) 716 /* 717 * Silicon revs 2.1 and older do not support multiblock transfers. 718 */ 719 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 720 cfg->b_max = 1; 721 #endif 722 mmc = mmc_create(cfg, priv_data); 723 if (mmc == NULL) 724 return -1; 725 726 return 0; 727 } 728