1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <twl6030.h> 32 #include <palmas.h> 33 #include <asm/gpio.h> 34 #include <asm/io.h> 35 #include <asm/arch/mmc_host_def.h> 36 #include <asm/arch/sys_proto.h> 37 38 /* common definitions for all OMAPs */ 39 #define SYSCTL_SRC (1 << 25) 40 #define SYSCTL_SRD (1 << 26) 41 42 struct omap_hsmmc_data { 43 struct hsmmc *base_addr; 44 int cd_gpio; 45 int wp_gpio; 46 }; 47 48 /* If we fail after 1 second wait, something is really bad */ 49 #define MAX_RETRY_MS 1000 50 51 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 52 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 53 unsigned int siz); 54 static struct mmc hsmmc_dev[3]; 55 static struct omap_hsmmc_data hsmmc_dev_data[3]; 56 57 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ 58 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) 59 static int omap_mmc_setup_gpio_in(int gpio, const char *label) 60 { 61 if (!gpio_is_valid(gpio)) 62 return -1; 63 64 if (gpio_request(gpio, label) < 0) 65 return -1; 66 67 if (gpio_direction_input(gpio) < 0) 68 return -1; 69 70 return gpio; 71 } 72 73 static int omap_mmc_getcd(struct mmc *mmc) 74 { 75 int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio; 76 return gpio_get_value(cd_gpio); 77 } 78 79 static int omap_mmc_getwp(struct mmc *mmc) 80 { 81 int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio; 82 return gpio_get_value(wp_gpio); 83 } 84 #else 85 static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) 86 { 87 return -1; 88 } 89 90 #define omap_mmc_getcd NULL 91 #define omap_mmc_getwp NULL 92 #endif 93 94 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 95 static void omap4_vmmc_pbias_config(struct mmc *mmc) 96 { 97 u32 value = 0; 98 99 value = readl((*ctrl)->control_pbiaslite); 100 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); 101 writel(value, (*ctrl)->control_pbiaslite); 102 /* set VMMC to 3V */ 103 twl6030_power_mmc_init(); 104 value = readl((*ctrl)->control_pbiaslite); 105 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; 106 writel(value, (*ctrl)->control_pbiaslite); 107 } 108 #endif 109 110 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) 111 static void omap5_pbias_config(struct mmc *mmc) 112 { 113 u32 value = 0; 114 115 value = readl((*ctrl)->control_pbias); 116 value &= ~SDCARD_PWRDNZ; 117 writel(value, (*ctrl)->control_pbias); 118 udelay(10); /* wait 10 us */ 119 value &= ~SDCARD_BIAS_PWRDNZ; 120 writel(value, (*ctrl)->control_pbias); 121 122 palmas_mmc1_poweron_ldo(); 123 124 value = readl((*ctrl)->control_pbias); 125 value |= SDCARD_BIAS_PWRDNZ; 126 writel(value, (*ctrl)->control_pbias); 127 udelay(150); /* wait 150 us */ 128 value |= SDCARD_PWRDNZ; 129 writel(value, (*ctrl)->control_pbias); 130 udelay(150); /* wait 150 us */ 131 } 132 #endif 133 134 unsigned char mmc_board_init(struct mmc *mmc) 135 { 136 #if defined(CONFIG_OMAP34XX) 137 t2_t *t2_base = (t2_t *)T2_BASE; 138 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 139 u32 pbias_lite; 140 141 pbias_lite = readl(&t2_base->pbias_lite); 142 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 143 writel(pbias_lite, &t2_base->pbias_lite); 144 #endif 145 #if defined(CONFIG_TWL4030_POWER) 146 twl4030_power_mmc_init(); 147 mdelay(100); /* ramp-up delay from Linux code */ 148 #endif 149 #if defined(CONFIG_OMAP34XX) 150 writel(pbias_lite | PBIASLITEPWRDNZ1 | 151 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 152 &t2_base->pbias_lite); 153 154 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 155 &t2_base->devconf0); 156 157 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 158 &t2_base->devconf1); 159 160 /* Change from default of 52MHz to 26MHz if necessary */ 161 if (!(mmc->host_caps & MMC_MODE_HS_52MHz)) 162 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, 163 &t2_base->ctl_prog_io1); 164 165 writel(readl(&prcm_base->fclken1_core) | 166 EN_MMC1 | EN_MMC2 | EN_MMC3, 167 &prcm_base->fclken1_core); 168 169 writel(readl(&prcm_base->iclken1_core) | 170 EN_MMC1 | EN_MMC2 | EN_MMC3, 171 &prcm_base->iclken1_core); 172 #endif 173 174 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 175 /* PBIAS config needed for MMC1 only */ 176 if (mmc->block_dev.dev == 0) 177 omap4_vmmc_pbias_config(mmc); 178 #endif 179 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) 180 if (mmc->block_dev.dev == 0) 181 omap5_pbias_config(mmc); 182 #endif 183 184 return 0; 185 } 186 187 void mmc_init_stream(struct hsmmc *mmc_base) 188 { 189 ulong start; 190 191 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 192 193 writel(MMC_CMD0, &mmc_base->cmd); 194 start = get_timer(0); 195 while (!(readl(&mmc_base->stat) & CC_MASK)) { 196 if (get_timer(0) - start > MAX_RETRY_MS) { 197 printf("%s: timedout waiting for cc!\n", __func__); 198 return; 199 } 200 } 201 writel(CC_MASK, &mmc_base->stat) 202 ; 203 writel(MMC_CMD0, &mmc_base->cmd) 204 ; 205 start = get_timer(0); 206 while (!(readl(&mmc_base->stat) & CC_MASK)) { 207 if (get_timer(0) - start > MAX_RETRY_MS) { 208 printf("%s: timedout waiting for cc2!\n", __func__); 209 return; 210 } 211 } 212 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 213 } 214 215 216 static int mmc_init_setup(struct mmc *mmc) 217 { 218 struct hsmmc *mmc_base; 219 unsigned int reg_val; 220 unsigned int dsor; 221 ulong start; 222 223 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 224 mmc_board_init(mmc); 225 226 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 227 &mmc_base->sysconfig); 228 start = get_timer(0); 229 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 230 if (get_timer(0) - start > MAX_RETRY_MS) { 231 printf("%s: timedout waiting for cc2!\n", __func__); 232 return TIMEOUT; 233 } 234 } 235 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 236 start = get_timer(0); 237 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 238 if (get_timer(0) - start > MAX_RETRY_MS) { 239 printf("%s: timedout waiting for softresetall!\n", 240 __func__); 241 return TIMEOUT; 242 } 243 } 244 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 245 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 246 &mmc_base->capa); 247 248 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 249 250 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 251 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 252 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 253 254 dsor = 240; 255 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 256 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 257 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 258 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 259 start = get_timer(0); 260 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 261 if (get_timer(0) - start > MAX_RETRY_MS) { 262 printf("%s: timedout waiting for ics!\n", __func__); 263 return TIMEOUT; 264 } 265 } 266 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 267 268 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 269 270 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 271 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 272 &mmc_base->ie); 273 274 mmc_init_stream(mmc_base); 275 276 return 0; 277 } 278 279 /* 280 * MMC controller internal finite state machine reset 281 * 282 * Used to reset command or data internal state machines, using respectively 283 * SRC or SRD bit of SYSCTL register 284 */ 285 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 286 { 287 ulong start; 288 289 mmc_reg_out(&mmc_base->sysctl, bit, bit); 290 291 start = get_timer(0); 292 while ((readl(&mmc_base->sysctl) & bit) != 0) { 293 if (get_timer(0) - start > MAX_RETRY_MS) { 294 printf("%s: timedout waiting for sysctl %x to clear\n", 295 __func__, bit); 296 return; 297 } 298 } 299 } 300 301 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 302 struct mmc_data *data) 303 { 304 struct hsmmc *mmc_base; 305 unsigned int flags, mmc_stat; 306 ulong start; 307 308 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 309 start = get_timer(0); 310 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 311 if (get_timer(0) - start > MAX_RETRY_MS) { 312 printf("%s: timedout waiting on cmd inhibit to clear\n", 313 __func__); 314 return TIMEOUT; 315 } 316 } 317 writel(0xFFFFFFFF, &mmc_base->stat); 318 start = get_timer(0); 319 while (readl(&mmc_base->stat)) { 320 if (get_timer(0) - start > MAX_RETRY_MS) { 321 printf("%s: timedout waiting for STAT (%x) to clear\n", 322 __func__, readl(&mmc_base->stat)); 323 return TIMEOUT; 324 } 325 } 326 /* 327 * CMDREG 328 * CMDIDX[13:8] : Command index 329 * DATAPRNT[5] : Data Present Select 330 * ENCMDIDX[4] : Command Index Check Enable 331 * ENCMDCRC[3] : Command CRC Check Enable 332 * RSPTYP[1:0] 333 * 00 = No Response 334 * 01 = Length 136 335 * 10 = Length 48 336 * 11 = Length 48 Check busy after response 337 */ 338 /* Delay added before checking the status of frq change 339 * retry not supported by mmc.c(core file) 340 */ 341 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 342 udelay(50000); /* wait 50 ms */ 343 344 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 345 flags = 0; 346 else if (cmd->resp_type & MMC_RSP_136) 347 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 348 else if (cmd->resp_type & MMC_RSP_BUSY) 349 flags = RSP_TYPE_LGHT48B; 350 else 351 flags = RSP_TYPE_LGHT48; 352 353 /* enable default flags */ 354 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 355 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 356 357 if (cmd->resp_type & MMC_RSP_CRC) 358 flags |= CCCE_CHECK; 359 if (cmd->resp_type & MMC_RSP_OPCODE) 360 flags |= CICE_CHECK; 361 362 if (data) { 363 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 364 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 365 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 366 data->blocksize = 512; 367 writel(data->blocksize | (data->blocks << 16), 368 &mmc_base->blk); 369 } else 370 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 371 372 if (data->flags & MMC_DATA_READ) 373 flags |= (DP_DATA | DDIR_READ); 374 else 375 flags |= (DP_DATA | DDIR_WRITE); 376 } 377 378 writel(cmd->cmdarg, &mmc_base->arg); 379 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 380 381 start = get_timer(0); 382 do { 383 mmc_stat = readl(&mmc_base->stat); 384 if (get_timer(0) - start > MAX_RETRY_MS) { 385 printf("%s : timeout: No status update\n", __func__); 386 return TIMEOUT; 387 } 388 } while (!mmc_stat); 389 390 if ((mmc_stat & IE_CTO) != 0) { 391 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 392 return TIMEOUT; 393 } else if ((mmc_stat & ERRI_MASK) != 0) 394 return -1; 395 396 if (mmc_stat & CC_MASK) { 397 writel(CC_MASK, &mmc_base->stat); 398 if (cmd->resp_type & MMC_RSP_PRESENT) { 399 if (cmd->resp_type & MMC_RSP_136) { 400 /* response type 2 */ 401 cmd->response[3] = readl(&mmc_base->rsp10); 402 cmd->response[2] = readl(&mmc_base->rsp32); 403 cmd->response[1] = readl(&mmc_base->rsp54); 404 cmd->response[0] = readl(&mmc_base->rsp76); 405 } else 406 /* response types 1, 1b, 3, 4, 5, 6 */ 407 cmd->response[0] = readl(&mmc_base->rsp10); 408 } 409 } 410 411 if (data && (data->flags & MMC_DATA_READ)) { 412 mmc_read_data(mmc_base, data->dest, 413 data->blocksize * data->blocks); 414 } else if (data && (data->flags & MMC_DATA_WRITE)) { 415 mmc_write_data(mmc_base, data->src, 416 data->blocksize * data->blocks); 417 } 418 return 0; 419 } 420 421 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 422 { 423 unsigned int *output_buf = (unsigned int *)buf; 424 unsigned int mmc_stat; 425 unsigned int count; 426 427 /* 428 * Start Polled Read 429 */ 430 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 431 count /= 4; 432 433 while (size) { 434 ulong start = get_timer(0); 435 do { 436 mmc_stat = readl(&mmc_base->stat); 437 if (get_timer(0) - start > MAX_RETRY_MS) { 438 printf("%s: timedout waiting for status!\n", 439 __func__); 440 return TIMEOUT; 441 } 442 } while (mmc_stat == 0); 443 444 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 445 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 446 447 if ((mmc_stat & ERRI_MASK) != 0) 448 return 1; 449 450 if (mmc_stat & BRR_MASK) { 451 unsigned int k; 452 453 writel(readl(&mmc_base->stat) | BRR_MASK, 454 &mmc_base->stat); 455 for (k = 0; k < count; k++) { 456 *output_buf = readl(&mmc_base->data); 457 output_buf++; 458 } 459 size -= (count*4); 460 } 461 462 if (mmc_stat & BWR_MASK) 463 writel(readl(&mmc_base->stat) | BWR_MASK, 464 &mmc_base->stat); 465 466 if (mmc_stat & TC_MASK) { 467 writel(readl(&mmc_base->stat) | TC_MASK, 468 &mmc_base->stat); 469 break; 470 } 471 } 472 return 0; 473 } 474 475 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 476 unsigned int size) 477 { 478 unsigned int *input_buf = (unsigned int *)buf; 479 unsigned int mmc_stat; 480 unsigned int count; 481 482 /* 483 * Start Polled Read 484 */ 485 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 486 count /= 4; 487 488 while (size) { 489 ulong start = get_timer(0); 490 do { 491 mmc_stat = readl(&mmc_base->stat); 492 if (get_timer(0) - start > MAX_RETRY_MS) { 493 printf("%s: timedout waiting for status!\n", 494 __func__); 495 return TIMEOUT; 496 } 497 } while (mmc_stat == 0); 498 499 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 500 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 501 502 if ((mmc_stat & ERRI_MASK) != 0) 503 return 1; 504 505 if (mmc_stat & BWR_MASK) { 506 unsigned int k; 507 508 writel(readl(&mmc_base->stat) | BWR_MASK, 509 &mmc_base->stat); 510 for (k = 0; k < count; k++) { 511 writel(*input_buf, &mmc_base->data); 512 input_buf++; 513 } 514 size -= (count*4); 515 } 516 517 if (mmc_stat & BRR_MASK) 518 writel(readl(&mmc_base->stat) | BRR_MASK, 519 &mmc_base->stat); 520 521 if (mmc_stat & TC_MASK) { 522 writel(readl(&mmc_base->stat) | TC_MASK, 523 &mmc_base->stat); 524 break; 525 } 526 } 527 return 0; 528 } 529 530 static void mmc_set_ios(struct mmc *mmc) 531 { 532 struct hsmmc *mmc_base; 533 unsigned int dsor = 0; 534 ulong start; 535 536 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 537 /* configue bus width */ 538 switch (mmc->bus_width) { 539 case 8: 540 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 541 &mmc_base->con); 542 break; 543 544 case 4: 545 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 546 &mmc_base->con); 547 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 548 &mmc_base->hctl); 549 break; 550 551 case 1: 552 default: 553 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 554 &mmc_base->con); 555 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 556 &mmc_base->hctl); 557 break; 558 } 559 560 /* configure clock with 96Mhz system clock. 561 */ 562 if (mmc->clock != 0) { 563 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 564 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 565 dsor++; 566 } 567 568 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 569 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 570 571 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 572 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 573 574 start = get_timer(0); 575 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 576 if (get_timer(0) - start > MAX_RETRY_MS) { 577 printf("%s: timedout waiting for ics!\n", __func__); 578 return; 579 } 580 } 581 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 582 } 583 584 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 585 int wp_gpio) 586 { 587 struct mmc *mmc = &hsmmc_dev[dev_index]; 588 struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index]; 589 590 sprintf(mmc->name, "OMAP SD/MMC"); 591 mmc->send_cmd = mmc_send_cmd; 592 mmc->set_ios = mmc_set_ios; 593 mmc->init = mmc_init_setup; 594 mmc->priv = priv_data; 595 596 switch (dev_index) { 597 case 0: 598 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 599 break; 600 #ifdef OMAP_HSMMC2_BASE 601 case 1: 602 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; 603 break; 604 #endif 605 #ifdef OMAP_HSMMC3_BASE 606 case 2: 607 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; 608 break; 609 #endif 610 default: 611 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 612 return 1; 613 } 614 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); 615 if (priv_data->cd_gpio != -1) 616 mmc->getcd = omap_mmc_getcd; 617 618 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); 619 if (priv_data->wp_gpio != -1) 620 mmc->getwp = omap_mmc_getwp; 621 622 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 623 mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | 624 MMC_MODE_HC) & ~host_caps_mask; 625 626 mmc->f_min = 400000; 627 628 if (f_max != 0) 629 mmc->f_max = f_max; 630 else { 631 if (mmc->host_caps & MMC_MODE_HS) { 632 if (mmc->host_caps & MMC_MODE_HS_52MHz) 633 mmc->f_max = 52000000; 634 else 635 mmc->f_max = 26000000; 636 } else 637 mmc->f_max = 20000000; 638 } 639 640 mmc->b_max = 0; 641 642 #if defined(CONFIG_OMAP34XX) 643 /* 644 * Silicon revs 2.1 and older do not support multiblock transfers. 645 */ 646 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 647 mmc->b_max = 1; 648 #endif 649 650 mmc_register(mmc); 651 652 return 0; 653 } 654