1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <twl6030.h> 32 #include <palmas.h> 33 #include <asm/gpio.h> 34 #include <asm/io.h> 35 #include <asm/arch/mmc_host_def.h> 36 #include <asm/arch/sys_proto.h> 37 38 /* common definitions for all OMAPs */ 39 #define SYSCTL_SRC (1 << 25) 40 #define SYSCTL_SRD (1 << 26) 41 42 struct omap_hsmmc_data { 43 struct hsmmc *base_addr; 44 int cd_gpio; 45 int wp_gpio; 46 }; 47 48 /* If we fail after 1 second wait, something is really bad */ 49 #define MAX_RETRY_MS 1000 50 51 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); 52 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 53 unsigned int siz); 54 static struct mmc hsmmc_dev[3]; 55 static struct omap_hsmmc_data hsmmc_dev_data[3]; 56 57 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ 58 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) 59 static int omap_mmc_setup_gpio_in(int gpio, const char *label) 60 { 61 if (!gpio_is_valid(gpio)) 62 return -1; 63 64 if (gpio_request(gpio, label) < 0) 65 return -1; 66 67 if (gpio_direction_input(gpio) < 0) 68 return -1; 69 70 return gpio; 71 } 72 73 static int omap_mmc_getcd(struct mmc *mmc) 74 { 75 int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio; 76 return gpio_get_value(cd_gpio); 77 } 78 79 static int omap_mmc_getwp(struct mmc *mmc) 80 { 81 int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio; 82 return gpio_get_value(wp_gpio); 83 } 84 #else 85 static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) 86 { 87 return -1; 88 } 89 90 #define omap_mmc_getcd NULL 91 #define omap_mmc_getwp NULL 92 #endif 93 94 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 95 static void omap4_vmmc_pbias_config(struct mmc *mmc) 96 { 97 u32 value = 0; 98 99 value = readl((*ctrl)->control_pbiaslite); 100 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); 101 writel(value, (*ctrl)->control_pbiaslite); 102 /* set VMMC to 3V */ 103 twl6030_power_mmc_init(); 104 value = readl((*ctrl)->control_pbiaslite); 105 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; 106 writel(value, (*ctrl)->control_pbiaslite); 107 } 108 #endif 109 110 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) 111 static void omap5_pbias_config(struct mmc *mmc) 112 { 113 u32 value = 0; 114 115 value = readl((*ctrl)->control_pbias); 116 value &= ~SDCARD_PWRDNZ; 117 writel(value, (*ctrl)->control_pbias); 118 udelay(10); /* wait 10 us */ 119 value &= ~SDCARD_BIAS_PWRDNZ; 120 writel(value, (*ctrl)->control_pbias); 121 122 palmas_mmc1_poweron_ldo(); 123 124 value = readl((*ctrl)->control_pbias); 125 value |= SDCARD_BIAS_PWRDNZ; 126 writel(value, (*ctrl)->control_pbias); 127 udelay(150); /* wait 150 us */ 128 value |= SDCARD_PWRDNZ; 129 writel(value, (*ctrl)->control_pbias); 130 udelay(150); /* wait 150 us */ 131 } 132 #endif 133 134 unsigned char mmc_board_init(struct mmc *mmc) 135 { 136 #if defined(CONFIG_OMAP34XX) 137 t2_t *t2_base = (t2_t *)T2_BASE; 138 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 139 u32 pbias_lite; 140 141 pbias_lite = readl(&t2_base->pbias_lite); 142 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); 143 writel(pbias_lite, &t2_base->pbias_lite); 144 #endif 145 #if defined(CONFIG_TWL4030_POWER) 146 twl4030_power_mmc_init(); 147 mdelay(100); /* ramp-up delay from Linux code */ 148 #endif 149 #if defined(CONFIG_OMAP34XX) 150 writel(pbias_lite | PBIASLITEPWRDNZ1 | 151 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 152 &t2_base->pbias_lite); 153 154 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 155 &t2_base->devconf0); 156 157 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 158 &t2_base->devconf1); 159 160 /* Change from default of 52MHz to 26MHz if necessary */ 161 if (!(mmc->host_caps & MMC_MODE_HS_52MHz)) 162 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, 163 &t2_base->ctl_prog_io1); 164 165 writel(readl(&prcm_base->fclken1_core) | 166 EN_MMC1 | EN_MMC2 | EN_MMC3, 167 &prcm_base->fclken1_core); 168 169 writel(readl(&prcm_base->iclken1_core) | 170 EN_MMC1 | EN_MMC2 | EN_MMC3, 171 &prcm_base->iclken1_core); 172 #endif 173 174 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 175 /* PBIAS config needed for MMC1 only */ 176 if (mmc->block_dev.dev == 0) 177 omap4_vmmc_pbias_config(mmc); 178 #endif 179 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) 180 if (mmc->block_dev.dev == 0) 181 omap5_pbias_config(mmc); 182 #endif 183 184 return 0; 185 } 186 187 void mmc_init_stream(struct hsmmc *mmc_base) 188 { 189 ulong start; 190 191 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 192 193 writel(MMC_CMD0, &mmc_base->cmd); 194 start = get_timer(0); 195 while (!(readl(&mmc_base->stat) & CC_MASK)) { 196 if (get_timer(0) - start > MAX_RETRY_MS) { 197 printf("%s: timedout waiting for cc!\n", __func__); 198 return; 199 } 200 } 201 writel(CC_MASK, &mmc_base->stat) 202 ; 203 writel(MMC_CMD0, &mmc_base->cmd) 204 ; 205 start = get_timer(0); 206 while (!(readl(&mmc_base->stat) & CC_MASK)) { 207 if (get_timer(0) - start > MAX_RETRY_MS) { 208 printf("%s: timedout waiting for cc2!\n", __func__); 209 return; 210 } 211 } 212 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 213 } 214 215 216 static int mmc_init_setup(struct mmc *mmc) 217 { 218 struct hsmmc *mmc_base; 219 unsigned int reg_val; 220 unsigned int dsor; 221 ulong start; 222 223 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 224 mmc_board_init(mmc); 225 226 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 227 &mmc_base->sysconfig); 228 start = get_timer(0); 229 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 230 if (get_timer(0) - start > MAX_RETRY_MS) { 231 printf("%s: timedout waiting for cc2!\n", __func__); 232 return TIMEOUT; 233 } 234 } 235 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 236 start = get_timer(0); 237 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 238 if (get_timer(0) - start > MAX_RETRY_MS) { 239 printf("%s: timedout waiting for softresetall!\n", 240 __func__); 241 return TIMEOUT; 242 } 243 } 244 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 245 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 246 &mmc_base->capa); 247 248 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 249 250 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 251 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 252 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 253 254 dsor = 240; 255 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 256 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 257 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 258 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 259 start = get_timer(0); 260 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 261 if (get_timer(0) - start > MAX_RETRY_MS) { 262 printf("%s: timedout waiting for ics!\n", __func__); 263 return TIMEOUT; 264 } 265 } 266 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 267 268 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 269 270 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 271 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 272 &mmc_base->ie); 273 274 mmc_init_stream(mmc_base); 275 276 return 0; 277 } 278 279 /* 280 * MMC controller internal finite state machine reset 281 * 282 * Used to reset command or data internal state machines, using respectively 283 * SRC or SRD bit of SYSCTL register 284 */ 285 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) 286 { 287 ulong start; 288 289 mmc_reg_out(&mmc_base->sysctl, bit, bit); 290 291 /* 292 * CMD(DAT) lines reset procedures are slightly different 293 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). 294 * According to OMAP3 TRM: 295 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it 296 * returns to 0x0. 297 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset 298 * procedure steps must be as follows: 299 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in 300 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). 301 * 2. Poll the SRC(SRD) bit until it is set to 0x1. 302 * 3. Wait until the SRC (SRD) bit returns to 0x0 303 * (reset procedure is completed). 304 */ 305 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 306 defined(CONFIG_AM33XX) 307 if (!(readl(&mmc_base->sysctl) & bit)) { 308 start = get_timer(0); 309 while (!(readl(&mmc_base->sysctl) & bit)) { 310 if (get_timer(0) - start > MAX_RETRY_MS) 311 return; 312 } 313 } 314 #endif 315 start = get_timer(0); 316 while ((readl(&mmc_base->sysctl) & bit) != 0) { 317 if (get_timer(0) - start > MAX_RETRY_MS) { 318 printf("%s: timedout waiting for sysctl %x to clear\n", 319 __func__, bit); 320 return; 321 } 322 } 323 } 324 325 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 326 struct mmc_data *data) 327 { 328 struct hsmmc *mmc_base; 329 unsigned int flags, mmc_stat; 330 ulong start; 331 332 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 333 start = get_timer(0); 334 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { 335 if (get_timer(0) - start > MAX_RETRY_MS) { 336 printf("%s: timedout waiting on cmd inhibit to clear\n", 337 __func__); 338 return TIMEOUT; 339 } 340 } 341 writel(0xFFFFFFFF, &mmc_base->stat); 342 start = get_timer(0); 343 while (readl(&mmc_base->stat)) { 344 if (get_timer(0) - start > MAX_RETRY_MS) { 345 printf("%s: timedout waiting for STAT (%x) to clear\n", 346 __func__, readl(&mmc_base->stat)); 347 return TIMEOUT; 348 } 349 } 350 /* 351 * CMDREG 352 * CMDIDX[13:8] : Command index 353 * DATAPRNT[5] : Data Present Select 354 * ENCMDIDX[4] : Command Index Check Enable 355 * ENCMDCRC[3] : Command CRC Check Enable 356 * RSPTYP[1:0] 357 * 00 = No Response 358 * 01 = Length 136 359 * 10 = Length 48 360 * 11 = Length 48 Check busy after response 361 */ 362 /* Delay added before checking the status of frq change 363 * retry not supported by mmc.c(core file) 364 */ 365 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 366 udelay(50000); /* wait 50 ms */ 367 368 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 369 flags = 0; 370 else if (cmd->resp_type & MMC_RSP_136) 371 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 372 else if (cmd->resp_type & MMC_RSP_BUSY) 373 flags = RSP_TYPE_LGHT48B; 374 else 375 flags = RSP_TYPE_LGHT48; 376 377 /* enable default flags */ 378 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 379 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 380 381 if (cmd->resp_type & MMC_RSP_CRC) 382 flags |= CCCE_CHECK; 383 if (cmd->resp_type & MMC_RSP_OPCODE) 384 flags |= CICE_CHECK; 385 386 if (data) { 387 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 388 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 389 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 390 data->blocksize = 512; 391 writel(data->blocksize | (data->blocks << 16), 392 &mmc_base->blk); 393 } else 394 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 395 396 if (data->flags & MMC_DATA_READ) 397 flags |= (DP_DATA | DDIR_READ); 398 else 399 flags |= (DP_DATA | DDIR_WRITE); 400 } 401 402 writel(cmd->cmdarg, &mmc_base->arg); 403 udelay(20); /* To fix "No status update" error on eMMC */ 404 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 405 406 start = get_timer(0); 407 do { 408 mmc_stat = readl(&mmc_base->stat); 409 if (get_timer(0) - start > MAX_RETRY_MS) { 410 printf("%s : timeout: No status update\n", __func__); 411 return TIMEOUT; 412 } 413 } while (!mmc_stat); 414 415 if ((mmc_stat & IE_CTO) != 0) { 416 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); 417 return TIMEOUT; 418 } else if ((mmc_stat & ERRI_MASK) != 0) 419 return -1; 420 421 if (mmc_stat & CC_MASK) { 422 writel(CC_MASK, &mmc_base->stat); 423 if (cmd->resp_type & MMC_RSP_PRESENT) { 424 if (cmd->resp_type & MMC_RSP_136) { 425 /* response type 2 */ 426 cmd->response[3] = readl(&mmc_base->rsp10); 427 cmd->response[2] = readl(&mmc_base->rsp32); 428 cmd->response[1] = readl(&mmc_base->rsp54); 429 cmd->response[0] = readl(&mmc_base->rsp76); 430 } else 431 /* response types 1, 1b, 3, 4, 5, 6 */ 432 cmd->response[0] = readl(&mmc_base->rsp10); 433 } 434 } 435 436 if (data && (data->flags & MMC_DATA_READ)) { 437 mmc_read_data(mmc_base, data->dest, 438 data->blocksize * data->blocks); 439 } else if (data && (data->flags & MMC_DATA_WRITE)) { 440 mmc_write_data(mmc_base, data->src, 441 data->blocksize * data->blocks); 442 } 443 return 0; 444 } 445 446 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) 447 { 448 unsigned int *output_buf = (unsigned int *)buf; 449 unsigned int mmc_stat; 450 unsigned int count; 451 452 /* 453 * Start Polled Read 454 */ 455 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 456 count /= 4; 457 458 while (size) { 459 ulong start = get_timer(0); 460 do { 461 mmc_stat = readl(&mmc_base->stat); 462 if (get_timer(0) - start > MAX_RETRY_MS) { 463 printf("%s: timedout waiting for status!\n", 464 __func__); 465 return TIMEOUT; 466 } 467 } while (mmc_stat == 0); 468 469 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 470 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 471 472 if ((mmc_stat & ERRI_MASK) != 0) 473 return 1; 474 475 if (mmc_stat & BRR_MASK) { 476 unsigned int k; 477 478 writel(readl(&mmc_base->stat) | BRR_MASK, 479 &mmc_base->stat); 480 for (k = 0; k < count; k++) { 481 *output_buf = readl(&mmc_base->data); 482 output_buf++; 483 } 484 size -= (count*4); 485 } 486 487 if (mmc_stat & BWR_MASK) 488 writel(readl(&mmc_base->stat) | BWR_MASK, 489 &mmc_base->stat); 490 491 if (mmc_stat & TC_MASK) { 492 writel(readl(&mmc_base->stat) | TC_MASK, 493 &mmc_base->stat); 494 break; 495 } 496 } 497 return 0; 498 } 499 500 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, 501 unsigned int size) 502 { 503 unsigned int *input_buf = (unsigned int *)buf; 504 unsigned int mmc_stat; 505 unsigned int count; 506 507 /* 508 * Start Polled Write 509 */ 510 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 511 count /= 4; 512 513 while (size) { 514 ulong start = get_timer(0); 515 do { 516 mmc_stat = readl(&mmc_base->stat); 517 if (get_timer(0) - start > MAX_RETRY_MS) { 518 printf("%s: timedout waiting for status!\n", 519 __func__); 520 return TIMEOUT; 521 } 522 } while (mmc_stat == 0); 523 524 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) 525 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 526 527 if ((mmc_stat & ERRI_MASK) != 0) 528 return 1; 529 530 if (mmc_stat & BWR_MASK) { 531 unsigned int k; 532 533 writel(readl(&mmc_base->stat) | BWR_MASK, 534 &mmc_base->stat); 535 for (k = 0; k < count; k++) { 536 writel(*input_buf, &mmc_base->data); 537 input_buf++; 538 } 539 size -= (count*4); 540 } 541 542 if (mmc_stat & BRR_MASK) 543 writel(readl(&mmc_base->stat) | BRR_MASK, 544 &mmc_base->stat); 545 546 if (mmc_stat & TC_MASK) { 547 writel(readl(&mmc_base->stat) | TC_MASK, 548 &mmc_base->stat); 549 break; 550 } 551 } 552 return 0; 553 } 554 555 static void mmc_set_ios(struct mmc *mmc) 556 { 557 struct hsmmc *mmc_base; 558 unsigned int dsor = 0; 559 ulong start; 560 561 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 562 /* configue bus width */ 563 switch (mmc->bus_width) { 564 case 8: 565 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 566 &mmc_base->con); 567 break; 568 569 case 4: 570 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 571 &mmc_base->con); 572 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 573 &mmc_base->hctl); 574 break; 575 576 case 1: 577 default: 578 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 579 &mmc_base->con); 580 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 581 &mmc_base->hctl); 582 break; 583 } 584 585 /* configure clock with 96Mhz system clock. 586 */ 587 if (mmc->clock != 0) { 588 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 589 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 590 dsor++; 591 } 592 593 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 594 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 595 596 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 597 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 598 599 start = get_timer(0); 600 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 601 if (get_timer(0) - start > MAX_RETRY_MS) { 602 printf("%s: timedout waiting for ics!\n", __func__); 603 return; 604 } 605 } 606 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 607 } 608 609 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 610 int wp_gpio) 611 { 612 struct mmc *mmc = &hsmmc_dev[dev_index]; 613 struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index]; 614 uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | 615 MMC_MODE_HC; 616 617 sprintf(mmc->name, "OMAP SD/MMC"); 618 mmc->send_cmd = mmc_send_cmd; 619 mmc->set_ios = mmc_set_ios; 620 mmc->init = mmc_init_setup; 621 mmc->priv = priv_data; 622 623 switch (dev_index) { 624 case 0: 625 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 626 break; 627 #ifdef OMAP_HSMMC2_BASE 628 case 1: 629 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; 630 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ 631 defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT) 632 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ 633 host_caps_val |= MMC_MODE_8BIT; 634 #endif 635 break; 636 #endif 637 #ifdef OMAP_HSMMC3_BASE 638 case 2: 639 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; 640 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) 641 /* Enable 8-bit interface for eMMC on DRA7XX */ 642 host_caps_val |= MMC_MODE_8BIT; 643 #endif 644 break; 645 #endif 646 default: 647 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; 648 return 1; 649 } 650 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); 651 if (priv_data->cd_gpio != -1) 652 mmc->getcd = omap_mmc_getcd; 653 654 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); 655 if (priv_data->wp_gpio != -1) 656 mmc->getwp = omap_mmc_getwp; 657 658 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 659 mmc->host_caps = host_caps_val & ~host_caps_mask; 660 661 mmc->f_min = 400000; 662 663 if (f_max != 0) 664 mmc->f_max = f_max; 665 else { 666 if (mmc->host_caps & MMC_MODE_HS) { 667 if (mmc->host_caps & MMC_MODE_HS_52MHz) 668 mmc->f_max = 52000000; 669 else 670 mmc->f_max = 26000000; 671 } else 672 mmc->f_max = 20000000; 673 } 674 675 mmc->b_max = 0; 676 677 #if defined(CONFIG_OMAP34XX) 678 /* 679 * Silicon revs 2.1 and older do not support multiblock transfers. 680 */ 681 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 682 mmc->b_max = 1; 683 #endif 684 685 mmc_register(mmc); 686 687 return 0; 688 } 689