1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Sukumar Ghorai <s-ghorai@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <config.h> 26 #include <common.h> 27 #include <mmc.h> 28 #include <part.h> 29 #include <i2c.h> 30 #include <twl4030.h> 31 #include <twl6030.h> 32 #include <asm/io.h> 33 #include <asm/arch/mmc_host_def.h> 34 #include <asm/arch/sys_proto.h> 35 36 /* If we fail after 1 second wait, something is really bad */ 37 #define MAX_RETRY_MS 1000 38 39 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size); 40 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz); 41 static struct mmc hsmmc_dev[2]; 42 43 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 44 static void omap4_vmmc_pbias_config(struct mmc *mmc) 45 { 46 u32 value = 0; 47 struct omap4_sys_ctrl_regs *const ctrl = 48 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; 49 50 51 value = readl(&ctrl->control_pbiaslite); 52 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); 53 writel(value, &ctrl->control_pbiaslite); 54 /* set VMMC to 3V */ 55 twl6030_power_mmc_init(); 56 value = readl(&ctrl->control_pbiaslite); 57 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; 58 writel(value, &ctrl->control_pbiaslite); 59 } 60 #endif 61 62 unsigned char mmc_board_init(struct mmc *mmc) 63 { 64 #if defined(CONFIG_TWL4030_POWER) 65 twl4030_power_mmc_init(); 66 #endif 67 68 #if defined(CONFIG_OMAP34XX) 69 t2_t *t2_base = (t2_t *)T2_BASE; 70 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 71 72 writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | 73 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, 74 &t2_base->pbias_lite); 75 76 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, 77 &t2_base->devconf0); 78 79 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, 80 &t2_base->devconf1); 81 82 writel(readl(&prcm_base->fclken1_core) | 83 EN_MMC1 | EN_MMC2 | EN_MMC3, 84 &prcm_base->fclken1_core); 85 86 writel(readl(&prcm_base->iclken1_core) | 87 EN_MMC1 | EN_MMC2 | EN_MMC3, 88 &prcm_base->iclken1_core); 89 #endif 90 91 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) 92 /* PBIAS config needed for MMC1 only */ 93 if (mmc->block_dev.dev == 0) 94 omap4_vmmc_pbias_config(mmc); 95 #endif 96 97 return 0; 98 } 99 100 void mmc_init_stream(hsmmc_t *mmc_base) 101 { 102 ulong start; 103 104 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); 105 106 writel(MMC_CMD0, &mmc_base->cmd); 107 start = get_timer(0); 108 while (!(readl(&mmc_base->stat) & CC_MASK)) { 109 if (get_timer(0) - start > MAX_RETRY_MS) { 110 printf("%s: timedout waiting for cc!\n", __func__); 111 return; 112 } 113 } 114 writel(CC_MASK, &mmc_base->stat) 115 ; 116 writel(MMC_CMD0, &mmc_base->cmd) 117 ; 118 start = get_timer(0); 119 while (!(readl(&mmc_base->stat) & CC_MASK)) { 120 if (get_timer(0) - start > MAX_RETRY_MS) { 121 printf("%s: timedout waiting for cc2!\n", __func__); 122 return; 123 } 124 } 125 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 126 } 127 128 129 static int mmc_init_setup(struct mmc *mmc) 130 { 131 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 132 unsigned int reg_val; 133 unsigned int dsor; 134 ulong start; 135 136 mmc_board_init(mmc); 137 138 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 139 &mmc_base->sysconfig); 140 start = get_timer(0); 141 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { 142 if (get_timer(0) - start > MAX_RETRY_MS) { 143 printf("%s: timedout waiting for cc2!\n", __func__); 144 return TIMEOUT; 145 } 146 } 147 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); 148 start = get_timer(0); 149 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { 150 if (get_timer(0) - start > MAX_RETRY_MS) { 151 printf("%s: timedout waiting for softresetall!\n", 152 __func__); 153 return TIMEOUT; 154 } 155 } 156 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 157 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 158 &mmc_base->capa); 159 160 reg_val = readl(&mmc_base->con) & RESERVED_MASK; 161 162 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | 163 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | 164 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); 165 166 dsor = 240; 167 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 168 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 169 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 170 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 171 start = get_timer(0); 172 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 173 if (get_timer(0) - start > MAX_RETRY_MS) { 174 printf("%s: timedout waiting for ics!\n", __func__); 175 return TIMEOUT; 176 } 177 } 178 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 179 180 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); 181 182 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | 183 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, 184 &mmc_base->ie); 185 186 mmc_init_stream(mmc_base); 187 188 return 0; 189 } 190 191 192 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 193 struct mmc_data *data) 194 { 195 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 196 unsigned int flags, mmc_stat; 197 ulong start; 198 199 start = get_timer(0); 200 while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) { 201 if (get_timer(0) - start > MAX_RETRY_MS) { 202 printf("%s: timedout waiting for cmddis!\n", __func__); 203 return TIMEOUT; 204 } 205 } 206 writel(0xFFFFFFFF, &mmc_base->stat); 207 start = get_timer(0); 208 while (readl(&mmc_base->stat)) { 209 if (get_timer(0) - start > MAX_RETRY_MS) { 210 printf("%s: timedout waiting for stat!\n", __func__); 211 return TIMEOUT; 212 } 213 } 214 /* 215 * CMDREG 216 * CMDIDX[13:8] : Command index 217 * DATAPRNT[5] : Data Present Select 218 * ENCMDIDX[4] : Command Index Check Enable 219 * ENCMDCRC[3] : Command CRC Check Enable 220 * RSPTYP[1:0] 221 * 00 = No Response 222 * 01 = Length 136 223 * 10 = Length 48 224 * 11 = Length 48 Check busy after response 225 */ 226 /* Delay added before checking the status of frq change 227 * retry not supported by mmc.c(core file) 228 */ 229 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) 230 udelay(50000); /* wait 50 ms */ 231 232 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 233 flags = 0; 234 else if (cmd->resp_type & MMC_RSP_136) 235 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; 236 else if (cmd->resp_type & MMC_RSP_BUSY) 237 flags = RSP_TYPE_LGHT48B; 238 else 239 flags = RSP_TYPE_LGHT48; 240 241 /* enable default flags */ 242 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | 243 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); 244 245 if (cmd->resp_type & MMC_RSP_CRC) 246 flags |= CCCE_CHECK; 247 if (cmd->resp_type & MMC_RSP_OPCODE) 248 flags |= CICE_CHECK; 249 250 if (data) { 251 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || 252 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { 253 flags |= (MSBS_MULTIBLK | BCE_ENABLE); 254 data->blocksize = 512; 255 writel(data->blocksize | (data->blocks << 16), 256 &mmc_base->blk); 257 } else 258 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); 259 260 if (data->flags & MMC_DATA_READ) 261 flags |= (DP_DATA | DDIR_READ); 262 else 263 flags |= (DP_DATA | DDIR_WRITE); 264 } 265 266 writel(cmd->cmdarg, &mmc_base->arg); 267 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); 268 269 start = get_timer(0); 270 do { 271 mmc_stat = readl(&mmc_base->stat); 272 if (get_timer(0) - start > MAX_RETRY_MS) { 273 printf("%s : timeout: No status update\n", __func__); 274 return TIMEOUT; 275 } 276 } while (!mmc_stat); 277 278 if ((mmc_stat & IE_CTO) != 0) 279 return TIMEOUT; 280 else if ((mmc_stat & ERRI_MASK) != 0) 281 return -1; 282 283 if (mmc_stat & CC_MASK) { 284 writel(CC_MASK, &mmc_base->stat); 285 if (cmd->resp_type & MMC_RSP_PRESENT) { 286 if (cmd->resp_type & MMC_RSP_136) { 287 /* response type 2 */ 288 cmd->response[3] = readl(&mmc_base->rsp10); 289 cmd->response[2] = readl(&mmc_base->rsp32); 290 cmd->response[1] = readl(&mmc_base->rsp54); 291 cmd->response[0] = readl(&mmc_base->rsp76); 292 } else 293 /* response types 1, 1b, 3, 4, 5, 6 */ 294 cmd->response[0] = readl(&mmc_base->rsp10); 295 } 296 } 297 298 if (data && (data->flags & MMC_DATA_READ)) { 299 mmc_read_data(mmc_base, data->dest, 300 data->blocksize * data->blocks); 301 } else if (data && (data->flags & MMC_DATA_WRITE)) { 302 mmc_write_data(mmc_base, data->src, 303 data->blocksize * data->blocks); 304 } 305 return 0; 306 } 307 308 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size) 309 { 310 unsigned int *output_buf = (unsigned int *)buf; 311 unsigned int mmc_stat; 312 unsigned int count; 313 314 /* 315 * Start Polled Read 316 */ 317 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 318 count /= 4; 319 320 while (size) { 321 ulong start = get_timer(0); 322 do { 323 mmc_stat = readl(&mmc_base->stat); 324 if (get_timer(0) - start > MAX_RETRY_MS) { 325 printf("%s: timedout waiting for status!\n", 326 __func__); 327 return TIMEOUT; 328 } 329 } while (mmc_stat == 0); 330 331 if ((mmc_stat & ERRI_MASK) != 0) 332 return 1; 333 334 if (mmc_stat & BRR_MASK) { 335 unsigned int k; 336 337 writel(readl(&mmc_base->stat) | BRR_MASK, 338 &mmc_base->stat); 339 for (k = 0; k < count; k++) { 340 *output_buf = readl(&mmc_base->data); 341 output_buf++; 342 } 343 size -= (count*4); 344 } 345 346 if (mmc_stat & BWR_MASK) 347 writel(readl(&mmc_base->stat) | BWR_MASK, 348 &mmc_base->stat); 349 350 if (mmc_stat & TC_MASK) { 351 writel(readl(&mmc_base->stat) | TC_MASK, 352 &mmc_base->stat); 353 break; 354 } 355 } 356 return 0; 357 } 358 359 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size) 360 { 361 unsigned int *input_buf = (unsigned int *)buf; 362 unsigned int mmc_stat; 363 unsigned int count; 364 365 /* 366 * Start Polled Read 367 */ 368 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; 369 count /= 4; 370 371 while (size) { 372 ulong start = get_timer(0); 373 do { 374 mmc_stat = readl(&mmc_base->stat); 375 if (get_timer(0) - start > MAX_RETRY_MS) { 376 printf("%s: timedout waiting for status!\n", 377 __func__); 378 return TIMEOUT; 379 } 380 } while (mmc_stat == 0); 381 382 if ((mmc_stat & ERRI_MASK) != 0) 383 return 1; 384 385 if (mmc_stat & BWR_MASK) { 386 unsigned int k; 387 388 writel(readl(&mmc_base->stat) | BWR_MASK, 389 &mmc_base->stat); 390 for (k = 0; k < count; k++) { 391 writel(*input_buf, &mmc_base->data); 392 input_buf++; 393 } 394 size -= (count*4); 395 } 396 397 if (mmc_stat & BRR_MASK) 398 writel(readl(&mmc_base->stat) | BRR_MASK, 399 &mmc_base->stat); 400 401 if (mmc_stat & TC_MASK) { 402 writel(readl(&mmc_base->stat) | TC_MASK, 403 &mmc_base->stat); 404 break; 405 } 406 } 407 return 0; 408 } 409 410 static void mmc_set_ios(struct mmc *mmc) 411 { 412 hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; 413 unsigned int dsor = 0; 414 ulong start; 415 416 /* configue bus width */ 417 switch (mmc->bus_width) { 418 case 8: 419 writel(readl(&mmc_base->con) | DTW_8_BITMODE, 420 &mmc_base->con); 421 break; 422 423 case 4: 424 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 425 &mmc_base->con); 426 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, 427 &mmc_base->hctl); 428 break; 429 430 case 1: 431 default: 432 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, 433 &mmc_base->con); 434 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, 435 &mmc_base->hctl); 436 break; 437 } 438 439 /* configure clock with 96Mhz system clock. 440 */ 441 if (mmc->clock != 0) { 442 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); 443 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) 444 dsor++; 445 } 446 447 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), 448 (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); 449 450 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, 451 (dsor << CLKD_OFFSET) | ICE_OSCILLATE); 452 453 start = get_timer(0); 454 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { 455 if (get_timer(0) - start > MAX_RETRY_MS) { 456 printf("%s: timedout waiting for ics!\n", __func__); 457 return; 458 } 459 } 460 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); 461 } 462 463 int omap_mmc_init(int dev_index) 464 { 465 struct mmc *mmc; 466 467 mmc = &hsmmc_dev[dev_index]; 468 469 sprintf(mmc->name, "OMAP SD/MMC"); 470 mmc->send_cmd = mmc_send_cmd; 471 mmc->set_ios = mmc_set_ios; 472 mmc->init = mmc_init_setup; 473 474 switch (dev_index) { 475 case 0: 476 mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE; 477 break; 478 #ifdef OMAP_HSMMC2_BASE 479 case 1: 480 mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE; 481 break; 482 #endif 483 #ifdef OMAP_HSMMC3_BASE 484 case 2: 485 mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE; 486 break; 487 #endif 488 default: 489 mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE; 490 return 1; 491 } 492 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 493 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | 494 MMC_MODE_HC; 495 496 mmc->f_min = 400000; 497 mmc->f_max = 52000000; 498 499 mmc->b_max = 0; 500 501 #if defined(CONFIG_OMAP34XX) 502 /* 503 * Silicon revs 2.1 and older do not support multiblock transfers. 504 */ 505 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) 506 mmc->b_max = 1; 507 #endif 508 509 mmc_register(mmc); 510 511 return 0; 512 } 513