1 /* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9 * Terry Lv 10 * 11 * Copyright 2007, Freescale Semiconductor, Inc 12 * Andy Fleming 13 * 14 * Based vaguely on the pxa mmc code: 15 * (C) Copyright 2003 16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17 * 18 * See file CREDITS for list of people who contributed to this 19 * project. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License as 23 * published by the Free Software Foundation; either version 2 of 24 * the License, or (at your option) any later version. 25 * 26 * This program is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29 * GNU General Public License for more details. 30 * 31 * You should have received a copy of the GNU General Public License 32 * along with this program; if not, write to the Free Software 33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34 * MA 02111-1307 USA 35 */ 36 #include <common.h> 37 #include <malloc.h> 38 #include <mmc.h> 39 #include <asm/errno.h> 40 #include <asm/io.h> 41 #include <asm/arch/clock.h> 42 #include <asm/arch/imx-regs.h> 43 #include <asm/arch/sys_proto.h> 44 #include <asm/arch/dma.h> 45 #include <bouncebuf.h> 46 47 struct mxsmmc_priv { 48 int id; 49 struct mxs_ssp_regs *regs; 50 uint32_t buswidth; 51 int (*mmc_is_wp)(int); 52 int (*mmc_cd)(int); 53 struct mxs_dma_desc *desc; 54 }; 55 56 #if defined(CONFIG_MX23) 57 static const unsigned int mxsmmc_id_offset = 1; 58 #elif defined(CONFIG_MX28) 59 static const unsigned int mxsmmc_id_offset = 0; 60 #endif 61 62 #define MXSMMC_MAX_TIMEOUT 10000 63 #define MXSMMC_SMALL_TRANSFER 512 64 65 static int mxsmmc_cd(struct mxsmmc_priv *priv) 66 { 67 struct mxs_ssp_regs *ssp_regs = priv->regs; 68 69 if (priv->mmc_cd) 70 return priv->mmc_cd(priv->id); 71 72 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT); 73 } 74 75 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 76 { 77 struct mxs_ssp_regs *ssp_regs = priv->regs; 78 uint32_t *data_ptr; 79 int timeout = MXSMMC_MAX_TIMEOUT; 80 uint32_t reg; 81 uint32_t data_count = data->blocksize * data->blocks; 82 83 if (data->flags & MMC_DATA_READ) { 84 data_ptr = (uint32_t *)data->dest; 85 while (data_count && --timeout) { 86 reg = readl(&ssp_regs->hw_ssp_status); 87 if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 88 *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 89 data_count -= 4; 90 timeout = MXSMMC_MAX_TIMEOUT; 91 } else 92 udelay(1000); 93 } 94 } else { 95 data_ptr = (uint32_t *)data->src; 96 timeout *= 100; 97 while (data_count && --timeout) { 98 reg = readl(&ssp_regs->hw_ssp_status); 99 if (!(reg & SSP_STATUS_FIFO_FULL)) { 100 writel(*data_ptr++, &ssp_regs->hw_ssp_data); 101 data_count -= 4; 102 timeout = MXSMMC_MAX_TIMEOUT; 103 } else 104 udelay(1000); 105 } 106 } 107 108 return timeout ? 0 : COMM_ERR; 109 } 110 111 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 112 { 113 uint32_t data_count = data->blocksize * data->blocks; 114 int dmach; 115 struct mxs_dma_desc *desc = priv->desc; 116 void *addr; 117 unsigned int flags; 118 struct bounce_buffer bbstate; 119 120 memset(desc, 0, sizeof(struct mxs_dma_desc)); 121 desc->address = (dma_addr_t)desc; 122 123 if (data->flags & MMC_DATA_READ) { 124 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 125 addr = data->dest; 126 flags = GEN_BB_WRITE; 127 } else { 128 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 129 addr = (void *)data->src; 130 flags = GEN_BB_READ; 131 } 132 133 bounce_buffer_start(&bbstate, addr, data_count, flags); 134 135 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer; 136 137 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 138 (data_count << MXS_DMA_DESC_BYTES_OFFSET); 139 140 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id + mxsmmc_id_offset; 141 mxs_dma_desc_append(dmach, priv->desc); 142 if (mxs_dma_go(dmach)) { 143 bounce_buffer_stop(&bbstate); 144 return COMM_ERR; 145 } 146 147 bounce_buffer_stop(&bbstate); 148 149 return 0; 150 } 151 152 /* 153 * Sends a command out on the bus. Takes the mmc pointer, 154 * a command pointer, and an optional data pointer. 155 */ 156 static int 157 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 158 { 159 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 160 struct mxs_ssp_regs *ssp_regs = priv->regs; 161 uint32_t reg; 162 int timeout; 163 uint32_t ctrl0; 164 int ret; 165 166 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 167 168 /* Check bus busy */ 169 timeout = MXSMMC_MAX_TIMEOUT; 170 while (--timeout) { 171 udelay(1000); 172 reg = readl(&ssp_regs->hw_ssp_status); 173 if (!(reg & 174 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 175 SSP_STATUS_CMD_BUSY))) { 176 break; 177 } 178 } 179 180 if (!timeout) { 181 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 182 return TIMEOUT; 183 } 184 185 /* See if card is present */ 186 if (!mxsmmc_cd(priv)) { 187 printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 188 return NO_CARD_ERR; 189 } 190 191 /* Start building CTRL0 contents */ 192 ctrl0 = priv->buswidth; 193 194 /* Set up command */ 195 if (!(cmd->resp_type & MMC_RSP_CRC)) 196 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 197 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 198 ctrl0 |= SSP_CTRL0_GET_RESP; 199 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 200 ctrl0 |= SSP_CTRL0_LONG_RESP; 201 202 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) 203 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 204 else 205 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 206 207 /* Command index */ 208 reg = readl(&ssp_regs->hw_ssp_cmd0); 209 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 210 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 211 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 212 reg |= SSP_CMD0_APPEND_8CYC; 213 writel(reg, &ssp_regs->hw_ssp_cmd0); 214 215 /* Command argument */ 216 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 217 218 /* Set up data */ 219 if (data) { 220 /* READ or WRITE */ 221 if (data->flags & MMC_DATA_READ) { 222 ctrl0 |= SSP_CTRL0_READ; 223 } else if (priv->mmc_is_wp && 224 priv->mmc_is_wp(mmc->block_dev.dev)) { 225 printf("MMC%d: Can not write a locked card!\n", 226 mmc->block_dev.dev); 227 return UNUSABLE_ERR; 228 } 229 230 ctrl0 |= SSP_CTRL0_DATA_XFER; 231 232 reg = data->blocksize * data->blocks; 233 #if defined(CONFIG_MX23) 234 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK; 235 236 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0, 237 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK, 238 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) | 239 ((ffs(data->blocksize) - 1) << 240 SSP_CMD0_BLOCK_SIZE_OFFSET)); 241 #elif defined(CONFIG_MX28) 242 writel(reg, &ssp_regs->hw_ssp_xfer_size); 243 244 reg = ((data->blocks - 1) << 245 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 246 ((ffs(data->blocksize) - 1) << 247 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 248 writel(reg, &ssp_regs->hw_ssp_block_size); 249 #endif 250 } 251 252 /* Kick off the command */ 253 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 254 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 255 256 /* Wait for the command to complete */ 257 timeout = MXSMMC_MAX_TIMEOUT; 258 while (--timeout) { 259 udelay(1000); 260 reg = readl(&ssp_regs->hw_ssp_status); 261 if (!(reg & SSP_STATUS_CMD_BUSY)) 262 break; 263 } 264 265 if (!timeout) { 266 printf("MMC%d: Command %d busy\n", 267 mmc->block_dev.dev, cmd->cmdidx); 268 return TIMEOUT; 269 } 270 271 /* Check command timeout */ 272 if (reg & SSP_STATUS_RESP_TIMEOUT) { 273 printf("MMC%d: Command %d timeout (status 0x%08x)\n", 274 mmc->block_dev.dev, cmd->cmdidx, reg); 275 return TIMEOUT; 276 } 277 278 /* Check command errors */ 279 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 280 printf("MMC%d: Command %d error (status 0x%08x)!\n", 281 mmc->block_dev.dev, cmd->cmdidx, reg); 282 return COMM_ERR; 283 } 284 285 /* Copy response to response buffer */ 286 if (cmd->resp_type & MMC_RSP_136) { 287 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 288 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 289 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 290 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 291 } else 292 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 293 294 /* Return if no data to process */ 295 if (!data) 296 return 0; 297 298 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { 299 ret = mxsmmc_send_cmd_pio(priv, data); 300 if (ret) { 301 printf("MMC%d: Data timeout with command %d " 302 "(status 0x%08x)!\n", 303 mmc->block_dev.dev, cmd->cmdidx, reg); 304 return ret; 305 } 306 } else { 307 ret = mxsmmc_send_cmd_dma(priv, data); 308 if (ret) { 309 printf("MMC%d: DMA transfer failed\n", 310 mmc->block_dev.dev); 311 return ret; 312 } 313 } 314 315 /* Check data errors */ 316 reg = readl(&ssp_regs->hw_ssp_status); 317 if (reg & 318 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 319 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 320 printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 321 mmc->block_dev.dev, cmd->cmdidx, reg); 322 return COMM_ERR; 323 } 324 325 return 0; 326 } 327 328 static void mxsmmc_set_ios(struct mmc *mmc) 329 { 330 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 331 struct mxs_ssp_regs *ssp_regs = priv->regs; 332 333 /* Set the clock speed */ 334 if (mmc->clock) 335 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000); 336 337 switch (mmc->bus_width) { 338 case 1: 339 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 340 break; 341 case 4: 342 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 343 break; 344 case 8: 345 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 346 break; 347 } 348 349 /* Set the bus width */ 350 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 351 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 352 353 debug("MMC%d: Set %d bits bus width\n", 354 mmc->block_dev.dev, mmc->bus_width); 355 } 356 357 static int mxsmmc_init(struct mmc *mmc) 358 { 359 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 360 struct mxs_ssp_regs *ssp_regs = priv->regs; 361 362 /* Reset SSP */ 363 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 364 365 /* Reconfigure the SSP block for MMC operation */ 366 writel(SSP_CTRL1_SSP_MODE_SD_MMC | 367 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | 368 SSP_CTRL1_DMA_ENABLE | 369 SSP_CTRL1_POLARITY | 370 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 371 SSP_CTRL1_DATA_CRC_IRQ_EN | 372 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 373 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 374 SSP_CTRL1_RESP_ERR_IRQ_EN, 375 &ssp_regs->hw_ssp_ctrl1_set); 376 377 /* Set initial bit clock 400 KHz */ 378 mxs_set_ssp_busclock(priv->id, 400); 379 380 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 381 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 382 udelay(200); 383 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 384 385 return 0; 386 } 387 388 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) 389 { 390 struct mmc *mmc = NULL; 391 struct mxsmmc_priv *priv = NULL; 392 int ret; 393 #if defined(CONFIG_MX23) 394 const unsigned int mxsmmc_max_id = 2; 395 const unsigned int mxsmmc_clk_id = 0; 396 #elif defined(CONFIG_MX28) 397 const unsigned int mxsmmc_max_id = 4; 398 const unsigned int mxsmmc_clk_id = id; 399 #endif 400 401 if (id >= mxsmmc_max_id) 402 return -ENODEV; 403 404 mmc = malloc(sizeof(struct mmc)); 405 if (!mmc) 406 return -ENOMEM; 407 408 priv = malloc(sizeof(struct mxsmmc_priv)); 409 if (!priv) { 410 free(mmc); 411 return -ENOMEM; 412 } 413 414 priv->desc = mxs_dma_desc_alloc(); 415 if (!priv->desc) { 416 free(priv); 417 free(mmc); 418 return -ENOMEM; 419 } 420 421 ret = mxs_dma_init_channel(id + mxsmmc_id_offset); 422 if (ret) 423 return ret; 424 425 priv->mmc_is_wp = wp; 426 priv->mmc_cd = cd; 427 priv->id = id; 428 priv->regs = mxs_ssp_regs_by_bus(id); 429 430 sprintf(mmc->name, "MXS MMC"); 431 mmc->send_cmd = mxsmmc_send_cmd; 432 mmc->set_ios = mxsmmc_set_ios; 433 mmc->init = mxsmmc_init; 434 mmc->getcd = NULL; 435 mmc->getwp = NULL; 436 mmc->priv = priv; 437 438 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 439 440 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 441 MMC_MODE_HS_52MHz | MMC_MODE_HS; 442 443 /* 444 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 445 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 446 * CLOCK_DIVIDE has to be an even value from 2 to 254, and 447 * CLOCK_RATE could be any integer from 0 to 255. 448 */ 449 mmc->f_min = 400000; 450 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; 451 mmc->b_max = 0x20; 452 453 mmc_register(mmc); 454 return 0; 455 } 456