1 /* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9 * Terry Lv 10 * 11 * Copyright 2007, Freescale Semiconductor, Inc 12 * Andy Fleming 13 * 14 * Based vaguely on the pxa mmc code: 15 * (C) Copyright 2003 16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17 * 18 * See file CREDITS for list of people who contributed to this 19 * project. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License as 23 * published by the Free Software Foundation; either version 2 of 24 * the License, or (at your option) any later version. 25 * 26 * This program is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29 * GNU General Public License for more details. 30 * 31 * You should have received a copy of the GNU General Public License 32 * along with this program; if not, write to the Free Software 33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34 * MA 02111-1307 USA 35 */ 36 #include <common.h> 37 #include <malloc.h> 38 #include <mmc.h> 39 #include <asm/errno.h> 40 #include <asm/io.h> 41 #include <asm/arch/clock.h> 42 #include <asm/arch/imx-regs.h> 43 #include <asm/arch/sys_proto.h> 44 45 struct mxsmmc_priv { 46 int id; 47 struct mx28_ssp_regs *regs; 48 uint32_t clkseq_bypass; 49 uint32_t *clkctrl_ssp; 50 uint32_t buswidth; 51 int (*mmc_is_wp)(int); 52 }; 53 54 #define MXSMMC_MAX_TIMEOUT 10000 55 56 /* 57 * Sends a command out on the bus. Takes the mmc pointer, 58 * a command pointer, and an optional data pointer. 59 */ 60 static int 61 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 62 { 63 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 64 struct mx28_ssp_regs *ssp_regs = priv->regs; 65 uint32_t reg; 66 int timeout; 67 uint32_t data_count; 68 uint32_t *data_ptr; 69 uint32_t ctrl0; 70 71 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 72 73 /* Check bus busy */ 74 timeout = MXSMMC_MAX_TIMEOUT; 75 while (--timeout) { 76 udelay(1000); 77 reg = readl(&ssp_regs->hw_ssp_status); 78 if (!(reg & 79 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 80 SSP_STATUS_CMD_BUSY))) { 81 break; 82 } 83 } 84 85 if (!timeout) { 86 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 87 return TIMEOUT; 88 } 89 90 /* See if card is present */ 91 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 92 printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 93 return NO_CARD_ERR; 94 } 95 96 /* Start building CTRL0 contents */ 97 ctrl0 = priv->buswidth; 98 99 /* Set up command */ 100 if (!(cmd->resp_type & MMC_RSP_CRC)) 101 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 102 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 103 ctrl0 |= SSP_CTRL0_GET_RESP; 104 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 105 ctrl0 |= SSP_CTRL0_LONG_RESP; 106 107 /* Command index */ 108 reg = readl(&ssp_regs->hw_ssp_cmd0); 109 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 110 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 111 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 112 reg |= SSP_CMD0_APPEND_8CYC; 113 writel(reg, &ssp_regs->hw_ssp_cmd0); 114 115 /* Command argument */ 116 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 117 118 /* Set up data */ 119 if (data) { 120 /* READ or WRITE */ 121 if (data->flags & MMC_DATA_READ) { 122 ctrl0 |= SSP_CTRL0_READ; 123 } else if (priv->mmc_is_wp(mmc->block_dev.dev)) { 124 printf("MMC%d: Can not write a locked card!\n", 125 mmc->block_dev.dev); 126 return UNUSABLE_ERR; 127 } 128 129 ctrl0 |= SSP_CTRL0_DATA_XFER; 130 reg = ((data->blocks - 1) << 131 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 132 ((ffs(data->blocksize) - 1) << 133 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 134 writel(reg, &ssp_regs->hw_ssp_block_size); 135 136 reg = data->blocksize * data->blocks; 137 writel(reg, &ssp_regs->hw_ssp_xfer_size); 138 } 139 140 /* Kick off the command */ 141 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 142 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 143 144 /* Wait for the command to complete */ 145 timeout = MXSMMC_MAX_TIMEOUT; 146 while (--timeout) { 147 udelay(1000); 148 reg = readl(&ssp_regs->hw_ssp_status); 149 if (!(reg & SSP_STATUS_CMD_BUSY)) 150 break; 151 } 152 153 if (!timeout) { 154 printf("MMC%d: Command %d busy\n", 155 mmc->block_dev.dev, cmd->cmdidx); 156 return TIMEOUT; 157 } 158 159 /* Check command timeout */ 160 if (reg & SSP_STATUS_RESP_TIMEOUT) { 161 printf("MMC%d: Command %d timeout (status 0x%08x)\n", 162 mmc->block_dev.dev, cmd->cmdidx, reg); 163 return TIMEOUT; 164 } 165 166 /* Check command errors */ 167 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 168 printf("MMC%d: Command %d error (status 0x%08x)!\n", 169 mmc->block_dev.dev, cmd->cmdidx, reg); 170 return COMM_ERR; 171 } 172 173 /* Copy response to response buffer */ 174 if (cmd->resp_type & MMC_RSP_136) { 175 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 176 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 177 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 178 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 179 } else 180 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 181 182 /* Return if no data to process */ 183 if (!data) 184 return 0; 185 186 /* Process the data */ 187 data_count = data->blocksize * data->blocks; 188 timeout = MXSMMC_MAX_TIMEOUT; 189 if (data->flags & MMC_DATA_READ) { 190 data_ptr = (uint32_t *)data->dest; 191 while (data_count && --timeout) { 192 reg = readl(&ssp_regs->hw_ssp_status); 193 if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 194 *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 195 data_count -= 4; 196 timeout = MXSMMC_MAX_TIMEOUT; 197 } else 198 udelay(1000); 199 } 200 } else { 201 data_ptr = (uint32_t *)data->src; 202 timeout *= 100; 203 while (data_count && --timeout) { 204 reg = readl(&ssp_regs->hw_ssp_status); 205 if (!(reg & SSP_STATUS_FIFO_FULL)) { 206 writel(*data_ptr++, &ssp_regs->hw_ssp_data); 207 data_count -= 4; 208 timeout = MXSMMC_MAX_TIMEOUT; 209 } else 210 udelay(1000); 211 } 212 } 213 214 if (!timeout) { 215 printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n", 216 mmc->block_dev.dev, cmd->cmdidx, reg); 217 return COMM_ERR; 218 } 219 220 /* Check data errors */ 221 reg = readl(&ssp_regs->hw_ssp_status); 222 if (reg & 223 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 224 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 225 printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 226 mmc->block_dev.dev, cmd->cmdidx, reg); 227 return COMM_ERR; 228 } 229 230 return 0; 231 } 232 233 static void mxsmmc_set_ios(struct mmc *mmc) 234 { 235 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 236 struct mx28_ssp_regs *ssp_regs = priv->regs; 237 238 /* Set the clock speed */ 239 if (mmc->clock) 240 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 241 242 switch (mmc->bus_width) { 243 case 1: 244 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 245 break; 246 case 4: 247 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 248 break; 249 case 8: 250 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 251 break; 252 } 253 254 /* Set the bus width */ 255 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 256 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 257 258 debug("MMC%d: Set %d bits bus width\n", 259 mmc->block_dev.dev, mmc->bus_width); 260 } 261 262 static int mxsmmc_init(struct mmc *mmc) 263 { 264 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 265 struct mx28_ssp_regs *ssp_regs = priv->regs; 266 267 /* Reset SSP */ 268 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 269 270 /* 8 bits word length in MMC mode */ 271 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 272 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK, 273 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 274 275 /* Set initial bit clock 400 KHz */ 276 mx28_set_ssp_busclock(priv->id, 400); 277 278 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 279 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 280 udelay(200); 281 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 282 283 return 0; 284 } 285 286 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 287 { 288 struct mx28_clkctrl_regs *clkctrl_regs = 289 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; 290 struct mmc *mmc = NULL; 291 struct mxsmmc_priv *priv = NULL; 292 293 mmc = malloc(sizeof(struct mmc)); 294 if (!mmc) 295 return -ENOMEM; 296 297 priv = malloc(sizeof(struct mxsmmc_priv)); 298 if (!priv) { 299 free(mmc); 300 return -ENOMEM; 301 } 302 303 priv->mmc_is_wp = wp; 304 priv->id = id; 305 switch (id) { 306 case 0: 307 priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE; 308 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 309 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 310 break; 311 case 1: 312 priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE; 313 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 314 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 315 break; 316 case 2: 317 priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE; 318 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 319 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 320 break; 321 case 3: 322 priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE; 323 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 324 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 325 break; 326 } 327 328 sprintf(mmc->name, "MXS MMC"); 329 mmc->send_cmd = mxsmmc_send_cmd; 330 mmc->set_ios = mxsmmc_set_ios; 331 mmc->init = mxsmmc_init; 332 mmc->getcd = NULL; 333 mmc->priv = priv; 334 335 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 336 337 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 338 MMC_MODE_HS_52MHz | MMC_MODE_HS; 339 340 /* 341 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 342 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 343 * CLOCK_DIVIDE has to be an even value from 2 to 254, and 344 * CLOCK_RATE could be any integer from 0 to 255. 345 */ 346 mmc->f_min = 400000; 347 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 348 mmc->b_max = 0; 349 350 mmc_register(mmc); 351 return 0; 352 } 353