1 /* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9 * Terry Lv 10 * 11 * Copyright 2007, Freescale Semiconductor, Inc 12 * Andy Fleming 13 * 14 * Based vaguely on the pxa mmc code: 15 * (C) Copyright 2003 16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17 * 18 * See file CREDITS for list of people who contributed to this 19 * project. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License as 23 * published by the Free Software Foundation; either version 2 of 24 * the License, or (at your option) any later version. 25 * 26 * This program is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29 * GNU General Public License for more details. 30 * 31 * You should have received a copy of the GNU General Public License 32 * along with this program; if not, write to the Free Software 33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34 * MA 02111-1307 USA 35 */ 36 #include <common.h> 37 #include <malloc.h> 38 #include <mmc.h> 39 #include <asm/errno.h> 40 #include <asm/io.h> 41 #include <asm/arch/clock.h> 42 #include <asm/arch/imx-regs.h> 43 #include <asm/arch/sys_proto.h> 44 #include <asm/arch/dma.h> 45 46 struct mxsmmc_priv { 47 int id; 48 struct mx28_ssp_regs *regs; 49 uint32_t clkseq_bypass; 50 uint32_t *clkctrl_ssp; 51 uint32_t buswidth; 52 int (*mmc_is_wp)(int); 53 struct mxs_dma_desc *desc; 54 }; 55 56 #define MXSMMC_MAX_TIMEOUT 10000 57 58 /* 59 * Sends a command out on the bus. Takes the mmc pointer, 60 * a command pointer, and an optional data pointer. 61 */ 62 static int 63 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 64 { 65 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 66 struct mx28_ssp_regs *ssp_regs = priv->regs; 67 uint32_t reg; 68 int timeout; 69 uint32_t data_count, cache_data_count; 70 uint32_t ctrl0; 71 72 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 73 74 /* Check bus busy */ 75 timeout = MXSMMC_MAX_TIMEOUT; 76 while (--timeout) { 77 udelay(1000); 78 reg = readl(&ssp_regs->hw_ssp_status); 79 if (!(reg & 80 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 81 SSP_STATUS_CMD_BUSY))) { 82 break; 83 } 84 } 85 86 if (!timeout) { 87 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 88 return TIMEOUT; 89 } 90 91 /* See if card is present */ 92 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 93 printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 94 return NO_CARD_ERR; 95 } 96 97 /* Start building CTRL0 contents */ 98 ctrl0 = priv->buswidth; 99 100 /* Set up command */ 101 if (!(cmd->resp_type & MMC_RSP_CRC)) 102 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 103 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 104 ctrl0 |= SSP_CTRL0_GET_RESP; 105 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 106 ctrl0 |= SSP_CTRL0_LONG_RESP; 107 108 /* Command index */ 109 reg = readl(&ssp_regs->hw_ssp_cmd0); 110 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 111 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 112 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 113 reg |= SSP_CMD0_APPEND_8CYC; 114 writel(reg, &ssp_regs->hw_ssp_cmd0); 115 116 /* Command argument */ 117 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 118 119 /* Set up data */ 120 if (data) { 121 /* READ or WRITE */ 122 if (data->flags & MMC_DATA_READ) { 123 ctrl0 |= SSP_CTRL0_READ; 124 } else if (priv->mmc_is_wp(mmc->block_dev.dev)) { 125 printf("MMC%d: Can not write a locked card!\n", 126 mmc->block_dev.dev); 127 return UNUSABLE_ERR; 128 } 129 130 ctrl0 |= SSP_CTRL0_DATA_XFER; 131 reg = ((data->blocks - 1) << 132 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 133 ((ffs(data->blocksize) - 1) << 134 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 135 writel(reg, &ssp_regs->hw_ssp_block_size); 136 137 reg = data->blocksize * data->blocks; 138 writel(reg, &ssp_regs->hw_ssp_xfer_size); 139 } 140 141 /* Kick off the command */ 142 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 143 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 144 145 /* Wait for the command to complete */ 146 timeout = MXSMMC_MAX_TIMEOUT; 147 while (--timeout) { 148 udelay(1000); 149 reg = readl(&ssp_regs->hw_ssp_status); 150 if (!(reg & SSP_STATUS_CMD_BUSY)) 151 break; 152 } 153 154 if (!timeout) { 155 printf("MMC%d: Command %d busy\n", 156 mmc->block_dev.dev, cmd->cmdidx); 157 return TIMEOUT; 158 } 159 160 /* Check command timeout */ 161 if (reg & SSP_STATUS_RESP_TIMEOUT) { 162 printf("MMC%d: Command %d timeout (status 0x%08x)\n", 163 mmc->block_dev.dev, cmd->cmdidx, reg); 164 return TIMEOUT; 165 } 166 167 /* Check command errors */ 168 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 169 printf("MMC%d: Command %d error (status 0x%08x)!\n", 170 mmc->block_dev.dev, cmd->cmdidx, reg); 171 return COMM_ERR; 172 } 173 174 /* Copy response to response buffer */ 175 if (cmd->resp_type & MMC_RSP_136) { 176 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 177 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 178 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 179 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 180 } else 181 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 182 183 /* Return if no data to process */ 184 if (!data) 185 return 0; 186 187 data_count = data->blocksize * data->blocks; 188 189 if (data_count % ARCH_DMA_MINALIGN) 190 cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); 191 else 192 cache_data_count = data_count; 193 194 if (data->flags & MMC_DATA_READ) { 195 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 196 priv->desc->cmd.address = (dma_addr_t)data->dest; 197 } else { 198 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 199 priv->desc->cmd.address = (dma_addr_t)data->src; 200 201 /* Flush data to DRAM so DMA can pick them up */ 202 flush_dcache_range((uint32_t)priv->desc->cmd.address, 203 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 204 } 205 206 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 207 (data_count << MXS_DMA_DESC_BYTES_OFFSET); 208 209 210 mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc); 211 if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) { 212 printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev); 213 return COMM_ERR; 214 } 215 216 /* The data arrived into DRAM, invalidate cache over them */ 217 if (data->flags & MMC_DATA_READ) { 218 invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 219 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 220 } 221 222 /* Check data errors */ 223 reg = readl(&ssp_regs->hw_ssp_status); 224 if (reg & 225 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 226 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 227 printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 228 mmc->block_dev.dev, cmd->cmdidx, reg); 229 return COMM_ERR; 230 } 231 232 return 0; 233 } 234 235 static void mxsmmc_set_ios(struct mmc *mmc) 236 { 237 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 238 struct mx28_ssp_regs *ssp_regs = priv->regs; 239 240 /* Set the clock speed */ 241 if (mmc->clock) 242 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 243 244 switch (mmc->bus_width) { 245 case 1: 246 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 247 break; 248 case 4: 249 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 250 break; 251 case 8: 252 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 253 break; 254 } 255 256 /* Set the bus width */ 257 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 258 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 259 260 debug("MMC%d: Set %d bits bus width\n", 261 mmc->block_dev.dev, mmc->bus_width); 262 } 263 264 static int mxsmmc_init(struct mmc *mmc) 265 { 266 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 267 struct mx28_ssp_regs *ssp_regs = priv->regs; 268 269 /* Reset SSP */ 270 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 271 272 /* 8 bits word length in MMC mode */ 273 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 274 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK, 275 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | 276 SSP_CTRL1_DMA_ENABLE); 277 278 /* Set initial bit clock 400 KHz */ 279 mx28_set_ssp_busclock(priv->id, 400); 280 281 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 282 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 283 udelay(200); 284 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 285 286 return 0; 287 } 288 289 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 290 { 291 struct mx28_clkctrl_regs *clkctrl_regs = 292 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; 293 struct mmc *mmc = NULL; 294 struct mxsmmc_priv *priv = NULL; 295 296 mmc = malloc(sizeof(struct mmc)); 297 if (!mmc) 298 return -ENOMEM; 299 300 priv = malloc(sizeof(struct mxsmmc_priv)); 301 if (!priv) { 302 free(mmc); 303 return -ENOMEM; 304 } 305 306 priv->desc = mxs_dma_desc_alloc(); 307 if (!priv->desc) { 308 free(priv); 309 free(mmc); 310 return -ENOMEM; 311 } 312 313 priv->mmc_is_wp = wp; 314 priv->id = id; 315 switch (id) { 316 case 0: 317 priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE; 318 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 319 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 320 break; 321 case 1: 322 priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE; 323 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 324 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 325 break; 326 case 2: 327 priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE; 328 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 329 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 330 break; 331 case 3: 332 priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE; 333 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 334 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 335 break; 336 } 337 338 sprintf(mmc->name, "MXS MMC"); 339 mmc->send_cmd = mxsmmc_send_cmd; 340 mmc->set_ios = mxsmmc_set_ios; 341 mmc->init = mxsmmc_init; 342 mmc->getcd = NULL; 343 mmc->priv = priv; 344 345 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 346 347 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 348 MMC_MODE_HS_52MHz | MMC_MODE_HS; 349 350 /* 351 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 352 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 353 * CLOCK_DIVIDE has to be an even value from 2 to 254, and 354 * CLOCK_RATE could be any integer from 0 to 255. 355 */ 356 mmc->f_min = 400000; 357 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 358 mmc->b_max = 0x40; 359 360 mmc_register(mmc); 361 return 0; 362 } 363