1 /* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9 * Terry Lv 10 * 11 * Copyright 2007, Freescale Semiconductor, Inc 12 * Andy Fleming 13 * 14 * Based vaguely on the pxa mmc code: 15 * (C) Copyright 2003 16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17 * 18 * See file CREDITS for list of people who contributed to this 19 * project. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License as 23 * published by the Free Software Foundation; either version 2 of 24 * the License, or (at your option) any later version. 25 * 26 * This program is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29 * GNU General Public License for more details. 30 * 31 * You should have received a copy of the GNU General Public License 32 * along with this program; if not, write to the Free Software 33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34 * MA 02111-1307 USA 35 */ 36 #include <common.h> 37 #include <malloc.h> 38 #include <mmc.h> 39 #include <asm/errno.h> 40 #include <asm/io.h> 41 #include <asm/arch/clock.h> 42 #include <asm/arch/imx-regs.h> 43 #include <asm/arch/sys_proto.h> 44 #include <asm/arch/dma.h> 45 46 struct mxsmmc_priv { 47 int id; 48 struct mxs_ssp_regs *regs; 49 uint32_t clkseq_bypass; 50 uint32_t *clkctrl_ssp; 51 uint32_t buswidth; 52 int (*mmc_is_wp)(int); 53 struct mxs_dma_desc *desc; 54 }; 55 56 #define MXSMMC_MAX_TIMEOUT 10000 57 #define MXSMMC_SMALL_TRANSFER 512 58 59 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 60 { 61 struct mxs_ssp_regs *ssp_regs = priv->regs; 62 uint32_t *data_ptr; 63 int timeout = MXSMMC_MAX_TIMEOUT; 64 uint32_t reg; 65 uint32_t data_count = data->blocksize * data->blocks; 66 67 if (data->flags & MMC_DATA_READ) { 68 data_ptr = (uint32_t *)data->dest; 69 while (data_count && --timeout) { 70 reg = readl(&ssp_regs->hw_ssp_status); 71 if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 72 *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 73 data_count -= 4; 74 timeout = MXSMMC_MAX_TIMEOUT; 75 } else 76 udelay(1000); 77 } 78 } else { 79 data_ptr = (uint32_t *)data->src; 80 timeout *= 100; 81 while (data_count && --timeout) { 82 reg = readl(&ssp_regs->hw_ssp_status); 83 if (!(reg & SSP_STATUS_FIFO_FULL)) { 84 writel(*data_ptr++, &ssp_regs->hw_ssp_data); 85 data_count -= 4; 86 timeout = MXSMMC_MAX_TIMEOUT; 87 } else 88 udelay(1000); 89 } 90 } 91 92 return timeout ? 0 : COMM_ERR; 93 } 94 95 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 96 { 97 uint32_t data_count = data->blocksize * data->blocks; 98 uint32_t cache_data_count; 99 int dmach; 100 struct mxs_dma_desc *desc = priv->desc; 101 102 memset(desc, 0, sizeof(struct mxs_dma_desc)); 103 desc->address = (dma_addr_t)desc; 104 105 if (data_count % ARCH_DMA_MINALIGN) 106 cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); 107 else 108 cache_data_count = data_count; 109 110 if (data->flags & MMC_DATA_READ) { 111 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 112 priv->desc->cmd.address = (dma_addr_t)data->dest; 113 } else { 114 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 115 priv->desc->cmd.address = (dma_addr_t)data->src; 116 117 /* Flush data to DRAM so DMA can pick them up */ 118 flush_dcache_range((uint32_t)priv->desc->cmd.address, 119 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 120 } 121 122 /* Invalidate the area, so no writeback into the RAM races with DMA */ 123 invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 124 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 125 126 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 127 (data_count << MXS_DMA_DESC_BYTES_OFFSET); 128 129 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; 130 mxs_dma_desc_append(dmach, priv->desc); 131 if (mxs_dma_go(dmach)) 132 return COMM_ERR; 133 134 /* The data arrived into DRAM, invalidate cache over them */ 135 if (data->flags & MMC_DATA_READ) { 136 invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 137 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 138 } 139 140 return 0; 141 } 142 143 /* 144 * Sends a command out on the bus. Takes the mmc pointer, 145 * a command pointer, and an optional data pointer. 146 */ 147 static int 148 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 149 { 150 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 151 struct mxs_ssp_regs *ssp_regs = priv->regs; 152 uint32_t reg; 153 int timeout; 154 uint32_t ctrl0; 155 int ret; 156 157 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 158 159 /* Check bus busy */ 160 timeout = MXSMMC_MAX_TIMEOUT; 161 while (--timeout) { 162 udelay(1000); 163 reg = readl(&ssp_regs->hw_ssp_status); 164 if (!(reg & 165 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 166 SSP_STATUS_CMD_BUSY))) { 167 break; 168 } 169 } 170 171 if (!timeout) { 172 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 173 return TIMEOUT; 174 } 175 176 /* See if card is present */ 177 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 178 printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 179 return NO_CARD_ERR; 180 } 181 182 /* Start building CTRL0 contents */ 183 ctrl0 = priv->buswidth; 184 185 /* Set up command */ 186 if (!(cmd->resp_type & MMC_RSP_CRC)) 187 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 188 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 189 ctrl0 |= SSP_CTRL0_GET_RESP; 190 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 191 ctrl0 |= SSP_CTRL0_LONG_RESP; 192 193 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) 194 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 195 else 196 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 197 198 /* Command index */ 199 reg = readl(&ssp_regs->hw_ssp_cmd0); 200 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 201 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 202 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 203 reg |= SSP_CMD0_APPEND_8CYC; 204 writel(reg, &ssp_regs->hw_ssp_cmd0); 205 206 /* Command argument */ 207 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 208 209 /* Set up data */ 210 if (data) { 211 /* READ or WRITE */ 212 if (data->flags & MMC_DATA_READ) { 213 ctrl0 |= SSP_CTRL0_READ; 214 } else if (priv->mmc_is_wp && 215 priv->mmc_is_wp(mmc->block_dev.dev)) { 216 printf("MMC%d: Can not write a locked card!\n", 217 mmc->block_dev.dev); 218 return UNUSABLE_ERR; 219 } 220 221 ctrl0 |= SSP_CTRL0_DATA_XFER; 222 reg = ((data->blocks - 1) << 223 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 224 ((ffs(data->blocksize) - 1) << 225 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 226 writel(reg, &ssp_regs->hw_ssp_block_size); 227 228 reg = data->blocksize * data->blocks; 229 writel(reg, &ssp_regs->hw_ssp_xfer_size); 230 } 231 232 /* Kick off the command */ 233 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 234 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 235 236 /* Wait for the command to complete */ 237 timeout = MXSMMC_MAX_TIMEOUT; 238 while (--timeout) { 239 udelay(1000); 240 reg = readl(&ssp_regs->hw_ssp_status); 241 if (!(reg & SSP_STATUS_CMD_BUSY)) 242 break; 243 } 244 245 if (!timeout) { 246 printf("MMC%d: Command %d busy\n", 247 mmc->block_dev.dev, cmd->cmdidx); 248 return TIMEOUT; 249 } 250 251 /* Check command timeout */ 252 if (reg & SSP_STATUS_RESP_TIMEOUT) { 253 printf("MMC%d: Command %d timeout (status 0x%08x)\n", 254 mmc->block_dev.dev, cmd->cmdidx, reg); 255 return TIMEOUT; 256 } 257 258 /* Check command errors */ 259 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 260 printf("MMC%d: Command %d error (status 0x%08x)!\n", 261 mmc->block_dev.dev, cmd->cmdidx, reg); 262 return COMM_ERR; 263 } 264 265 /* Copy response to response buffer */ 266 if (cmd->resp_type & MMC_RSP_136) { 267 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 268 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 269 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 270 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 271 } else 272 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 273 274 /* Return if no data to process */ 275 if (!data) 276 return 0; 277 278 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { 279 ret = mxsmmc_send_cmd_pio(priv, data); 280 if (ret) { 281 printf("MMC%d: Data timeout with command %d " 282 "(status 0x%08x)!\n", 283 mmc->block_dev.dev, cmd->cmdidx, reg); 284 return ret; 285 } 286 } else { 287 ret = mxsmmc_send_cmd_dma(priv, data); 288 if (ret) { 289 printf("MMC%d: DMA transfer failed\n", 290 mmc->block_dev.dev); 291 return ret; 292 } 293 } 294 295 /* Check data errors */ 296 reg = readl(&ssp_regs->hw_ssp_status); 297 if (reg & 298 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 299 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 300 printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 301 mmc->block_dev.dev, cmd->cmdidx, reg); 302 return COMM_ERR; 303 } 304 305 return 0; 306 } 307 308 static void mxsmmc_set_ios(struct mmc *mmc) 309 { 310 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 311 struct mxs_ssp_regs *ssp_regs = priv->regs; 312 313 /* Set the clock speed */ 314 if (mmc->clock) 315 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 316 317 switch (mmc->bus_width) { 318 case 1: 319 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 320 break; 321 case 4: 322 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 323 break; 324 case 8: 325 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 326 break; 327 } 328 329 /* Set the bus width */ 330 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 331 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 332 333 debug("MMC%d: Set %d bits bus width\n", 334 mmc->block_dev.dev, mmc->bus_width); 335 } 336 337 static int mxsmmc_init(struct mmc *mmc) 338 { 339 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 340 struct mxs_ssp_regs *ssp_regs = priv->regs; 341 342 /* Reset SSP */ 343 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 344 345 /* 8 bits word length in MMC mode */ 346 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 347 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | 348 SSP_CTRL1_DMA_ENABLE, 349 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 350 351 /* Set initial bit clock 400 KHz */ 352 mx28_set_ssp_busclock(priv->id, 400); 353 354 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 355 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 356 udelay(200); 357 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 358 359 return 0; 360 } 361 362 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 363 { 364 struct mxs_clkctrl_regs *clkctrl_regs = 365 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 366 struct mmc *mmc = NULL; 367 struct mxsmmc_priv *priv = NULL; 368 int ret; 369 370 mmc = malloc(sizeof(struct mmc)); 371 if (!mmc) 372 return -ENOMEM; 373 374 priv = malloc(sizeof(struct mxsmmc_priv)); 375 if (!priv) { 376 free(mmc); 377 return -ENOMEM; 378 } 379 380 priv->desc = mxs_dma_desc_alloc(); 381 if (!priv->desc) { 382 free(priv); 383 free(mmc); 384 return -ENOMEM; 385 } 386 387 ret = mxs_dma_init_channel(id); 388 if (ret) 389 return ret; 390 391 priv->mmc_is_wp = wp; 392 priv->id = id; 393 switch (id) { 394 case 0: 395 priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE; 396 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 397 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 398 break; 399 case 1: 400 priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE; 401 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 402 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 403 break; 404 case 2: 405 priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE; 406 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 407 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 408 break; 409 case 3: 410 priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE; 411 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 412 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 413 break; 414 } 415 416 sprintf(mmc->name, "MXS MMC"); 417 mmc->send_cmd = mxsmmc_send_cmd; 418 mmc->set_ios = mxsmmc_set_ios; 419 mmc->init = mxsmmc_init; 420 mmc->getcd = NULL; 421 mmc->priv = priv; 422 423 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 424 425 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 426 MMC_MODE_HS_52MHz | MMC_MODE_HS; 427 428 /* 429 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 430 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 431 * CLOCK_DIVIDE has to be an even value from 2 to 254, and 432 * CLOCK_RATE could be any integer from 0 to 255. 433 */ 434 mmc->f_min = 400000; 435 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 436 mmc->b_max = 0x20; 437 438 mmc_register(mmc); 439 return 0; 440 } 441