1 /* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9 * Terry Lv 10 * 11 * Copyright 2007, Freescale Semiconductor, Inc 12 * Andy Fleming 13 * 14 * Based vaguely on the pxa mmc code: 15 * (C) Copyright 2003 16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17 * 18 * See file CREDITS for list of people who contributed to this 19 * project. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License as 23 * published by the Free Software Foundation; either version 2 of 24 * the License, or (at your option) any later version. 25 * 26 * This program is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29 * GNU General Public License for more details. 30 * 31 * You should have received a copy of the GNU General Public License 32 * along with this program; if not, write to the Free Software 33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34 * MA 02111-1307 USA 35 */ 36 #include <common.h> 37 #include <malloc.h> 38 #include <mmc.h> 39 #include <asm/errno.h> 40 #include <asm/io.h> 41 #include <asm/arch/clock.h> 42 #include <asm/arch/imx-regs.h> 43 #include <asm/arch/sys_proto.h> 44 #include <asm/arch/dma.h> 45 #include <bouncebuf.h> 46 47 struct mxsmmc_priv { 48 int id; 49 struct mxs_ssp_regs *regs; 50 uint32_t buswidth; 51 int (*mmc_is_wp)(int); 52 struct mxs_dma_desc *desc; 53 }; 54 55 #define MXSMMC_MAX_TIMEOUT 10000 56 #define MXSMMC_SMALL_TRANSFER 512 57 58 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 59 { 60 struct mxs_ssp_regs *ssp_regs = priv->regs; 61 uint32_t *data_ptr; 62 int timeout = MXSMMC_MAX_TIMEOUT; 63 uint32_t reg; 64 uint32_t data_count = data->blocksize * data->blocks; 65 66 if (data->flags & MMC_DATA_READ) { 67 data_ptr = (uint32_t *)data->dest; 68 while (data_count && --timeout) { 69 reg = readl(&ssp_regs->hw_ssp_status); 70 if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 71 *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 72 data_count -= 4; 73 timeout = MXSMMC_MAX_TIMEOUT; 74 } else 75 udelay(1000); 76 } 77 } else { 78 data_ptr = (uint32_t *)data->src; 79 timeout *= 100; 80 while (data_count && --timeout) { 81 reg = readl(&ssp_regs->hw_ssp_status); 82 if (!(reg & SSP_STATUS_FIFO_FULL)) { 83 writel(*data_ptr++, &ssp_regs->hw_ssp_data); 84 data_count -= 4; 85 timeout = MXSMMC_MAX_TIMEOUT; 86 } else 87 udelay(1000); 88 } 89 } 90 91 return timeout ? 0 : COMM_ERR; 92 } 93 94 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 95 { 96 uint32_t data_count = data->blocksize * data->blocks; 97 int dmach; 98 struct mxs_dma_desc *desc = priv->desc; 99 void *addr; 100 unsigned int flags; 101 struct bounce_buffer bbstate; 102 103 memset(desc, 0, sizeof(struct mxs_dma_desc)); 104 desc->address = (dma_addr_t)desc; 105 106 if (data->flags & MMC_DATA_READ) { 107 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 108 addr = data->dest; 109 flags = GEN_BB_WRITE; 110 } else { 111 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 112 addr = (void *)data->src; 113 flags = GEN_BB_READ; 114 } 115 116 bounce_buffer_start(&bbstate, addr, data_count, flags); 117 118 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer; 119 120 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 121 (data_count << MXS_DMA_DESC_BYTES_OFFSET); 122 123 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; 124 mxs_dma_desc_append(dmach, priv->desc); 125 if (mxs_dma_go(dmach)) { 126 bounce_buffer_stop(&bbstate); 127 return COMM_ERR; 128 } 129 130 bounce_buffer_stop(&bbstate); 131 132 return 0; 133 } 134 135 /* 136 * Sends a command out on the bus. Takes the mmc pointer, 137 * a command pointer, and an optional data pointer. 138 */ 139 static int 140 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 141 { 142 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 143 struct mxs_ssp_regs *ssp_regs = priv->regs; 144 uint32_t reg; 145 int timeout; 146 uint32_t ctrl0; 147 int ret; 148 149 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 150 151 /* Check bus busy */ 152 timeout = MXSMMC_MAX_TIMEOUT; 153 while (--timeout) { 154 udelay(1000); 155 reg = readl(&ssp_regs->hw_ssp_status); 156 if (!(reg & 157 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 158 SSP_STATUS_CMD_BUSY))) { 159 break; 160 } 161 } 162 163 if (!timeout) { 164 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 165 return TIMEOUT; 166 } 167 168 /* See if card is present */ 169 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 170 printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 171 return NO_CARD_ERR; 172 } 173 174 /* Start building CTRL0 contents */ 175 ctrl0 = priv->buswidth; 176 177 /* Set up command */ 178 if (!(cmd->resp_type & MMC_RSP_CRC)) 179 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 180 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 181 ctrl0 |= SSP_CTRL0_GET_RESP; 182 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 183 ctrl0 |= SSP_CTRL0_LONG_RESP; 184 185 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) 186 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 187 else 188 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 189 190 /* Command index */ 191 reg = readl(&ssp_regs->hw_ssp_cmd0); 192 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 193 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 194 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 195 reg |= SSP_CMD0_APPEND_8CYC; 196 writel(reg, &ssp_regs->hw_ssp_cmd0); 197 198 /* Command argument */ 199 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 200 201 /* Set up data */ 202 if (data) { 203 /* READ or WRITE */ 204 if (data->flags & MMC_DATA_READ) { 205 ctrl0 |= SSP_CTRL0_READ; 206 } else if (priv->mmc_is_wp && 207 priv->mmc_is_wp(mmc->block_dev.dev)) { 208 printf("MMC%d: Can not write a locked card!\n", 209 mmc->block_dev.dev); 210 return UNUSABLE_ERR; 211 } 212 213 ctrl0 |= SSP_CTRL0_DATA_XFER; 214 reg = ((data->blocks - 1) << 215 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 216 ((ffs(data->blocksize) - 1) << 217 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 218 writel(reg, &ssp_regs->hw_ssp_block_size); 219 220 reg = data->blocksize * data->blocks; 221 writel(reg, &ssp_regs->hw_ssp_xfer_size); 222 } 223 224 /* Kick off the command */ 225 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 226 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 227 228 /* Wait for the command to complete */ 229 timeout = MXSMMC_MAX_TIMEOUT; 230 while (--timeout) { 231 udelay(1000); 232 reg = readl(&ssp_regs->hw_ssp_status); 233 if (!(reg & SSP_STATUS_CMD_BUSY)) 234 break; 235 } 236 237 if (!timeout) { 238 printf("MMC%d: Command %d busy\n", 239 mmc->block_dev.dev, cmd->cmdidx); 240 return TIMEOUT; 241 } 242 243 /* Check command timeout */ 244 if (reg & SSP_STATUS_RESP_TIMEOUT) { 245 printf("MMC%d: Command %d timeout (status 0x%08x)\n", 246 mmc->block_dev.dev, cmd->cmdidx, reg); 247 return TIMEOUT; 248 } 249 250 /* Check command errors */ 251 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 252 printf("MMC%d: Command %d error (status 0x%08x)!\n", 253 mmc->block_dev.dev, cmd->cmdidx, reg); 254 return COMM_ERR; 255 } 256 257 /* Copy response to response buffer */ 258 if (cmd->resp_type & MMC_RSP_136) { 259 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 260 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 261 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 262 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 263 } else 264 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 265 266 /* Return if no data to process */ 267 if (!data) 268 return 0; 269 270 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { 271 ret = mxsmmc_send_cmd_pio(priv, data); 272 if (ret) { 273 printf("MMC%d: Data timeout with command %d " 274 "(status 0x%08x)!\n", 275 mmc->block_dev.dev, cmd->cmdidx, reg); 276 return ret; 277 } 278 } else { 279 ret = mxsmmc_send_cmd_dma(priv, data); 280 if (ret) { 281 printf("MMC%d: DMA transfer failed\n", 282 mmc->block_dev.dev); 283 return ret; 284 } 285 } 286 287 /* Check data errors */ 288 reg = readl(&ssp_regs->hw_ssp_status); 289 if (reg & 290 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 291 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 292 printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 293 mmc->block_dev.dev, cmd->cmdidx, reg); 294 return COMM_ERR; 295 } 296 297 return 0; 298 } 299 300 static void mxsmmc_set_ios(struct mmc *mmc) 301 { 302 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 303 struct mxs_ssp_regs *ssp_regs = priv->regs; 304 305 /* Set the clock speed */ 306 if (mmc->clock) 307 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000); 308 309 switch (mmc->bus_width) { 310 case 1: 311 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 312 break; 313 case 4: 314 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 315 break; 316 case 8: 317 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 318 break; 319 } 320 321 /* Set the bus width */ 322 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 323 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 324 325 debug("MMC%d: Set %d bits bus width\n", 326 mmc->block_dev.dev, mmc->bus_width); 327 } 328 329 static int mxsmmc_init(struct mmc *mmc) 330 { 331 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 332 struct mxs_ssp_regs *ssp_regs = priv->regs; 333 334 /* Reset SSP */ 335 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 336 337 /* 8 bits word length in MMC mode */ 338 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 339 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | 340 SSP_CTRL1_DMA_ENABLE, 341 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 342 343 /* Set initial bit clock 400 KHz */ 344 mxs_set_ssp_busclock(priv->id, 400); 345 346 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 347 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 348 udelay(200); 349 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 350 351 return 0; 352 } 353 354 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 355 { 356 struct mmc *mmc = NULL; 357 struct mxsmmc_priv *priv = NULL; 358 int ret; 359 #if defined(CONFIG_MX23) 360 const unsigned int mxsmmc_max_id = 2; 361 const unsigned int mxsmmc_clk_id = 0; 362 #elif defined(CONFIG_MX28) 363 const unsigned int mxsmmc_max_id = 4; 364 const unsigned int mxsmmc_clk_id = id; 365 #endif 366 367 if (id >= mxsmmc_max_id) 368 return -ENODEV; 369 370 mmc = malloc(sizeof(struct mmc)); 371 if (!mmc) 372 return -ENOMEM; 373 374 priv = malloc(sizeof(struct mxsmmc_priv)); 375 if (!priv) { 376 free(mmc); 377 return -ENOMEM; 378 } 379 380 priv->desc = mxs_dma_desc_alloc(); 381 if (!priv->desc) { 382 free(priv); 383 free(mmc); 384 return -ENOMEM; 385 } 386 387 ret = mxs_dma_init_channel(id); 388 if (ret) 389 return ret; 390 391 priv->mmc_is_wp = wp; 392 priv->id = id; 393 priv->regs = mxs_ssp_regs_by_bus(id); 394 395 sprintf(mmc->name, "MXS MMC"); 396 mmc->send_cmd = mxsmmc_send_cmd; 397 mmc->set_ios = mxsmmc_set_ios; 398 mmc->init = mxsmmc_init; 399 mmc->getcd = NULL; 400 mmc->priv = priv; 401 402 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 403 404 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 405 MMC_MODE_HS_52MHz | MMC_MODE_HS; 406 407 /* 408 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 409 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 410 * CLOCK_DIVIDE has to be an even value from 2 to 254, and 411 * CLOCK_RATE could be any integer from 0 to 255. 412 */ 413 mmc->f_min = 400000; 414 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; 415 mmc->b_max = 0x20; 416 417 mmc_register(mmc); 418 return 0; 419 } 420