1 /* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9 * Terry Lv 10 * 11 * Copyright 2007, Freescale Semiconductor, Inc 12 * Andy Fleming 13 * 14 * Based vaguely on the pxa mmc code: 15 * (C) Copyright 2003 16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17 * 18 * See file CREDITS for list of people who contributed to this 19 * project. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License as 23 * published by the Free Software Foundation; either version 2 of 24 * the License, or (at your option) any later version. 25 * 26 * This program is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29 * GNU General Public License for more details. 30 * 31 * You should have received a copy of the GNU General Public License 32 * along with this program; if not, write to the Free Software 33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34 * MA 02111-1307 USA 35 */ 36 #include <common.h> 37 #include <malloc.h> 38 #include <mmc.h> 39 #include <asm/errno.h> 40 #include <asm/io.h> 41 #include <asm/arch/clock.h> 42 #include <asm/arch/imx-regs.h> 43 #include <asm/arch/sys_proto.h> 44 #include <asm/arch/dma.h> 45 #include <bouncebuf.h> 46 47 struct mxsmmc_priv { 48 int id; 49 struct mxs_ssp_regs *regs; 50 uint32_t clkseq_bypass; 51 uint32_t *clkctrl_ssp; 52 uint32_t buswidth; 53 int (*mmc_is_wp)(int); 54 struct mxs_dma_desc *desc; 55 }; 56 57 #define MXSMMC_MAX_TIMEOUT 10000 58 #define MXSMMC_SMALL_TRANSFER 512 59 60 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 61 { 62 struct mxs_ssp_regs *ssp_regs = priv->regs; 63 uint32_t *data_ptr; 64 int timeout = MXSMMC_MAX_TIMEOUT; 65 uint32_t reg; 66 uint32_t data_count = data->blocksize * data->blocks; 67 68 if (data->flags & MMC_DATA_READ) { 69 data_ptr = (uint32_t *)data->dest; 70 while (data_count && --timeout) { 71 reg = readl(&ssp_regs->hw_ssp_status); 72 if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 73 *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 74 data_count -= 4; 75 timeout = MXSMMC_MAX_TIMEOUT; 76 } else 77 udelay(1000); 78 } 79 } else { 80 data_ptr = (uint32_t *)data->src; 81 timeout *= 100; 82 while (data_count && --timeout) { 83 reg = readl(&ssp_regs->hw_ssp_status); 84 if (!(reg & SSP_STATUS_FIFO_FULL)) { 85 writel(*data_ptr++, &ssp_regs->hw_ssp_data); 86 data_count -= 4; 87 timeout = MXSMMC_MAX_TIMEOUT; 88 } else 89 udelay(1000); 90 } 91 } 92 93 return timeout ? 0 : COMM_ERR; 94 } 95 96 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 97 { 98 uint32_t data_count = data->blocksize * data->blocks; 99 uint32_t cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); 100 int dmach; 101 struct mxs_dma_desc *desc = priv->desc; 102 void *addr, *backup; 103 uint8_t flags; 104 105 memset(desc, 0, sizeof(struct mxs_dma_desc)); 106 desc->address = (dma_addr_t)desc; 107 108 if (data->flags & MMC_DATA_READ) { 109 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 110 addr = data->dest; 111 flags = GEN_BB_WRITE; 112 } else { 113 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 114 addr = (void *)data->src; 115 flags = GEN_BB_READ; 116 } 117 118 bounce_buffer_start(&addr, data_count, &backup, flags); 119 120 priv->desc->cmd.address = (dma_addr_t)addr; 121 122 if (data->flags & MMC_DATA_WRITE) { 123 /* Flush data to DRAM so DMA can pick them up */ 124 flush_dcache_range((uint32_t)addr, 125 (uint32_t)(addr) + cache_data_count); 126 } 127 128 /* Invalidate the area, so no writeback into the RAM races with DMA */ 129 invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 130 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 131 132 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 133 (data_count << MXS_DMA_DESC_BYTES_OFFSET); 134 135 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; 136 mxs_dma_desc_append(dmach, priv->desc); 137 if (mxs_dma_go(dmach)) { 138 bounce_buffer_stop(&addr, data_count, &backup, flags); 139 return COMM_ERR; 140 } 141 142 /* The data arrived into DRAM, invalidate cache over them */ 143 if (data->flags & MMC_DATA_READ) { 144 invalidate_dcache_range((uint32_t)addr, 145 (uint32_t)(addr) + cache_data_count); 146 } 147 148 bounce_buffer_stop(&addr, data_count, &backup, flags); 149 150 return 0; 151 } 152 153 /* 154 * Sends a command out on the bus. Takes the mmc pointer, 155 * a command pointer, and an optional data pointer. 156 */ 157 static int 158 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 159 { 160 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 161 struct mxs_ssp_regs *ssp_regs = priv->regs; 162 uint32_t reg; 163 int timeout; 164 uint32_t ctrl0; 165 int ret; 166 167 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 168 169 /* Check bus busy */ 170 timeout = MXSMMC_MAX_TIMEOUT; 171 while (--timeout) { 172 udelay(1000); 173 reg = readl(&ssp_regs->hw_ssp_status); 174 if (!(reg & 175 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 176 SSP_STATUS_CMD_BUSY))) { 177 break; 178 } 179 } 180 181 if (!timeout) { 182 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 183 return TIMEOUT; 184 } 185 186 /* See if card is present */ 187 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 188 printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 189 return NO_CARD_ERR; 190 } 191 192 /* Start building CTRL0 contents */ 193 ctrl0 = priv->buswidth; 194 195 /* Set up command */ 196 if (!(cmd->resp_type & MMC_RSP_CRC)) 197 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 198 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 199 ctrl0 |= SSP_CTRL0_GET_RESP; 200 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 201 ctrl0 |= SSP_CTRL0_LONG_RESP; 202 203 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) 204 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 205 else 206 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 207 208 /* Command index */ 209 reg = readl(&ssp_regs->hw_ssp_cmd0); 210 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 211 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 212 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 213 reg |= SSP_CMD0_APPEND_8CYC; 214 writel(reg, &ssp_regs->hw_ssp_cmd0); 215 216 /* Command argument */ 217 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 218 219 /* Set up data */ 220 if (data) { 221 /* READ or WRITE */ 222 if (data->flags & MMC_DATA_READ) { 223 ctrl0 |= SSP_CTRL0_READ; 224 } else if (priv->mmc_is_wp && 225 priv->mmc_is_wp(mmc->block_dev.dev)) { 226 printf("MMC%d: Can not write a locked card!\n", 227 mmc->block_dev.dev); 228 return UNUSABLE_ERR; 229 } 230 231 ctrl0 |= SSP_CTRL0_DATA_XFER; 232 reg = ((data->blocks - 1) << 233 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 234 ((ffs(data->blocksize) - 1) << 235 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 236 writel(reg, &ssp_regs->hw_ssp_block_size); 237 238 reg = data->blocksize * data->blocks; 239 writel(reg, &ssp_regs->hw_ssp_xfer_size); 240 } 241 242 /* Kick off the command */ 243 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 244 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 245 246 /* Wait for the command to complete */ 247 timeout = MXSMMC_MAX_TIMEOUT; 248 while (--timeout) { 249 udelay(1000); 250 reg = readl(&ssp_regs->hw_ssp_status); 251 if (!(reg & SSP_STATUS_CMD_BUSY)) 252 break; 253 } 254 255 if (!timeout) { 256 printf("MMC%d: Command %d busy\n", 257 mmc->block_dev.dev, cmd->cmdidx); 258 return TIMEOUT; 259 } 260 261 /* Check command timeout */ 262 if (reg & SSP_STATUS_RESP_TIMEOUT) { 263 printf("MMC%d: Command %d timeout (status 0x%08x)\n", 264 mmc->block_dev.dev, cmd->cmdidx, reg); 265 return TIMEOUT; 266 } 267 268 /* Check command errors */ 269 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 270 printf("MMC%d: Command %d error (status 0x%08x)!\n", 271 mmc->block_dev.dev, cmd->cmdidx, reg); 272 return COMM_ERR; 273 } 274 275 /* Copy response to response buffer */ 276 if (cmd->resp_type & MMC_RSP_136) { 277 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 278 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 279 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 280 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 281 } else 282 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 283 284 /* Return if no data to process */ 285 if (!data) 286 return 0; 287 288 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { 289 ret = mxsmmc_send_cmd_pio(priv, data); 290 if (ret) { 291 printf("MMC%d: Data timeout with command %d " 292 "(status 0x%08x)!\n", 293 mmc->block_dev.dev, cmd->cmdidx, reg); 294 return ret; 295 } 296 } else { 297 ret = mxsmmc_send_cmd_dma(priv, data); 298 if (ret) { 299 printf("MMC%d: DMA transfer failed\n", 300 mmc->block_dev.dev); 301 return ret; 302 } 303 } 304 305 /* Check data errors */ 306 reg = readl(&ssp_regs->hw_ssp_status); 307 if (reg & 308 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 309 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 310 printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 311 mmc->block_dev.dev, cmd->cmdidx, reg); 312 return COMM_ERR; 313 } 314 315 return 0; 316 } 317 318 static void mxsmmc_set_ios(struct mmc *mmc) 319 { 320 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 321 struct mxs_ssp_regs *ssp_regs = priv->regs; 322 323 /* Set the clock speed */ 324 if (mmc->clock) 325 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 326 327 switch (mmc->bus_width) { 328 case 1: 329 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 330 break; 331 case 4: 332 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 333 break; 334 case 8: 335 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 336 break; 337 } 338 339 /* Set the bus width */ 340 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 341 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 342 343 debug("MMC%d: Set %d bits bus width\n", 344 mmc->block_dev.dev, mmc->bus_width); 345 } 346 347 static int mxsmmc_init(struct mmc *mmc) 348 { 349 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 350 struct mxs_ssp_regs *ssp_regs = priv->regs; 351 352 /* Reset SSP */ 353 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 354 355 /* 8 bits word length in MMC mode */ 356 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 357 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | 358 SSP_CTRL1_DMA_ENABLE, 359 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 360 361 /* Set initial bit clock 400 KHz */ 362 mx28_set_ssp_busclock(priv->id, 400); 363 364 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 365 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 366 udelay(200); 367 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 368 369 return 0; 370 } 371 372 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 373 { 374 struct mxs_clkctrl_regs *clkctrl_regs = 375 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 376 struct mmc *mmc = NULL; 377 struct mxsmmc_priv *priv = NULL; 378 int ret; 379 380 mmc = malloc(sizeof(struct mmc)); 381 if (!mmc) 382 return -ENOMEM; 383 384 priv = malloc(sizeof(struct mxsmmc_priv)); 385 if (!priv) { 386 free(mmc); 387 return -ENOMEM; 388 } 389 390 priv->desc = mxs_dma_desc_alloc(); 391 if (!priv->desc) { 392 free(priv); 393 free(mmc); 394 return -ENOMEM; 395 } 396 397 ret = mxs_dma_init_channel(id); 398 if (ret) 399 return ret; 400 401 priv->mmc_is_wp = wp; 402 priv->id = id; 403 switch (id) { 404 case 0: 405 priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE; 406 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 407 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 408 break; 409 case 1: 410 priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE; 411 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 412 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 413 break; 414 case 2: 415 priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE; 416 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 417 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 418 break; 419 case 3: 420 priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE; 421 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 422 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 423 break; 424 } 425 426 sprintf(mmc->name, "MXS MMC"); 427 mmc->send_cmd = mxsmmc_send_cmd; 428 mmc->set_ios = mxsmmc_set_ios; 429 mmc->init = mxsmmc_init; 430 mmc->getcd = NULL; 431 mmc->priv = priv; 432 433 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 434 435 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 436 MMC_MODE_HS_52MHz | MMC_MODE_HS; 437 438 /* 439 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 440 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 441 * CLOCK_DIVIDE has to be an even value from 2 to 254, and 442 * CLOCK_RATE could be any integer from 0 to 255. 443 */ 444 mmc->f_min = 400000; 445 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 446 mmc->b_max = 0x20; 447 448 mmc_register(mmc); 449 return 0; 450 } 451