1 /* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9 * Terry Lv 10 * 11 * Copyright 2007, Freescale Semiconductor, Inc 12 * Andy Fleming 13 * 14 * Based vaguely on the pxa mmc code: 15 * (C) Copyright 2003 16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17 * 18 * See file CREDITS for list of people who contributed to this 19 * project. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License as 23 * published by the Free Software Foundation; either version 2 of 24 * the License, or (at your option) any later version. 25 * 26 * This program is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29 * GNU General Public License for more details. 30 * 31 * You should have received a copy of the GNU General Public License 32 * along with this program; if not, write to the Free Software 33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34 * MA 02111-1307 USA 35 */ 36 #include <common.h> 37 #include <malloc.h> 38 #include <mmc.h> 39 #include <asm/errno.h> 40 #include <asm/io.h> 41 #include <asm/arch/clock.h> 42 #include <asm/arch/imx-regs.h> 43 #include <asm/arch/sys_proto.h> 44 #include <asm/arch/dma.h> 45 46 /* 47 * CONFIG_MXS_MMC_DMA: This feature is highly experimental and has no 48 * performance benefit unless you operate the platform with 49 * data cache enabled. This is disabled by default, enable 50 * only if you know what you're doing. 51 */ 52 53 struct mxsmmc_priv { 54 int id; 55 struct mx28_ssp_regs *regs; 56 uint32_t clkseq_bypass; 57 uint32_t *clkctrl_ssp; 58 uint32_t buswidth; 59 int (*mmc_is_wp)(int); 60 struct mxs_dma_desc *desc; 61 }; 62 63 #define MXSMMC_MAX_TIMEOUT 10000 64 65 /* 66 * Sends a command out on the bus. Takes the mmc pointer, 67 * a command pointer, and an optional data pointer. 68 */ 69 static int 70 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 71 { 72 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 73 struct mx28_ssp_regs *ssp_regs = priv->regs; 74 uint32_t reg; 75 int timeout; 76 uint32_t data_count; 77 uint32_t ctrl0; 78 #ifndef CONFIG_MXS_MMC_DMA 79 uint32_t *data_ptr; 80 #else 81 uint32_t cache_data_count; 82 #endif 83 84 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 85 86 /* Check bus busy */ 87 timeout = MXSMMC_MAX_TIMEOUT; 88 while (--timeout) { 89 udelay(1000); 90 reg = readl(&ssp_regs->hw_ssp_status); 91 if (!(reg & 92 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 93 SSP_STATUS_CMD_BUSY))) { 94 break; 95 } 96 } 97 98 if (!timeout) { 99 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 100 return TIMEOUT; 101 } 102 103 /* See if card is present */ 104 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 105 printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 106 return NO_CARD_ERR; 107 } 108 109 /* Start building CTRL0 contents */ 110 ctrl0 = priv->buswidth; 111 112 /* Set up command */ 113 if (!(cmd->resp_type & MMC_RSP_CRC)) 114 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 115 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 116 ctrl0 |= SSP_CTRL0_GET_RESP; 117 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 118 ctrl0 |= SSP_CTRL0_LONG_RESP; 119 120 /* Command index */ 121 reg = readl(&ssp_regs->hw_ssp_cmd0); 122 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 123 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 124 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 125 reg |= SSP_CMD0_APPEND_8CYC; 126 writel(reg, &ssp_regs->hw_ssp_cmd0); 127 128 /* Command argument */ 129 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 130 131 /* Set up data */ 132 if (data) { 133 /* READ or WRITE */ 134 if (data->flags & MMC_DATA_READ) { 135 ctrl0 |= SSP_CTRL0_READ; 136 } else if (priv->mmc_is_wp(mmc->block_dev.dev)) { 137 printf("MMC%d: Can not write a locked card!\n", 138 mmc->block_dev.dev); 139 return UNUSABLE_ERR; 140 } 141 142 ctrl0 |= SSP_CTRL0_DATA_XFER; 143 reg = ((data->blocks - 1) << 144 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 145 ((ffs(data->blocksize) - 1) << 146 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 147 writel(reg, &ssp_regs->hw_ssp_block_size); 148 149 reg = data->blocksize * data->blocks; 150 writel(reg, &ssp_regs->hw_ssp_xfer_size); 151 } 152 153 /* Kick off the command */ 154 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 155 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 156 157 /* Wait for the command to complete */ 158 timeout = MXSMMC_MAX_TIMEOUT; 159 while (--timeout) { 160 udelay(1000); 161 reg = readl(&ssp_regs->hw_ssp_status); 162 if (!(reg & SSP_STATUS_CMD_BUSY)) 163 break; 164 } 165 166 if (!timeout) { 167 printf("MMC%d: Command %d busy\n", 168 mmc->block_dev.dev, cmd->cmdidx); 169 return TIMEOUT; 170 } 171 172 /* Check command timeout */ 173 if (reg & SSP_STATUS_RESP_TIMEOUT) { 174 printf("MMC%d: Command %d timeout (status 0x%08x)\n", 175 mmc->block_dev.dev, cmd->cmdidx, reg); 176 return TIMEOUT; 177 } 178 179 /* Check command errors */ 180 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 181 printf("MMC%d: Command %d error (status 0x%08x)!\n", 182 mmc->block_dev.dev, cmd->cmdidx, reg); 183 return COMM_ERR; 184 } 185 186 /* Copy response to response buffer */ 187 if (cmd->resp_type & MMC_RSP_136) { 188 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 189 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 190 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 191 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 192 } else 193 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 194 195 /* Return if no data to process */ 196 if (!data) 197 return 0; 198 199 data_count = data->blocksize * data->blocks; 200 timeout = MXSMMC_MAX_TIMEOUT; 201 202 #ifdef CONFIG_MXS_MMC_DMA 203 if (data_count % ARCH_DMA_MINALIGN) 204 cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); 205 else 206 cache_data_count = data_count; 207 208 if (data->flags & MMC_DATA_READ) { 209 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 210 priv->desc->cmd.address = (dma_addr_t)data->dest; 211 } else { 212 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 213 priv->desc->cmd.address = (dma_addr_t)data->src; 214 215 /* Flush data to DRAM so DMA can pick them up */ 216 flush_dcache_range((uint32_t)priv->desc->cmd.address, 217 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 218 } 219 220 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 221 (data_count << MXS_DMA_DESC_BYTES_OFFSET); 222 223 224 mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc); 225 if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) { 226 printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev); 227 return COMM_ERR; 228 } 229 230 /* The data arrived into DRAM, invalidate cache over them */ 231 if (data->flags & MMC_DATA_READ) { 232 invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 233 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 234 } 235 #else 236 if (data->flags & MMC_DATA_READ) { 237 data_ptr = (uint32_t *)data->dest; 238 while (data_count && --timeout) { 239 reg = readl(&ssp_regs->hw_ssp_status); 240 if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 241 *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 242 data_count -= 4; 243 timeout = MXSMMC_MAX_TIMEOUT; 244 } else 245 udelay(1000); 246 } 247 } else { 248 data_ptr = (uint32_t *)data->src; 249 timeout *= 100; 250 while (data_count && --timeout) { 251 reg = readl(&ssp_regs->hw_ssp_status); 252 if (!(reg & SSP_STATUS_FIFO_FULL)) { 253 writel(*data_ptr++, &ssp_regs->hw_ssp_data); 254 data_count -= 4; 255 timeout = MXSMMC_MAX_TIMEOUT; 256 } else 257 udelay(1000); 258 } 259 } 260 261 if (!timeout) { 262 printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n", 263 mmc->block_dev.dev, cmd->cmdidx, reg); 264 return COMM_ERR; 265 } 266 #endif 267 268 /* Check data errors */ 269 reg = readl(&ssp_regs->hw_ssp_status); 270 if (reg & 271 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 272 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 273 printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 274 mmc->block_dev.dev, cmd->cmdidx, reg); 275 return COMM_ERR; 276 } 277 278 return 0; 279 } 280 281 static void mxsmmc_set_ios(struct mmc *mmc) 282 { 283 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 284 struct mx28_ssp_regs *ssp_regs = priv->regs; 285 286 /* Set the clock speed */ 287 if (mmc->clock) 288 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 289 290 switch (mmc->bus_width) { 291 case 1: 292 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 293 break; 294 case 4: 295 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 296 break; 297 case 8: 298 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 299 break; 300 } 301 302 /* Set the bus width */ 303 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 304 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 305 306 debug("MMC%d: Set %d bits bus width\n", 307 mmc->block_dev.dev, mmc->bus_width); 308 } 309 310 static int mxsmmc_init(struct mmc *mmc) 311 { 312 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 313 struct mx28_ssp_regs *ssp_regs = priv->regs; 314 315 /* Reset SSP */ 316 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 317 318 /* 8 bits word length in MMC mode */ 319 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 320 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK, 321 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | 322 SSP_CTRL1_DMA_ENABLE); 323 324 /* Set initial bit clock 400 KHz */ 325 mx28_set_ssp_busclock(priv->id, 400); 326 327 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 328 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 329 udelay(200); 330 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 331 332 return 0; 333 } 334 335 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 336 { 337 struct mx28_clkctrl_regs *clkctrl_regs = 338 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; 339 struct mmc *mmc = NULL; 340 struct mxsmmc_priv *priv = NULL; 341 int ret; 342 343 mmc = malloc(sizeof(struct mmc)); 344 if (!mmc) 345 return -ENOMEM; 346 347 priv = malloc(sizeof(struct mxsmmc_priv)); 348 if (!priv) { 349 free(mmc); 350 return -ENOMEM; 351 } 352 353 priv->desc = mxs_dma_desc_alloc(); 354 if (!priv->desc) { 355 free(priv); 356 free(mmc); 357 return -ENOMEM; 358 } 359 360 ret = mxs_dma_init_channel(id); 361 if (ret) 362 return ret; 363 364 priv->mmc_is_wp = wp; 365 priv->id = id; 366 switch (id) { 367 case 0: 368 priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE; 369 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 370 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 371 break; 372 case 1: 373 priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE; 374 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 375 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 376 break; 377 case 2: 378 priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE; 379 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 380 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 381 break; 382 case 3: 383 priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE; 384 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 385 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 386 break; 387 } 388 389 sprintf(mmc->name, "MXS MMC"); 390 mmc->send_cmd = mxsmmc_send_cmd; 391 mmc->set_ios = mxsmmc_set_ios; 392 mmc->init = mxsmmc_init; 393 mmc->getcd = NULL; 394 mmc->priv = priv; 395 396 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 397 398 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 399 MMC_MODE_HS_52MHz | MMC_MODE_HS; 400 401 /* 402 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 403 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 404 * CLOCK_DIVIDE has to be an even value from 2 to 254, and 405 * CLOCK_RATE could be any integer from 0 to 255. 406 */ 407 mmc->f_min = 400000; 408 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 409 mmc->b_max = 0x40; 410 411 mmc_register(mmc); 412 return 0; 413 } 414