1 /* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9 * Terry Lv 10 * 11 * Copyright 2007, Freescale Semiconductor, Inc 12 * Andy Fleming 13 * 14 * Based vaguely on the pxa mmc code: 15 * (C) Copyright 2003 16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17 * 18 * See file CREDITS for list of people who contributed to this 19 * project. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License as 23 * published by the Free Software Foundation; either version 2 of 24 * the License, or (at your option) any later version. 25 * 26 * This program is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29 * GNU General Public License for more details. 30 * 31 * You should have received a copy of the GNU General Public License 32 * along with this program; if not, write to the Free Software 33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34 * MA 02111-1307 USA 35 */ 36 #include <common.h> 37 #include <malloc.h> 38 #include <mmc.h> 39 #include <asm/errno.h> 40 #include <asm/io.h> 41 #include <asm/arch/clock.h> 42 #include <asm/arch/imx-regs.h> 43 #include <asm/arch/sys_proto.h> 44 #include <asm/arch/dma.h> 45 46 struct mxsmmc_priv { 47 int id; 48 struct mxs_ssp_regs *regs; 49 uint32_t clkseq_bypass; 50 uint32_t *clkctrl_ssp; 51 uint32_t buswidth; 52 int (*mmc_is_wp)(int); 53 struct mxs_dma_desc *desc; 54 }; 55 56 #define MXSMMC_MAX_TIMEOUT 10000 57 #define MXSMMC_SMALL_TRANSFER 512 58 59 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 60 { 61 struct mxs_ssp_regs *ssp_regs = priv->regs; 62 uint32_t *data_ptr; 63 int timeout = MXSMMC_MAX_TIMEOUT; 64 uint32_t reg; 65 uint32_t data_count = data->blocksize * data->blocks; 66 67 if (data->flags & MMC_DATA_READ) { 68 data_ptr = (uint32_t *)data->dest; 69 while (data_count && --timeout) { 70 reg = readl(&ssp_regs->hw_ssp_status); 71 if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 72 *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 73 data_count -= 4; 74 timeout = MXSMMC_MAX_TIMEOUT; 75 } else 76 udelay(1000); 77 } 78 } else { 79 data_ptr = (uint32_t *)data->src; 80 timeout *= 100; 81 while (data_count && --timeout) { 82 reg = readl(&ssp_regs->hw_ssp_status); 83 if (!(reg & SSP_STATUS_FIFO_FULL)) { 84 writel(*data_ptr++, &ssp_regs->hw_ssp_data); 85 data_count -= 4; 86 timeout = MXSMMC_MAX_TIMEOUT; 87 } else 88 udelay(1000); 89 } 90 } 91 92 return timeout ? 0 : COMM_ERR; 93 } 94 95 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 96 { 97 uint32_t data_count = data->blocksize * data->blocks; 98 uint32_t cache_data_count; 99 int dmach; 100 struct mxs_dma_desc *desc = priv->desc; 101 102 memset(desc, 0, sizeof(struct mxs_dma_desc)); 103 desc->address = (dma_addr_t)desc; 104 105 if (data_count % ARCH_DMA_MINALIGN) 106 cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); 107 else 108 cache_data_count = data_count; 109 110 if (data->flags & MMC_DATA_READ) { 111 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 112 priv->desc->cmd.address = (dma_addr_t)data->dest; 113 } else { 114 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 115 priv->desc->cmd.address = (dma_addr_t)data->src; 116 117 /* Flush data to DRAM so DMA can pick them up */ 118 flush_dcache_range((uint32_t)priv->desc->cmd.address, 119 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 120 } 121 122 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 123 (data_count << MXS_DMA_DESC_BYTES_OFFSET); 124 125 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; 126 mxs_dma_desc_append(dmach, priv->desc); 127 if (mxs_dma_go(dmach)) 128 return COMM_ERR; 129 130 /* The data arrived into DRAM, invalidate cache over them */ 131 if (data->flags & MMC_DATA_READ) { 132 invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 133 (uint32_t)(priv->desc->cmd.address + cache_data_count)); 134 } 135 136 return 0; 137 } 138 139 /* 140 * Sends a command out on the bus. Takes the mmc pointer, 141 * a command pointer, and an optional data pointer. 142 */ 143 static int 144 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 145 { 146 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 147 struct mxs_ssp_regs *ssp_regs = priv->regs; 148 uint32_t reg; 149 int timeout; 150 uint32_t ctrl0; 151 int ret; 152 153 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 154 155 /* Check bus busy */ 156 timeout = MXSMMC_MAX_TIMEOUT; 157 while (--timeout) { 158 udelay(1000); 159 reg = readl(&ssp_regs->hw_ssp_status); 160 if (!(reg & 161 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 162 SSP_STATUS_CMD_BUSY))) { 163 break; 164 } 165 } 166 167 if (!timeout) { 168 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 169 return TIMEOUT; 170 } 171 172 /* See if card is present */ 173 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 174 printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 175 return NO_CARD_ERR; 176 } 177 178 /* Start building CTRL0 contents */ 179 ctrl0 = priv->buswidth; 180 181 /* Set up command */ 182 if (!(cmd->resp_type & MMC_RSP_CRC)) 183 ctrl0 |= SSP_CTRL0_IGNORE_CRC; 184 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 185 ctrl0 |= SSP_CTRL0_GET_RESP; 186 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 187 ctrl0 |= SSP_CTRL0_LONG_RESP; 188 189 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) 190 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 191 else 192 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 193 194 /* Command index */ 195 reg = readl(&ssp_regs->hw_ssp_cmd0); 196 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 197 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 198 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 199 reg |= SSP_CMD0_APPEND_8CYC; 200 writel(reg, &ssp_regs->hw_ssp_cmd0); 201 202 /* Command argument */ 203 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 204 205 /* Set up data */ 206 if (data) { 207 /* READ or WRITE */ 208 if (data->flags & MMC_DATA_READ) { 209 ctrl0 |= SSP_CTRL0_READ; 210 } else if (priv->mmc_is_wp && 211 priv->mmc_is_wp(mmc->block_dev.dev)) { 212 printf("MMC%d: Can not write a locked card!\n", 213 mmc->block_dev.dev); 214 return UNUSABLE_ERR; 215 } 216 217 ctrl0 |= SSP_CTRL0_DATA_XFER; 218 reg = ((data->blocks - 1) << 219 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 220 ((ffs(data->blocksize) - 1) << 221 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 222 writel(reg, &ssp_regs->hw_ssp_block_size); 223 224 reg = data->blocksize * data->blocks; 225 writel(reg, &ssp_regs->hw_ssp_xfer_size); 226 } 227 228 /* Kick off the command */ 229 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 230 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 231 232 /* Wait for the command to complete */ 233 timeout = MXSMMC_MAX_TIMEOUT; 234 while (--timeout) { 235 udelay(1000); 236 reg = readl(&ssp_regs->hw_ssp_status); 237 if (!(reg & SSP_STATUS_CMD_BUSY)) 238 break; 239 } 240 241 if (!timeout) { 242 printf("MMC%d: Command %d busy\n", 243 mmc->block_dev.dev, cmd->cmdidx); 244 return TIMEOUT; 245 } 246 247 /* Check command timeout */ 248 if (reg & SSP_STATUS_RESP_TIMEOUT) { 249 printf("MMC%d: Command %d timeout (status 0x%08x)\n", 250 mmc->block_dev.dev, cmd->cmdidx, reg); 251 return TIMEOUT; 252 } 253 254 /* Check command errors */ 255 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 256 printf("MMC%d: Command %d error (status 0x%08x)!\n", 257 mmc->block_dev.dev, cmd->cmdidx, reg); 258 return COMM_ERR; 259 } 260 261 /* Copy response to response buffer */ 262 if (cmd->resp_type & MMC_RSP_136) { 263 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 264 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 265 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 266 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 267 } else 268 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 269 270 /* Return if no data to process */ 271 if (!data) 272 return 0; 273 274 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { 275 ret = mxsmmc_send_cmd_pio(priv, data); 276 if (ret) { 277 printf("MMC%d: Data timeout with command %d " 278 "(status 0x%08x)!\n", 279 mmc->block_dev.dev, cmd->cmdidx, reg); 280 return ret; 281 } 282 } else { 283 ret = mxsmmc_send_cmd_dma(priv, data); 284 if (ret) { 285 printf("MMC%d: DMA transfer failed\n", 286 mmc->block_dev.dev); 287 return ret; 288 } 289 } 290 291 /* Check data errors */ 292 reg = readl(&ssp_regs->hw_ssp_status); 293 if (reg & 294 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 295 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 296 printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 297 mmc->block_dev.dev, cmd->cmdidx, reg); 298 return COMM_ERR; 299 } 300 301 return 0; 302 } 303 304 static void mxsmmc_set_ios(struct mmc *mmc) 305 { 306 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 307 struct mxs_ssp_regs *ssp_regs = priv->regs; 308 309 /* Set the clock speed */ 310 if (mmc->clock) 311 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 312 313 switch (mmc->bus_width) { 314 case 1: 315 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 316 break; 317 case 4: 318 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 319 break; 320 case 8: 321 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 322 break; 323 } 324 325 /* Set the bus width */ 326 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 327 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 328 329 debug("MMC%d: Set %d bits bus width\n", 330 mmc->block_dev.dev, mmc->bus_width); 331 } 332 333 static int mxsmmc_init(struct mmc *mmc) 334 { 335 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 336 struct mxs_ssp_regs *ssp_regs = priv->regs; 337 338 /* Reset SSP */ 339 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 340 341 /* 8 bits word length in MMC mode */ 342 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 343 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | 344 SSP_CTRL1_DMA_ENABLE, 345 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 346 347 /* Set initial bit clock 400 KHz */ 348 mx28_set_ssp_busclock(priv->id, 400); 349 350 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 351 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 352 udelay(200); 353 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 354 355 return 0; 356 } 357 358 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 359 { 360 struct mxs_clkctrl_regs *clkctrl_regs = 361 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 362 struct mmc *mmc = NULL; 363 struct mxsmmc_priv *priv = NULL; 364 int ret; 365 366 mmc = malloc(sizeof(struct mmc)); 367 if (!mmc) 368 return -ENOMEM; 369 370 priv = malloc(sizeof(struct mxsmmc_priv)); 371 if (!priv) { 372 free(mmc); 373 return -ENOMEM; 374 } 375 376 priv->desc = mxs_dma_desc_alloc(); 377 if (!priv->desc) { 378 free(priv); 379 free(mmc); 380 return -ENOMEM; 381 } 382 383 ret = mxs_dma_init_channel(id); 384 if (ret) 385 return ret; 386 387 priv->mmc_is_wp = wp; 388 priv->id = id; 389 switch (id) { 390 case 0: 391 priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE; 392 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 393 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 394 break; 395 case 1: 396 priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE; 397 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 398 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 399 break; 400 case 2: 401 priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE; 402 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 403 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 404 break; 405 case 3: 406 priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE; 407 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 408 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 409 break; 410 } 411 412 sprintf(mmc->name, "MXS MMC"); 413 mmc->send_cmd = mxsmmc_send_cmd; 414 mmc->set_ios = mxsmmc_set_ios; 415 mmc->init = mxsmmc_init; 416 mmc->getcd = NULL; 417 mmc->priv = priv; 418 419 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 420 421 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 422 MMC_MODE_HS_52MHz | MMC_MODE_HS; 423 424 /* 425 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 426 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 427 * CLOCK_DIVIDE has to be an even value from 2 to 254, and 428 * CLOCK_RATE could be any integer from 0 to 255. 429 */ 430 mmc->f_min = 400000; 431 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 432 mmc->b_max = 0x20; 433 434 mmc_register(mmc); 435 return 0; 436 } 437