171a758e1SMarek Vasut /* 271a758e1SMarek Vasut * Freescale i.MX28 SSP MMC driver 371a758e1SMarek Vasut * 471a758e1SMarek Vasut * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 571a758e1SMarek Vasut * on behalf of DENX Software Engineering GmbH 671a758e1SMarek Vasut * 771a758e1SMarek Vasut * Based on code from LTIB: 871a758e1SMarek Vasut * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 971a758e1SMarek Vasut * Terry Lv 1071a758e1SMarek Vasut * 1171a758e1SMarek Vasut * Copyright 2007, Freescale Semiconductor, Inc 1271a758e1SMarek Vasut * Andy Fleming 1371a758e1SMarek Vasut * 1471a758e1SMarek Vasut * Based vaguely on the pxa mmc code: 1571a758e1SMarek Vasut * (C) Copyright 2003 1671a758e1SMarek Vasut * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 1771a758e1SMarek Vasut * 1871a758e1SMarek Vasut * See file CREDITS for list of people who contributed to this 1971a758e1SMarek Vasut * project. 2071a758e1SMarek Vasut * 2171a758e1SMarek Vasut * This program is free software; you can redistribute it and/or 2271a758e1SMarek Vasut * modify it under the terms of the GNU General Public License as 2371a758e1SMarek Vasut * published by the Free Software Foundation; either version 2 of 2471a758e1SMarek Vasut * the License, or (at your option) any later version. 2571a758e1SMarek Vasut * 2671a758e1SMarek Vasut * This program is distributed in the hope that it will be useful, 2771a758e1SMarek Vasut * but WITHOUT ANY WARRANTY; without even the implied warranty of 2871a758e1SMarek Vasut * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2971a758e1SMarek Vasut * GNU General Public License for more details. 3071a758e1SMarek Vasut * 3171a758e1SMarek Vasut * You should have received a copy of the GNU General Public License 3271a758e1SMarek Vasut * along with this program; if not, write to the Free Software 3371a758e1SMarek Vasut * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 3471a758e1SMarek Vasut * MA 02111-1307 USA 3571a758e1SMarek Vasut */ 3671a758e1SMarek Vasut #include <common.h> 3771a758e1SMarek Vasut #include <malloc.h> 3871a758e1SMarek Vasut #include <mmc.h> 3971a758e1SMarek Vasut #include <asm/errno.h> 4071a758e1SMarek Vasut #include <asm/io.h> 4171a758e1SMarek Vasut #include <asm/arch/clock.h> 4271a758e1SMarek Vasut #include <asm/arch/imx-regs.h> 4371a758e1SMarek Vasut #include <asm/arch/sys_proto.h> 443687c415SMarek Vasut #include <asm/arch/dma.h> 4571a758e1SMarek Vasut 464cc76c60SMarek Vasut /* 474cc76c60SMarek Vasut * CONFIG_MXS_MMC_DMA: This feature is highly experimental and has no 484cc76c60SMarek Vasut * performance benefit unless you operate the platform with 494cc76c60SMarek Vasut * data cache enabled. This is disabled by default, enable 504cc76c60SMarek Vasut * only if you know what you're doing. 514cc76c60SMarek Vasut */ 524cc76c60SMarek Vasut 5371a758e1SMarek Vasut struct mxsmmc_priv { 5471a758e1SMarek Vasut int id; 559c471142SOtavio Salvador struct mxs_ssp_regs *regs; 5671a758e1SMarek Vasut uint32_t clkseq_bypass; 5771a758e1SMarek Vasut uint32_t *clkctrl_ssp; 5871a758e1SMarek Vasut uint32_t buswidth; 5971a758e1SMarek Vasut int (*mmc_is_wp)(int); 603687c415SMarek Vasut struct mxs_dma_desc *desc; 6171a758e1SMarek Vasut }; 6271a758e1SMarek Vasut 6371a758e1SMarek Vasut #define MXSMMC_MAX_TIMEOUT 10000 6471a758e1SMarek Vasut 65*86983328SMarek Vasut #ifndef CONFIG_MXS_MMC_DMA 66*86983328SMarek Vasut static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 67*86983328SMarek Vasut { 68*86983328SMarek Vasut struct mxs_ssp_regs *ssp_regs = priv->regs; 69*86983328SMarek Vasut uint32_t *data_ptr; 70*86983328SMarek Vasut int timeout = MXSMMC_MAX_TIMEOUT; 71*86983328SMarek Vasut uint32_t reg; 72*86983328SMarek Vasut uint32_t data_count = data->blocksize * data->blocks; 73*86983328SMarek Vasut 74*86983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 75*86983328SMarek Vasut data_ptr = (uint32_t *)data->dest; 76*86983328SMarek Vasut while (data_count && --timeout) { 77*86983328SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 78*86983328SMarek Vasut if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 79*86983328SMarek Vasut *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 80*86983328SMarek Vasut data_count -= 4; 81*86983328SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 82*86983328SMarek Vasut } else 83*86983328SMarek Vasut udelay(1000); 84*86983328SMarek Vasut } 85*86983328SMarek Vasut } else { 86*86983328SMarek Vasut data_ptr = (uint32_t *)data->src; 87*86983328SMarek Vasut timeout *= 100; 88*86983328SMarek Vasut while (data_count && --timeout) { 89*86983328SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 90*86983328SMarek Vasut if (!(reg & SSP_STATUS_FIFO_FULL)) { 91*86983328SMarek Vasut writel(*data_ptr++, &ssp_regs->hw_ssp_data); 92*86983328SMarek Vasut data_count -= 4; 93*86983328SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 94*86983328SMarek Vasut } else 95*86983328SMarek Vasut udelay(1000); 96*86983328SMarek Vasut } 97*86983328SMarek Vasut } 98*86983328SMarek Vasut 99*86983328SMarek Vasut return timeout ? 0 : COMM_ERR; 100*86983328SMarek Vasut } 101*86983328SMarek Vasut #else 102*86983328SMarek Vasut static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 103*86983328SMarek Vasut { 104*86983328SMarek Vasut uint32_t data_count = data->blocksize * data->blocks; 105*86983328SMarek Vasut uint32_t cache_data_count; 106*86983328SMarek Vasut int dmach; 107*86983328SMarek Vasut 108*86983328SMarek Vasut if (data_count % ARCH_DMA_MINALIGN) 109*86983328SMarek Vasut cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); 110*86983328SMarek Vasut else 111*86983328SMarek Vasut cache_data_count = data_count; 112*86983328SMarek Vasut 113*86983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 114*86983328SMarek Vasut priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 115*86983328SMarek Vasut priv->desc->cmd.address = (dma_addr_t)data->dest; 116*86983328SMarek Vasut } else { 117*86983328SMarek Vasut priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 118*86983328SMarek Vasut priv->desc->cmd.address = (dma_addr_t)data->src; 119*86983328SMarek Vasut 120*86983328SMarek Vasut /* Flush data to DRAM so DMA can pick them up */ 121*86983328SMarek Vasut flush_dcache_range((uint32_t)priv->desc->cmd.address, 122*86983328SMarek Vasut (uint32_t)(priv->desc->cmd.address + cache_data_count)); 123*86983328SMarek Vasut } 124*86983328SMarek Vasut 125*86983328SMarek Vasut priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 126*86983328SMarek Vasut (data_count << MXS_DMA_DESC_BYTES_OFFSET); 127*86983328SMarek Vasut 128*86983328SMarek Vasut 129*86983328SMarek Vasut dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; 130*86983328SMarek Vasut mxs_dma_desc_append(dmach, priv->desc); 131*86983328SMarek Vasut if (mxs_dma_go(dmach)) 132*86983328SMarek Vasut return COMM_ERR; 133*86983328SMarek Vasut 134*86983328SMarek Vasut /* The data arrived into DRAM, invalidate cache over them */ 135*86983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 136*86983328SMarek Vasut invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 137*86983328SMarek Vasut (uint32_t)(priv->desc->cmd.address + cache_data_count)); 138*86983328SMarek Vasut } 139*86983328SMarek Vasut 140*86983328SMarek Vasut return 0; 141*86983328SMarek Vasut } 142*86983328SMarek Vasut #endif 143*86983328SMarek Vasut 14471a758e1SMarek Vasut /* 14571a758e1SMarek Vasut * Sends a command out on the bus. Takes the mmc pointer, 14671a758e1SMarek Vasut * a command pointer, and an optional data pointer. 14771a758e1SMarek Vasut */ 14871a758e1SMarek Vasut static int 14971a758e1SMarek Vasut mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 15071a758e1SMarek Vasut { 15171a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 1529c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 15371a758e1SMarek Vasut uint32_t reg; 15471a758e1SMarek Vasut int timeout; 15571a758e1SMarek Vasut uint32_t ctrl0; 156*86983328SMarek Vasut int ret; 15771a758e1SMarek Vasut 15871a758e1SMarek Vasut debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 15971a758e1SMarek Vasut 16071a758e1SMarek Vasut /* Check bus busy */ 16171a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 16271a758e1SMarek Vasut while (--timeout) { 16371a758e1SMarek Vasut udelay(1000); 16471a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 16571a758e1SMarek Vasut if (!(reg & 16671a758e1SMarek Vasut (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 16771a758e1SMarek Vasut SSP_STATUS_CMD_BUSY))) { 16871a758e1SMarek Vasut break; 16971a758e1SMarek Vasut } 17071a758e1SMarek Vasut } 17171a758e1SMarek Vasut 17271a758e1SMarek Vasut if (!timeout) { 17371a758e1SMarek Vasut printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 17471a758e1SMarek Vasut return TIMEOUT; 17571a758e1SMarek Vasut } 17671a758e1SMarek Vasut 17771a758e1SMarek Vasut /* See if card is present */ 17871a758e1SMarek Vasut if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 17971a758e1SMarek Vasut printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 18071a758e1SMarek Vasut return NO_CARD_ERR; 18171a758e1SMarek Vasut } 18271a758e1SMarek Vasut 18371a758e1SMarek Vasut /* Start building CTRL0 contents */ 18471a758e1SMarek Vasut ctrl0 = priv->buswidth; 18571a758e1SMarek Vasut 18671a758e1SMarek Vasut /* Set up command */ 18771a758e1SMarek Vasut if (!(cmd->resp_type & MMC_RSP_CRC)) 18871a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_IGNORE_CRC; 18971a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 19071a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_GET_RESP; 19171a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 19271a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_LONG_RESP; 19371a758e1SMarek Vasut 19471a758e1SMarek Vasut /* Command index */ 19571a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_cmd0); 19671a758e1SMarek Vasut reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 19771a758e1SMarek Vasut reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 19871a758e1SMarek Vasut if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 19971a758e1SMarek Vasut reg |= SSP_CMD0_APPEND_8CYC; 20071a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_cmd0); 20171a758e1SMarek Vasut 20271a758e1SMarek Vasut /* Command argument */ 20371a758e1SMarek Vasut writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 20471a758e1SMarek Vasut 20571a758e1SMarek Vasut /* Set up data */ 20671a758e1SMarek Vasut if (data) { 20771a758e1SMarek Vasut /* READ or WRITE */ 20871a758e1SMarek Vasut if (data->flags & MMC_DATA_READ) { 20971a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_READ; 210c7527b70SMarek Vasut } else if (priv->mmc_is_wp && 211c7527b70SMarek Vasut priv->mmc_is_wp(mmc->block_dev.dev)) { 21271a758e1SMarek Vasut printf("MMC%d: Can not write a locked card!\n", 21371a758e1SMarek Vasut mmc->block_dev.dev); 21471a758e1SMarek Vasut return UNUSABLE_ERR; 21571a758e1SMarek Vasut } 21671a758e1SMarek Vasut 21771a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_DATA_XFER; 21871a758e1SMarek Vasut reg = ((data->blocks - 1) << 21971a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 22071a758e1SMarek Vasut ((ffs(data->blocksize) - 1) << 22171a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 22271a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_block_size); 22371a758e1SMarek Vasut 22471a758e1SMarek Vasut reg = data->blocksize * data->blocks; 22571a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_xfer_size); 22671a758e1SMarek Vasut } 22771a758e1SMarek Vasut 22871a758e1SMarek Vasut /* Kick off the command */ 22971a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 23071a758e1SMarek Vasut writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 23171a758e1SMarek Vasut 23271a758e1SMarek Vasut /* Wait for the command to complete */ 23371a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 23471a758e1SMarek Vasut while (--timeout) { 23571a758e1SMarek Vasut udelay(1000); 23671a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 23771a758e1SMarek Vasut if (!(reg & SSP_STATUS_CMD_BUSY)) 23871a758e1SMarek Vasut break; 23971a758e1SMarek Vasut } 24071a758e1SMarek Vasut 24171a758e1SMarek Vasut if (!timeout) { 24271a758e1SMarek Vasut printf("MMC%d: Command %d busy\n", 24371a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx); 24471a758e1SMarek Vasut return TIMEOUT; 24571a758e1SMarek Vasut } 24671a758e1SMarek Vasut 24771a758e1SMarek Vasut /* Check command timeout */ 24871a758e1SMarek Vasut if (reg & SSP_STATUS_RESP_TIMEOUT) { 24971a758e1SMarek Vasut printf("MMC%d: Command %d timeout (status 0x%08x)\n", 25071a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 25171a758e1SMarek Vasut return TIMEOUT; 25271a758e1SMarek Vasut } 25371a758e1SMarek Vasut 25471a758e1SMarek Vasut /* Check command errors */ 25571a758e1SMarek Vasut if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 25671a758e1SMarek Vasut printf("MMC%d: Command %d error (status 0x%08x)!\n", 25771a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 25871a758e1SMarek Vasut return COMM_ERR; 25971a758e1SMarek Vasut } 26071a758e1SMarek Vasut 26171a758e1SMarek Vasut /* Copy response to response buffer */ 26271a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) { 26371a758e1SMarek Vasut cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 26471a758e1SMarek Vasut cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 26571a758e1SMarek Vasut cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 26671a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 26771a758e1SMarek Vasut } else 26871a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 26971a758e1SMarek Vasut 27071a758e1SMarek Vasut /* Return if no data to process */ 27171a758e1SMarek Vasut if (!data) 27271a758e1SMarek Vasut return 0; 27371a758e1SMarek Vasut 2744cc76c60SMarek Vasut #ifdef CONFIG_MXS_MMC_DMA 275401650a1SMarek Vasut writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 276401650a1SMarek Vasut 277*86983328SMarek Vasut ret = mxsmmc_send_cmd_dma(priv, data); 278*86983328SMarek Vasut if (ret) { 2793687c415SMarek Vasut printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev); 280*86983328SMarek Vasut return ret; 2813687c415SMarek Vasut } 2824cc76c60SMarek Vasut #else 283401650a1SMarek Vasut writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 284401650a1SMarek Vasut 285*86983328SMarek Vasut ret = mxsmmc_send_cmd_pio(priv, data); 286*86983328SMarek Vasut if (ret) { 2874cc76c60SMarek Vasut printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n", 2884cc76c60SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 289*86983328SMarek Vasut return ret; 2904cc76c60SMarek Vasut } 2914cc76c60SMarek Vasut #endif 2923687c415SMarek Vasut 29371a758e1SMarek Vasut /* Check data errors */ 29471a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 29571a758e1SMarek Vasut if (reg & 29671a758e1SMarek Vasut (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 29771a758e1SMarek Vasut SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 29871a758e1SMarek Vasut printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 29971a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 30071a758e1SMarek Vasut return COMM_ERR; 30171a758e1SMarek Vasut } 30271a758e1SMarek Vasut 30371a758e1SMarek Vasut return 0; 30471a758e1SMarek Vasut } 30571a758e1SMarek Vasut 30671a758e1SMarek Vasut static void mxsmmc_set_ios(struct mmc *mmc) 30771a758e1SMarek Vasut { 30871a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 3099c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 31071a758e1SMarek Vasut 31171a758e1SMarek Vasut /* Set the clock speed */ 31271a758e1SMarek Vasut if (mmc->clock) 31371a758e1SMarek Vasut mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 31471a758e1SMarek Vasut 31571a758e1SMarek Vasut switch (mmc->bus_width) { 31671a758e1SMarek Vasut case 1: 31771a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 31871a758e1SMarek Vasut break; 31971a758e1SMarek Vasut case 4: 32071a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 32171a758e1SMarek Vasut break; 32271a758e1SMarek Vasut case 8: 32371a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 32471a758e1SMarek Vasut break; 32571a758e1SMarek Vasut } 32671a758e1SMarek Vasut 32771a758e1SMarek Vasut /* Set the bus width */ 32871a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 32971a758e1SMarek Vasut SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 33071a758e1SMarek Vasut 33171a758e1SMarek Vasut debug("MMC%d: Set %d bits bus width\n", 33271a758e1SMarek Vasut mmc->block_dev.dev, mmc->bus_width); 33371a758e1SMarek Vasut } 33471a758e1SMarek Vasut 33571a758e1SMarek Vasut static int mxsmmc_init(struct mmc *mmc) 33671a758e1SMarek Vasut { 33771a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 3389c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 33971a758e1SMarek Vasut 34071a758e1SMarek Vasut /* Reset SSP */ 34171a758e1SMarek Vasut mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 34271a758e1SMarek Vasut 34371a758e1SMarek Vasut /* 8 bits word length in MMC mode */ 34471a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 34571a758e1SMarek Vasut SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK, 3463687c415SMarek Vasut SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | 3473687c415SMarek Vasut SSP_CTRL1_DMA_ENABLE); 34871a758e1SMarek Vasut 34971a758e1SMarek Vasut /* Set initial bit clock 400 KHz */ 35071a758e1SMarek Vasut mx28_set_ssp_busclock(priv->id, 400); 35171a758e1SMarek Vasut 35271a758e1SMarek Vasut /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 35371a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 35471a758e1SMarek Vasut udelay(200); 35571a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 35671a758e1SMarek Vasut 35771a758e1SMarek Vasut return 0; 35871a758e1SMarek Vasut } 35971a758e1SMarek Vasut 36071a758e1SMarek Vasut int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 36171a758e1SMarek Vasut { 3629c471142SOtavio Salvador struct mxs_clkctrl_regs *clkctrl_regs = 3639c471142SOtavio Salvador (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 36471a758e1SMarek Vasut struct mmc *mmc = NULL; 36571a758e1SMarek Vasut struct mxsmmc_priv *priv = NULL; 36696666a39SMarek Vasut int ret; 36771a758e1SMarek Vasut 36871a758e1SMarek Vasut mmc = malloc(sizeof(struct mmc)); 36971a758e1SMarek Vasut if (!mmc) 37071a758e1SMarek Vasut return -ENOMEM; 37171a758e1SMarek Vasut 37271a758e1SMarek Vasut priv = malloc(sizeof(struct mxsmmc_priv)); 37371a758e1SMarek Vasut if (!priv) { 37471a758e1SMarek Vasut free(mmc); 37571a758e1SMarek Vasut return -ENOMEM; 37671a758e1SMarek Vasut } 37771a758e1SMarek Vasut 3783687c415SMarek Vasut priv->desc = mxs_dma_desc_alloc(); 3793687c415SMarek Vasut if (!priv->desc) { 3803687c415SMarek Vasut free(priv); 3813687c415SMarek Vasut free(mmc); 3823687c415SMarek Vasut return -ENOMEM; 3833687c415SMarek Vasut } 3843687c415SMarek Vasut 38596666a39SMarek Vasut ret = mxs_dma_init_channel(id); 38696666a39SMarek Vasut if (ret) 38796666a39SMarek Vasut return ret; 38896666a39SMarek Vasut 38971a758e1SMarek Vasut priv->mmc_is_wp = wp; 39071a758e1SMarek Vasut priv->id = id; 39171a758e1SMarek Vasut switch (id) { 39271a758e1SMarek Vasut case 0: 3939c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE; 39471a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 39571a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 39671a758e1SMarek Vasut break; 39771a758e1SMarek Vasut case 1: 3989c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE; 39971a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 40071a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 40171a758e1SMarek Vasut break; 40271a758e1SMarek Vasut case 2: 4039c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE; 40471a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 40571a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 40671a758e1SMarek Vasut break; 40771a758e1SMarek Vasut case 3: 4089c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE; 40971a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 41071a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 41171a758e1SMarek Vasut break; 41271a758e1SMarek Vasut } 41371a758e1SMarek Vasut 41471a758e1SMarek Vasut sprintf(mmc->name, "MXS MMC"); 41571a758e1SMarek Vasut mmc->send_cmd = mxsmmc_send_cmd; 41671a758e1SMarek Vasut mmc->set_ios = mxsmmc_set_ios; 41771a758e1SMarek Vasut mmc->init = mxsmmc_init; 41848972d90SThierry Reding mmc->getcd = NULL; 41971a758e1SMarek Vasut mmc->priv = priv; 42071a758e1SMarek Vasut 42171a758e1SMarek Vasut mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 42271a758e1SMarek Vasut 42371a758e1SMarek Vasut mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 42471a758e1SMarek Vasut MMC_MODE_HS_52MHz | MMC_MODE_HS; 42571a758e1SMarek Vasut 42671a758e1SMarek Vasut /* 42771a758e1SMarek Vasut * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 42871a758e1SMarek Vasut * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 42971a758e1SMarek Vasut * CLOCK_DIVIDE has to be an even value from 2 to 254, and 43071a758e1SMarek Vasut * CLOCK_RATE could be any integer from 0 to 255. 43171a758e1SMarek Vasut */ 43271a758e1SMarek Vasut mmc->f_min = 400000; 43371a758e1SMarek Vasut mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 434e7205905SMarek Vasut mmc->b_max = 0x20; 43571a758e1SMarek Vasut 43671a758e1SMarek Vasut mmc_register(mmc); 43771a758e1SMarek Vasut return 0; 43871a758e1SMarek Vasut } 439