1*71a758e1SMarek Vasut /* 2*71a758e1SMarek Vasut * Freescale i.MX28 SSP MMC driver 3*71a758e1SMarek Vasut * 4*71a758e1SMarek Vasut * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5*71a758e1SMarek Vasut * on behalf of DENX Software Engineering GmbH 6*71a758e1SMarek Vasut * 7*71a758e1SMarek Vasut * Based on code from LTIB: 8*71a758e1SMarek Vasut * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 9*71a758e1SMarek Vasut * Terry Lv 10*71a758e1SMarek Vasut * 11*71a758e1SMarek Vasut * Copyright 2007, Freescale Semiconductor, Inc 12*71a758e1SMarek Vasut * Andy Fleming 13*71a758e1SMarek Vasut * 14*71a758e1SMarek Vasut * Based vaguely on the pxa mmc code: 15*71a758e1SMarek Vasut * (C) Copyright 2003 16*71a758e1SMarek Vasut * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 17*71a758e1SMarek Vasut * 18*71a758e1SMarek Vasut * See file CREDITS for list of people who contributed to this 19*71a758e1SMarek Vasut * project. 20*71a758e1SMarek Vasut * 21*71a758e1SMarek Vasut * This program is free software; you can redistribute it and/or 22*71a758e1SMarek Vasut * modify it under the terms of the GNU General Public License as 23*71a758e1SMarek Vasut * published by the Free Software Foundation; either version 2 of 24*71a758e1SMarek Vasut * the License, or (at your option) any later version. 25*71a758e1SMarek Vasut * 26*71a758e1SMarek Vasut * This program is distributed in the hope that it will be useful, 27*71a758e1SMarek Vasut * but WITHOUT ANY WARRANTY; without even the implied warranty of 28*71a758e1SMarek Vasut * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 29*71a758e1SMarek Vasut * GNU General Public License for more details. 30*71a758e1SMarek Vasut * 31*71a758e1SMarek Vasut * You should have received a copy of the GNU General Public License 32*71a758e1SMarek Vasut * along with this program; if not, write to the Free Software 33*71a758e1SMarek Vasut * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 34*71a758e1SMarek Vasut * MA 02111-1307 USA 35*71a758e1SMarek Vasut */ 36*71a758e1SMarek Vasut #include <common.h> 37*71a758e1SMarek Vasut #include <malloc.h> 38*71a758e1SMarek Vasut #include <mmc.h> 39*71a758e1SMarek Vasut #include <asm/errno.h> 40*71a758e1SMarek Vasut #include <asm/io.h> 41*71a758e1SMarek Vasut #include <asm/arch/clock.h> 42*71a758e1SMarek Vasut #include <asm/arch/imx-regs.h> 43*71a758e1SMarek Vasut #include <asm/arch/sys_proto.h> 44*71a758e1SMarek Vasut 45*71a758e1SMarek Vasut struct mxsmmc_priv { 46*71a758e1SMarek Vasut int id; 47*71a758e1SMarek Vasut struct mx28_ssp_regs *regs; 48*71a758e1SMarek Vasut uint32_t clkseq_bypass; 49*71a758e1SMarek Vasut uint32_t *clkctrl_ssp; 50*71a758e1SMarek Vasut uint32_t buswidth; 51*71a758e1SMarek Vasut int (*mmc_is_wp)(int); 52*71a758e1SMarek Vasut }; 53*71a758e1SMarek Vasut 54*71a758e1SMarek Vasut #define MXSMMC_MAX_TIMEOUT 10000 55*71a758e1SMarek Vasut 56*71a758e1SMarek Vasut /* 57*71a758e1SMarek Vasut * Sends a command out on the bus. Takes the mmc pointer, 58*71a758e1SMarek Vasut * a command pointer, and an optional data pointer. 59*71a758e1SMarek Vasut */ 60*71a758e1SMarek Vasut static int 61*71a758e1SMarek Vasut mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 62*71a758e1SMarek Vasut { 63*71a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 64*71a758e1SMarek Vasut struct mx28_ssp_regs *ssp_regs = priv->regs; 65*71a758e1SMarek Vasut uint32_t reg; 66*71a758e1SMarek Vasut int timeout; 67*71a758e1SMarek Vasut uint32_t data_count; 68*71a758e1SMarek Vasut uint32_t *data_ptr; 69*71a758e1SMarek Vasut uint32_t ctrl0; 70*71a758e1SMarek Vasut 71*71a758e1SMarek Vasut debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 72*71a758e1SMarek Vasut 73*71a758e1SMarek Vasut /* Check bus busy */ 74*71a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 75*71a758e1SMarek Vasut while (--timeout) { 76*71a758e1SMarek Vasut udelay(1000); 77*71a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 78*71a758e1SMarek Vasut if (!(reg & 79*71a758e1SMarek Vasut (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 80*71a758e1SMarek Vasut SSP_STATUS_CMD_BUSY))) { 81*71a758e1SMarek Vasut break; 82*71a758e1SMarek Vasut } 83*71a758e1SMarek Vasut } 84*71a758e1SMarek Vasut 85*71a758e1SMarek Vasut if (!timeout) { 86*71a758e1SMarek Vasut printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 87*71a758e1SMarek Vasut return TIMEOUT; 88*71a758e1SMarek Vasut } 89*71a758e1SMarek Vasut 90*71a758e1SMarek Vasut /* See if card is present */ 91*71a758e1SMarek Vasut if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 92*71a758e1SMarek Vasut printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 93*71a758e1SMarek Vasut return NO_CARD_ERR; 94*71a758e1SMarek Vasut } 95*71a758e1SMarek Vasut 96*71a758e1SMarek Vasut /* Start building CTRL0 contents */ 97*71a758e1SMarek Vasut ctrl0 = priv->buswidth; 98*71a758e1SMarek Vasut 99*71a758e1SMarek Vasut /* Set up command */ 100*71a758e1SMarek Vasut if (!(cmd->resp_type & MMC_RSP_CRC)) 101*71a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_IGNORE_CRC; 102*71a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 103*71a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_GET_RESP; 104*71a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 105*71a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_LONG_RESP; 106*71a758e1SMarek Vasut 107*71a758e1SMarek Vasut /* Command index */ 108*71a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_cmd0); 109*71a758e1SMarek Vasut reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 110*71a758e1SMarek Vasut reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 111*71a758e1SMarek Vasut if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 112*71a758e1SMarek Vasut reg |= SSP_CMD0_APPEND_8CYC; 113*71a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_cmd0); 114*71a758e1SMarek Vasut 115*71a758e1SMarek Vasut /* Command argument */ 116*71a758e1SMarek Vasut writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 117*71a758e1SMarek Vasut 118*71a758e1SMarek Vasut /* Set up data */ 119*71a758e1SMarek Vasut if (data) { 120*71a758e1SMarek Vasut /* READ or WRITE */ 121*71a758e1SMarek Vasut if (data->flags & MMC_DATA_READ) { 122*71a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_READ; 123*71a758e1SMarek Vasut } else if (priv->mmc_is_wp(mmc->block_dev.dev)) { 124*71a758e1SMarek Vasut printf("MMC%d: Can not write a locked card!\n", 125*71a758e1SMarek Vasut mmc->block_dev.dev); 126*71a758e1SMarek Vasut return UNUSABLE_ERR; 127*71a758e1SMarek Vasut } 128*71a758e1SMarek Vasut 129*71a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_DATA_XFER; 130*71a758e1SMarek Vasut reg = ((data->blocks - 1) << 131*71a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 132*71a758e1SMarek Vasut ((ffs(data->blocksize) - 1) << 133*71a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 134*71a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_block_size); 135*71a758e1SMarek Vasut 136*71a758e1SMarek Vasut reg = data->blocksize * data->blocks; 137*71a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_xfer_size); 138*71a758e1SMarek Vasut } 139*71a758e1SMarek Vasut 140*71a758e1SMarek Vasut /* Kick off the command */ 141*71a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 142*71a758e1SMarek Vasut writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 143*71a758e1SMarek Vasut 144*71a758e1SMarek Vasut /* Wait for the command to complete */ 145*71a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 146*71a758e1SMarek Vasut while (--timeout) { 147*71a758e1SMarek Vasut udelay(1000); 148*71a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 149*71a758e1SMarek Vasut if (!(reg & SSP_STATUS_CMD_BUSY)) 150*71a758e1SMarek Vasut break; 151*71a758e1SMarek Vasut } 152*71a758e1SMarek Vasut 153*71a758e1SMarek Vasut if (!timeout) { 154*71a758e1SMarek Vasut printf("MMC%d: Command %d busy\n", 155*71a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx); 156*71a758e1SMarek Vasut return TIMEOUT; 157*71a758e1SMarek Vasut } 158*71a758e1SMarek Vasut 159*71a758e1SMarek Vasut /* Check command timeout */ 160*71a758e1SMarek Vasut if (reg & SSP_STATUS_RESP_TIMEOUT) { 161*71a758e1SMarek Vasut printf("MMC%d: Command %d timeout (status 0x%08x)\n", 162*71a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 163*71a758e1SMarek Vasut return TIMEOUT; 164*71a758e1SMarek Vasut } 165*71a758e1SMarek Vasut 166*71a758e1SMarek Vasut /* Check command errors */ 167*71a758e1SMarek Vasut if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 168*71a758e1SMarek Vasut printf("MMC%d: Command %d error (status 0x%08x)!\n", 169*71a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 170*71a758e1SMarek Vasut return COMM_ERR; 171*71a758e1SMarek Vasut } 172*71a758e1SMarek Vasut 173*71a758e1SMarek Vasut /* Copy response to response buffer */ 174*71a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) { 175*71a758e1SMarek Vasut cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 176*71a758e1SMarek Vasut cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 177*71a758e1SMarek Vasut cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 178*71a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 179*71a758e1SMarek Vasut } else 180*71a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 181*71a758e1SMarek Vasut 182*71a758e1SMarek Vasut /* Return if no data to process */ 183*71a758e1SMarek Vasut if (!data) 184*71a758e1SMarek Vasut return 0; 185*71a758e1SMarek Vasut 186*71a758e1SMarek Vasut /* Process the data */ 187*71a758e1SMarek Vasut data_count = data->blocksize * data->blocks; 188*71a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 189*71a758e1SMarek Vasut if (data->flags & MMC_DATA_READ) { 190*71a758e1SMarek Vasut data_ptr = (uint32_t *)data->dest; 191*71a758e1SMarek Vasut while (data_count && --timeout) { 192*71a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 193*71a758e1SMarek Vasut if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 194*71a758e1SMarek Vasut *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 195*71a758e1SMarek Vasut data_count -= 4; 196*71a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 197*71a758e1SMarek Vasut } else 198*71a758e1SMarek Vasut udelay(1000); 199*71a758e1SMarek Vasut } 200*71a758e1SMarek Vasut } else { 201*71a758e1SMarek Vasut data_ptr = (uint32_t *)data->src; 202*71a758e1SMarek Vasut timeout *= 100; 203*71a758e1SMarek Vasut while (data_count && --timeout) { 204*71a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 205*71a758e1SMarek Vasut if (!(reg & SSP_STATUS_FIFO_FULL)) { 206*71a758e1SMarek Vasut writel(*data_ptr++, &ssp_regs->hw_ssp_data); 207*71a758e1SMarek Vasut data_count -= 4; 208*71a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 209*71a758e1SMarek Vasut } else 210*71a758e1SMarek Vasut udelay(1000); 211*71a758e1SMarek Vasut } 212*71a758e1SMarek Vasut } 213*71a758e1SMarek Vasut 214*71a758e1SMarek Vasut if (!timeout) { 215*71a758e1SMarek Vasut printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n", 216*71a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 217*71a758e1SMarek Vasut return COMM_ERR; 218*71a758e1SMarek Vasut } 219*71a758e1SMarek Vasut 220*71a758e1SMarek Vasut /* Check data errors */ 221*71a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 222*71a758e1SMarek Vasut if (reg & 223*71a758e1SMarek Vasut (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 224*71a758e1SMarek Vasut SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 225*71a758e1SMarek Vasut printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 226*71a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 227*71a758e1SMarek Vasut return COMM_ERR; 228*71a758e1SMarek Vasut } 229*71a758e1SMarek Vasut 230*71a758e1SMarek Vasut return 0; 231*71a758e1SMarek Vasut } 232*71a758e1SMarek Vasut 233*71a758e1SMarek Vasut static void mxsmmc_set_ios(struct mmc *mmc) 234*71a758e1SMarek Vasut { 235*71a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 236*71a758e1SMarek Vasut struct mx28_ssp_regs *ssp_regs = priv->regs; 237*71a758e1SMarek Vasut 238*71a758e1SMarek Vasut /* Set the clock speed */ 239*71a758e1SMarek Vasut if (mmc->clock) 240*71a758e1SMarek Vasut mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 241*71a758e1SMarek Vasut 242*71a758e1SMarek Vasut switch (mmc->bus_width) { 243*71a758e1SMarek Vasut case 1: 244*71a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 245*71a758e1SMarek Vasut break; 246*71a758e1SMarek Vasut case 4: 247*71a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 248*71a758e1SMarek Vasut break; 249*71a758e1SMarek Vasut case 8: 250*71a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 251*71a758e1SMarek Vasut break; 252*71a758e1SMarek Vasut } 253*71a758e1SMarek Vasut 254*71a758e1SMarek Vasut /* Set the bus width */ 255*71a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 256*71a758e1SMarek Vasut SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 257*71a758e1SMarek Vasut 258*71a758e1SMarek Vasut debug("MMC%d: Set %d bits bus width\n", 259*71a758e1SMarek Vasut mmc->block_dev.dev, mmc->bus_width); 260*71a758e1SMarek Vasut } 261*71a758e1SMarek Vasut 262*71a758e1SMarek Vasut static int mxsmmc_init(struct mmc *mmc) 263*71a758e1SMarek Vasut { 264*71a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 265*71a758e1SMarek Vasut struct mx28_ssp_regs *ssp_regs = priv->regs; 266*71a758e1SMarek Vasut 267*71a758e1SMarek Vasut /* Reset SSP */ 268*71a758e1SMarek Vasut mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 269*71a758e1SMarek Vasut 270*71a758e1SMarek Vasut /* 8 bits word length in MMC mode */ 271*71a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 272*71a758e1SMarek Vasut SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK, 273*71a758e1SMarek Vasut SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 274*71a758e1SMarek Vasut 275*71a758e1SMarek Vasut /* Set initial bit clock 400 KHz */ 276*71a758e1SMarek Vasut mx28_set_ssp_busclock(priv->id, 400); 277*71a758e1SMarek Vasut 278*71a758e1SMarek Vasut /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 279*71a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 280*71a758e1SMarek Vasut udelay(200); 281*71a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 282*71a758e1SMarek Vasut 283*71a758e1SMarek Vasut return 0; 284*71a758e1SMarek Vasut } 285*71a758e1SMarek Vasut 286*71a758e1SMarek Vasut int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 287*71a758e1SMarek Vasut { 288*71a758e1SMarek Vasut struct mx28_clkctrl_regs *clkctrl_regs = 289*71a758e1SMarek Vasut (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; 290*71a758e1SMarek Vasut struct mmc *mmc = NULL; 291*71a758e1SMarek Vasut struct mxsmmc_priv *priv = NULL; 292*71a758e1SMarek Vasut 293*71a758e1SMarek Vasut mmc = malloc(sizeof(struct mmc)); 294*71a758e1SMarek Vasut if (!mmc) 295*71a758e1SMarek Vasut return -ENOMEM; 296*71a758e1SMarek Vasut 297*71a758e1SMarek Vasut priv = malloc(sizeof(struct mxsmmc_priv)); 298*71a758e1SMarek Vasut if (!priv) { 299*71a758e1SMarek Vasut free(mmc); 300*71a758e1SMarek Vasut return -ENOMEM; 301*71a758e1SMarek Vasut } 302*71a758e1SMarek Vasut 303*71a758e1SMarek Vasut priv->mmc_is_wp = wp; 304*71a758e1SMarek Vasut priv->id = id; 305*71a758e1SMarek Vasut switch (id) { 306*71a758e1SMarek Vasut case 0: 307*71a758e1SMarek Vasut priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE; 308*71a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 309*71a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 310*71a758e1SMarek Vasut break; 311*71a758e1SMarek Vasut case 1: 312*71a758e1SMarek Vasut priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE; 313*71a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 314*71a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 315*71a758e1SMarek Vasut break; 316*71a758e1SMarek Vasut case 2: 317*71a758e1SMarek Vasut priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE; 318*71a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 319*71a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 320*71a758e1SMarek Vasut break; 321*71a758e1SMarek Vasut case 3: 322*71a758e1SMarek Vasut priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE; 323*71a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 324*71a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 325*71a758e1SMarek Vasut break; 326*71a758e1SMarek Vasut } 327*71a758e1SMarek Vasut 328*71a758e1SMarek Vasut sprintf(mmc->name, "MXS MMC"); 329*71a758e1SMarek Vasut mmc->send_cmd = mxsmmc_send_cmd; 330*71a758e1SMarek Vasut mmc->set_ios = mxsmmc_set_ios; 331*71a758e1SMarek Vasut mmc->init = mxsmmc_init; 332*71a758e1SMarek Vasut mmc->priv = priv; 333*71a758e1SMarek Vasut 334*71a758e1SMarek Vasut mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 335*71a758e1SMarek Vasut 336*71a758e1SMarek Vasut mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 337*71a758e1SMarek Vasut MMC_MODE_HS_52MHz | MMC_MODE_HS; 338*71a758e1SMarek Vasut 339*71a758e1SMarek Vasut /* 340*71a758e1SMarek Vasut * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 341*71a758e1SMarek Vasut * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 342*71a758e1SMarek Vasut * CLOCK_DIVIDE has to be an even value from 2 to 254, and 343*71a758e1SMarek Vasut * CLOCK_RATE could be any integer from 0 to 255. 344*71a758e1SMarek Vasut */ 345*71a758e1SMarek Vasut mmc->f_min = 400000; 346*71a758e1SMarek Vasut mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 347*71a758e1SMarek Vasut mmc->b_max = 0; 348*71a758e1SMarek Vasut 349*71a758e1SMarek Vasut mmc_register(mmc); 350*71a758e1SMarek Vasut return 0; 351*71a758e1SMarek Vasut } 352