171a758e1SMarek Vasut /* 271a758e1SMarek Vasut * Freescale i.MX28 SSP MMC driver 371a758e1SMarek Vasut * 471a758e1SMarek Vasut * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 571a758e1SMarek Vasut * on behalf of DENX Software Engineering GmbH 671a758e1SMarek Vasut * 771a758e1SMarek Vasut * Based on code from LTIB: 871a758e1SMarek Vasut * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 971a758e1SMarek Vasut * Terry Lv 1071a758e1SMarek Vasut * 1171a758e1SMarek Vasut * Copyright 2007, Freescale Semiconductor, Inc 1271a758e1SMarek Vasut * Andy Fleming 1371a758e1SMarek Vasut * 1471a758e1SMarek Vasut * Based vaguely on the pxa mmc code: 1571a758e1SMarek Vasut * (C) Copyright 2003 1671a758e1SMarek Vasut * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 1771a758e1SMarek Vasut * 1871a758e1SMarek Vasut * See file CREDITS for list of people who contributed to this 1971a758e1SMarek Vasut * project. 2071a758e1SMarek Vasut * 2171a758e1SMarek Vasut * This program is free software; you can redistribute it and/or 2271a758e1SMarek Vasut * modify it under the terms of the GNU General Public License as 2371a758e1SMarek Vasut * published by the Free Software Foundation; either version 2 of 2471a758e1SMarek Vasut * the License, or (at your option) any later version. 2571a758e1SMarek Vasut * 2671a758e1SMarek Vasut * This program is distributed in the hope that it will be useful, 2771a758e1SMarek Vasut * but WITHOUT ANY WARRANTY; without even the implied warranty of 2871a758e1SMarek Vasut * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2971a758e1SMarek Vasut * GNU General Public License for more details. 3071a758e1SMarek Vasut * 3171a758e1SMarek Vasut * You should have received a copy of the GNU General Public License 3271a758e1SMarek Vasut * along with this program; if not, write to the Free Software 3371a758e1SMarek Vasut * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 3471a758e1SMarek Vasut * MA 02111-1307 USA 3571a758e1SMarek Vasut */ 3671a758e1SMarek Vasut #include <common.h> 3771a758e1SMarek Vasut #include <malloc.h> 3871a758e1SMarek Vasut #include <mmc.h> 3971a758e1SMarek Vasut #include <asm/errno.h> 4071a758e1SMarek Vasut #include <asm/io.h> 4171a758e1SMarek Vasut #include <asm/arch/clock.h> 4271a758e1SMarek Vasut #include <asm/arch/imx-regs.h> 4371a758e1SMarek Vasut #include <asm/arch/sys_proto.h> 443687c415SMarek Vasut #include <asm/arch/dma.h> 45*4e6d81d1SMarek Vasut #include <bouncebuf.h> 4671a758e1SMarek Vasut 4771a758e1SMarek Vasut struct mxsmmc_priv { 4871a758e1SMarek Vasut int id; 499c471142SOtavio Salvador struct mxs_ssp_regs *regs; 5071a758e1SMarek Vasut uint32_t clkseq_bypass; 5171a758e1SMarek Vasut uint32_t *clkctrl_ssp; 5271a758e1SMarek Vasut uint32_t buswidth; 5371a758e1SMarek Vasut int (*mmc_is_wp)(int); 543687c415SMarek Vasut struct mxs_dma_desc *desc; 5571a758e1SMarek Vasut }; 5671a758e1SMarek Vasut 5771a758e1SMarek Vasut #define MXSMMC_MAX_TIMEOUT 10000 5820255900SMarek Vasut #define MXSMMC_SMALL_TRANSFER 512 5971a758e1SMarek Vasut 6086983328SMarek Vasut static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 6186983328SMarek Vasut { 6286983328SMarek Vasut struct mxs_ssp_regs *ssp_regs = priv->regs; 6386983328SMarek Vasut uint32_t *data_ptr; 6486983328SMarek Vasut int timeout = MXSMMC_MAX_TIMEOUT; 6586983328SMarek Vasut uint32_t reg; 6686983328SMarek Vasut uint32_t data_count = data->blocksize * data->blocks; 6786983328SMarek Vasut 6886983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 6986983328SMarek Vasut data_ptr = (uint32_t *)data->dest; 7086983328SMarek Vasut while (data_count && --timeout) { 7186983328SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 7286983328SMarek Vasut if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 7386983328SMarek Vasut *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 7486983328SMarek Vasut data_count -= 4; 7586983328SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 7686983328SMarek Vasut } else 7786983328SMarek Vasut udelay(1000); 7886983328SMarek Vasut } 7986983328SMarek Vasut } else { 8086983328SMarek Vasut data_ptr = (uint32_t *)data->src; 8186983328SMarek Vasut timeout *= 100; 8286983328SMarek Vasut while (data_count && --timeout) { 8386983328SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 8486983328SMarek Vasut if (!(reg & SSP_STATUS_FIFO_FULL)) { 8586983328SMarek Vasut writel(*data_ptr++, &ssp_regs->hw_ssp_data); 8686983328SMarek Vasut data_count -= 4; 8786983328SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 8886983328SMarek Vasut } else 8986983328SMarek Vasut udelay(1000); 9086983328SMarek Vasut } 9186983328SMarek Vasut } 9286983328SMarek Vasut 9386983328SMarek Vasut return timeout ? 0 : COMM_ERR; 9486983328SMarek Vasut } 9520255900SMarek Vasut 9686983328SMarek Vasut static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 9786983328SMarek Vasut { 9886983328SMarek Vasut uint32_t data_count = data->blocksize * data->blocks; 99*4e6d81d1SMarek Vasut uint32_t cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); 10086983328SMarek Vasut int dmach; 101abb85be7SMarek Vasut struct mxs_dma_desc *desc = priv->desc; 102*4e6d81d1SMarek Vasut void *addr, *backup; 103*4e6d81d1SMarek Vasut uint8_t flags; 104abb85be7SMarek Vasut 105abb85be7SMarek Vasut memset(desc, 0, sizeof(struct mxs_dma_desc)); 106abb85be7SMarek Vasut desc->address = (dma_addr_t)desc; 10786983328SMarek Vasut 10886983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 10986983328SMarek Vasut priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 110*4e6d81d1SMarek Vasut addr = data->dest; 111*4e6d81d1SMarek Vasut flags = GEN_BB_WRITE; 11286983328SMarek Vasut } else { 11386983328SMarek Vasut priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 114*4e6d81d1SMarek Vasut addr = (void *)data->src; 115*4e6d81d1SMarek Vasut flags = GEN_BB_READ; 116*4e6d81d1SMarek Vasut } 11786983328SMarek Vasut 118*4e6d81d1SMarek Vasut bounce_buffer_start(&addr, data_count, &backup, flags); 119*4e6d81d1SMarek Vasut 120*4e6d81d1SMarek Vasut priv->desc->cmd.address = (dma_addr_t)addr; 121*4e6d81d1SMarek Vasut 122*4e6d81d1SMarek Vasut if (data->flags & MMC_DATA_WRITE) { 12386983328SMarek Vasut /* Flush data to DRAM so DMA can pick them up */ 124*4e6d81d1SMarek Vasut flush_dcache_range((uint32_t)addr, 125*4e6d81d1SMarek Vasut (uint32_t)(addr) + cache_data_count); 12686983328SMarek Vasut } 12786983328SMarek Vasut 12897ed12ceSMarek Vasut /* Invalidate the area, so no writeback into the RAM races with DMA */ 12997ed12ceSMarek Vasut invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 13097ed12ceSMarek Vasut (uint32_t)(priv->desc->cmd.address + cache_data_count)); 13197ed12ceSMarek Vasut 13286983328SMarek Vasut priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 13386983328SMarek Vasut (data_count << MXS_DMA_DESC_BYTES_OFFSET); 13486983328SMarek Vasut 13586983328SMarek Vasut dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; 13686983328SMarek Vasut mxs_dma_desc_append(dmach, priv->desc); 137*4e6d81d1SMarek Vasut if (mxs_dma_go(dmach)) { 138*4e6d81d1SMarek Vasut bounce_buffer_stop(&addr, data_count, &backup, flags); 13986983328SMarek Vasut return COMM_ERR; 140*4e6d81d1SMarek Vasut } 14186983328SMarek Vasut 14286983328SMarek Vasut /* The data arrived into DRAM, invalidate cache over them */ 14386983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 144*4e6d81d1SMarek Vasut invalidate_dcache_range((uint32_t)addr, 145*4e6d81d1SMarek Vasut (uint32_t)(addr) + cache_data_count); 14686983328SMarek Vasut } 14786983328SMarek Vasut 148*4e6d81d1SMarek Vasut bounce_buffer_stop(&addr, data_count, &backup, flags); 149*4e6d81d1SMarek Vasut 15086983328SMarek Vasut return 0; 15186983328SMarek Vasut } 15286983328SMarek Vasut 15371a758e1SMarek Vasut /* 15471a758e1SMarek Vasut * Sends a command out on the bus. Takes the mmc pointer, 15571a758e1SMarek Vasut * a command pointer, and an optional data pointer. 15671a758e1SMarek Vasut */ 15771a758e1SMarek Vasut static int 15871a758e1SMarek Vasut mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 15971a758e1SMarek Vasut { 16071a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 1619c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 16271a758e1SMarek Vasut uint32_t reg; 16371a758e1SMarek Vasut int timeout; 16471a758e1SMarek Vasut uint32_t ctrl0; 16586983328SMarek Vasut int ret; 16671a758e1SMarek Vasut 16771a758e1SMarek Vasut debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 16871a758e1SMarek Vasut 16971a758e1SMarek Vasut /* Check bus busy */ 17071a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 17171a758e1SMarek Vasut while (--timeout) { 17271a758e1SMarek Vasut udelay(1000); 17371a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 17471a758e1SMarek Vasut if (!(reg & 17571a758e1SMarek Vasut (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 17671a758e1SMarek Vasut SSP_STATUS_CMD_BUSY))) { 17771a758e1SMarek Vasut break; 17871a758e1SMarek Vasut } 17971a758e1SMarek Vasut } 18071a758e1SMarek Vasut 18171a758e1SMarek Vasut if (!timeout) { 18271a758e1SMarek Vasut printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 18371a758e1SMarek Vasut return TIMEOUT; 18471a758e1SMarek Vasut } 18571a758e1SMarek Vasut 18671a758e1SMarek Vasut /* See if card is present */ 18771a758e1SMarek Vasut if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 18871a758e1SMarek Vasut printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 18971a758e1SMarek Vasut return NO_CARD_ERR; 19071a758e1SMarek Vasut } 19171a758e1SMarek Vasut 19271a758e1SMarek Vasut /* Start building CTRL0 contents */ 19371a758e1SMarek Vasut ctrl0 = priv->buswidth; 19471a758e1SMarek Vasut 19571a758e1SMarek Vasut /* Set up command */ 19671a758e1SMarek Vasut if (!(cmd->resp_type & MMC_RSP_CRC)) 19771a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_IGNORE_CRC; 19871a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 19971a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_GET_RESP; 20071a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 20171a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_LONG_RESP; 20271a758e1SMarek Vasut 203abb85be7SMarek Vasut if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) 204abb85be7SMarek Vasut writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 205abb85be7SMarek Vasut else 206abb85be7SMarek Vasut writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 207abb85be7SMarek Vasut 20871a758e1SMarek Vasut /* Command index */ 20971a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_cmd0); 21071a758e1SMarek Vasut reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 21171a758e1SMarek Vasut reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 21271a758e1SMarek Vasut if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 21371a758e1SMarek Vasut reg |= SSP_CMD0_APPEND_8CYC; 21471a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_cmd0); 21571a758e1SMarek Vasut 21671a758e1SMarek Vasut /* Command argument */ 21771a758e1SMarek Vasut writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 21871a758e1SMarek Vasut 21971a758e1SMarek Vasut /* Set up data */ 22071a758e1SMarek Vasut if (data) { 22171a758e1SMarek Vasut /* READ or WRITE */ 22271a758e1SMarek Vasut if (data->flags & MMC_DATA_READ) { 22371a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_READ; 224c7527b70SMarek Vasut } else if (priv->mmc_is_wp && 225c7527b70SMarek Vasut priv->mmc_is_wp(mmc->block_dev.dev)) { 22671a758e1SMarek Vasut printf("MMC%d: Can not write a locked card!\n", 22771a758e1SMarek Vasut mmc->block_dev.dev); 22871a758e1SMarek Vasut return UNUSABLE_ERR; 22971a758e1SMarek Vasut } 23071a758e1SMarek Vasut 23171a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_DATA_XFER; 23271a758e1SMarek Vasut reg = ((data->blocks - 1) << 23371a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 23471a758e1SMarek Vasut ((ffs(data->blocksize) - 1) << 23571a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 23671a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_block_size); 23771a758e1SMarek Vasut 23871a758e1SMarek Vasut reg = data->blocksize * data->blocks; 23971a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_xfer_size); 24071a758e1SMarek Vasut } 24171a758e1SMarek Vasut 24271a758e1SMarek Vasut /* Kick off the command */ 24371a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 24471a758e1SMarek Vasut writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 24571a758e1SMarek Vasut 24671a758e1SMarek Vasut /* Wait for the command to complete */ 24771a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 24871a758e1SMarek Vasut while (--timeout) { 24971a758e1SMarek Vasut udelay(1000); 25071a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 25171a758e1SMarek Vasut if (!(reg & SSP_STATUS_CMD_BUSY)) 25271a758e1SMarek Vasut break; 25371a758e1SMarek Vasut } 25471a758e1SMarek Vasut 25571a758e1SMarek Vasut if (!timeout) { 25671a758e1SMarek Vasut printf("MMC%d: Command %d busy\n", 25771a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx); 25871a758e1SMarek Vasut return TIMEOUT; 25971a758e1SMarek Vasut } 26071a758e1SMarek Vasut 26171a758e1SMarek Vasut /* Check command timeout */ 26271a758e1SMarek Vasut if (reg & SSP_STATUS_RESP_TIMEOUT) { 26371a758e1SMarek Vasut printf("MMC%d: Command %d timeout (status 0x%08x)\n", 26471a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 26571a758e1SMarek Vasut return TIMEOUT; 26671a758e1SMarek Vasut } 26771a758e1SMarek Vasut 26871a758e1SMarek Vasut /* Check command errors */ 26971a758e1SMarek Vasut if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 27071a758e1SMarek Vasut printf("MMC%d: Command %d error (status 0x%08x)!\n", 27171a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 27271a758e1SMarek Vasut return COMM_ERR; 27371a758e1SMarek Vasut } 27471a758e1SMarek Vasut 27571a758e1SMarek Vasut /* Copy response to response buffer */ 27671a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) { 27771a758e1SMarek Vasut cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 27871a758e1SMarek Vasut cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 27971a758e1SMarek Vasut cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 28071a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 28171a758e1SMarek Vasut } else 28271a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 28371a758e1SMarek Vasut 28471a758e1SMarek Vasut /* Return if no data to process */ 28571a758e1SMarek Vasut if (!data) 28671a758e1SMarek Vasut return 0; 28771a758e1SMarek Vasut 28820255900SMarek Vasut if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { 28986983328SMarek Vasut ret = mxsmmc_send_cmd_pio(priv, data); 29086983328SMarek Vasut if (ret) { 29120255900SMarek Vasut printf("MMC%d: Data timeout with command %d " 29220255900SMarek Vasut "(status 0x%08x)!\n", 2934cc76c60SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 29486983328SMarek Vasut return ret; 2954cc76c60SMarek Vasut } 296abb85be7SMarek Vasut } else { 297abb85be7SMarek Vasut ret = mxsmmc_send_cmd_dma(priv, data); 298abb85be7SMarek Vasut if (ret) { 299abb85be7SMarek Vasut printf("MMC%d: DMA transfer failed\n", 300abb85be7SMarek Vasut mmc->block_dev.dev); 301abb85be7SMarek Vasut return ret; 302abb85be7SMarek Vasut } 30320255900SMarek Vasut } 3043687c415SMarek Vasut 30571a758e1SMarek Vasut /* Check data errors */ 30671a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 30771a758e1SMarek Vasut if (reg & 30871a758e1SMarek Vasut (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 30971a758e1SMarek Vasut SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 31071a758e1SMarek Vasut printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 31171a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 31271a758e1SMarek Vasut return COMM_ERR; 31371a758e1SMarek Vasut } 31471a758e1SMarek Vasut 31571a758e1SMarek Vasut return 0; 31671a758e1SMarek Vasut } 31771a758e1SMarek Vasut 31871a758e1SMarek Vasut static void mxsmmc_set_ios(struct mmc *mmc) 31971a758e1SMarek Vasut { 32071a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 3219c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 32271a758e1SMarek Vasut 32371a758e1SMarek Vasut /* Set the clock speed */ 32471a758e1SMarek Vasut if (mmc->clock) 32571a758e1SMarek Vasut mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 32671a758e1SMarek Vasut 32771a758e1SMarek Vasut switch (mmc->bus_width) { 32871a758e1SMarek Vasut case 1: 32971a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 33071a758e1SMarek Vasut break; 33171a758e1SMarek Vasut case 4: 33271a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 33371a758e1SMarek Vasut break; 33471a758e1SMarek Vasut case 8: 33571a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 33671a758e1SMarek Vasut break; 33771a758e1SMarek Vasut } 33871a758e1SMarek Vasut 33971a758e1SMarek Vasut /* Set the bus width */ 34071a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 34171a758e1SMarek Vasut SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 34271a758e1SMarek Vasut 34371a758e1SMarek Vasut debug("MMC%d: Set %d bits bus width\n", 34471a758e1SMarek Vasut mmc->block_dev.dev, mmc->bus_width); 34571a758e1SMarek Vasut } 34671a758e1SMarek Vasut 34771a758e1SMarek Vasut static int mxsmmc_init(struct mmc *mmc) 34871a758e1SMarek Vasut { 34971a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 3509c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 35171a758e1SMarek Vasut 35271a758e1SMarek Vasut /* Reset SSP */ 353fa7a51cbSOtavio Salvador mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 35471a758e1SMarek Vasut 35571a758e1SMarek Vasut /* 8 bits word length in MMC mode */ 35671a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 357abb85be7SMarek Vasut SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | 358abb85be7SMarek Vasut SSP_CTRL1_DMA_ENABLE, 359abb85be7SMarek Vasut SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 36071a758e1SMarek Vasut 36171a758e1SMarek Vasut /* Set initial bit clock 400 KHz */ 36271a758e1SMarek Vasut mx28_set_ssp_busclock(priv->id, 400); 36371a758e1SMarek Vasut 36471a758e1SMarek Vasut /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 36571a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 36671a758e1SMarek Vasut udelay(200); 36771a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 36871a758e1SMarek Vasut 36971a758e1SMarek Vasut return 0; 37071a758e1SMarek Vasut } 37171a758e1SMarek Vasut 37271a758e1SMarek Vasut int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 37371a758e1SMarek Vasut { 3749c471142SOtavio Salvador struct mxs_clkctrl_regs *clkctrl_regs = 3759c471142SOtavio Salvador (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 37671a758e1SMarek Vasut struct mmc *mmc = NULL; 37771a758e1SMarek Vasut struct mxsmmc_priv *priv = NULL; 37896666a39SMarek Vasut int ret; 37971a758e1SMarek Vasut 38071a758e1SMarek Vasut mmc = malloc(sizeof(struct mmc)); 38171a758e1SMarek Vasut if (!mmc) 38271a758e1SMarek Vasut return -ENOMEM; 38371a758e1SMarek Vasut 38471a758e1SMarek Vasut priv = malloc(sizeof(struct mxsmmc_priv)); 38571a758e1SMarek Vasut if (!priv) { 38671a758e1SMarek Vasut free(mmc); 38771a758e1SMarek Vasut return -ENOMEM; 38871a758e1SMarek Vasut } 38971a758e1SMarek Vasut 3903687c415SMarek Vasut priv->desc = mxs_dma_desc_alloc(); 3913687c415SMarek Vasut if (!priv->desc) { 3923687c415SMarek Vasut free(priv); 3933687c415SMarek Vasut free(mmc); 3943687c415SMarek Vasut return -ENOMEM; 3953687c415SMarek Vasut } 3963687c415SMarek Vasut 39796666a39SMarek Vasut ret = mxs_dma_init_channel(id); 39896666a39SMarek Vasut if (ret) 39996666a39SMarek Vasut return ret; 40096666a39SMarek Vasut 40171a758e1SMarek Vasut priv->mmc_is_wp = wp; 40271a758e1SMarek Vasut priv->id = id; 40371a758e1SMarek Vasut switch (id) { 40471a758e1SMarek Vasut case 0: 4059c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE; 40671a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 40771a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 40871a758e1SMarek Vasut break; 40971a758e1SMarek Vasut case 1: 4109c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE; 41171a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 41271a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 41371a758e1SMarek Vasut break; 41471a758e1SMarek Vasut case 2: 4159c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE; 41671a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 41771a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 41871a758e1SMarek Vasut break; 41971a758e1SMarek Vasut case 3: 4209c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE; 42171a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 42271a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 42371a758e1SMarek Vasut break; 42471a758e1SMarek Vasut } 42571a758e1SMarek Vasut 42671a758e1SMarek Vasut sprintf(mmc->name, "MXS MMC"); 42771a758e1SMarek Vasut mmc->send_cmd = mxsmmc_send_cmd; 42871a758e1SMarek Vasut mmc->set_ios = mxsmmc_set_ios; 42971a758e1SMarek Vasut mmc->init = mxsmmc_init; 43048972d90SThierry Reding mmc->getcd = NULL; 43171a758e1SMarek Vasut mmc->priv = priv; 43271a758e1SMarek Vasut 43371a758e1SMarek Vasut mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 43471a758e1SMarek Vasut 43571a758e1SMarek Vasut mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 43671a758e1SMarek Vasut MMC_MODE_HS_52MHz | MMC_MODE_HS; 43771a758e1SMarek Vasut 43871a758e1SMarek Vasut /* 43971a758e1SMarek Vasut * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 44071a758e1SMarek Vasut * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 44171a758e1SMarek Vasut * CLOCK_DIVIDE has to be an even value from 2 to 254, and 44271a758e1SMarek Vasut * CLOCK_RATE could be any integer from 0 to 255. 44371a758e1SMarek Vasut */ 44471a758e1SMarek Vasut mmc->f_min = 400000; 44571a758e1SMarek Vasut mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 446e7205905SMarek Vasut mmc->b_max = 0x20; 44771a758e1SMarek Vasut 44871a758e1SMarek Vasut mmc_register(mmc); 44971a758e1SMarek Vasut return 0; 45071a758e1SMarek Vasut } 451