171a758e1SMarek Vasut /* 271a758e1SMarek Vasut * Freescale i.MX28 SSP MMC driver 371a758e1SMarek Vasut * 471a758e1SMarek Vasut * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 571a758e1SMarek Vasut * on behalf of DENX Software Engineering GmbH 671a758e1SMarek Vasut * 771a758e1SMarek Vasut * Based on code from LTIB: 871a758e1SMarek Vasut * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 971a758e1SMarek Vasut * Terry Lv 1071a758e1SMarek Vasut * 1171a758e1SMarek Vasut * Copyright 2007, Freescale Semiconductor, Inc 1271a758e1SMarek Vasut * Andy Fleming 1371a758e1SMarek Vasut * 1471a758e1SMarek Vasut * Based vaguely on the pxa mmc code: 1571a758e1SMarek Vasut * (C) Copyright 2003 1671a758e1SMarek Vasut * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 1771a758e1SMarek Vasut * 1871a758e1SMarek Vasut * See file CREDITS for list of people who contributed to this 1971a758e1SMarek Vasut * project. 2071a758e1SMarek Vasut * 2171a758e1SMarek Vasut * This program is free software; you can redistribute it and/or 2271a758e1SMarek Vasut * modify it under the terms of the GNU General Public License as 2371a758e1SMarek Vasut * published by the Free Software Foundation; either version 2 of 2471a758e1SMarek Vasut * the License, or (at your option) any later version. 2571a758e1SMarek Vasut * 2671a758e1SMarek Vasut * This program is distributed in the hope that it will be useful, 2771a758e1SMarek Vasut * but WITHOUT ANY WARRANTY; without even the implied warranty of 2871a758e1SMarek Vasut * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2971a758e1SMarek Vasut * GNU General Public License for more details. 3071a758e1SMarek Vasut * 3171a758e1SMarek Vasut * You should have received a copy of the GNU General Public License 3271a758e1SMarek Vasut * along with this program; if not, write to the Free Software 3371a758e1SMarek Vasut * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 3471a758e1SMarek Vasut * MA 02111-1307 USA 3571a758e1SMarek Vasut */ 3671a758e1SMarek Vasut #include <common.h> 3771a758e1SMarek Vasut #include <malloc.h> 3871a758e1SMarek Vasut #include <mmc.h> 3971a758e1SMarek Vasut #include <asm/errno.h> 4071a758e1SMarek Vasut #include <asm/io.h> 4171a758e1SMarek Vasut #include <asm/arch/clock.h> 4271a758e1SMarek Vasut #include <asm/arch/imx-regs.h> 4371a758e1SMarek Vasut #include <asm/arch/sys_proto.h> 443687c415SMarek Vasut #include <asm/arch/dma.h> 454e6d81d1SMarek Vasut #include <bouncebuf.h> 4671a758e1SMarek Vasut 4771a758e1SMarek Vasut struct mxsmmc_priv { 4871a758e1SMarek Vasut int id; 499c471142SOtavio Salvador struct mxs_ssp_regs *regs; 5071a758e1SMarek Vasut uint32_t buswidth; 5171a758e1SMarek Vasut int (*mmc_is_wp)(int); 5290bc2bf2SMarek Vasut int (*mmc_cd)(int); 533687c415SMarek Vasut struct mxs_dma_desc *desc; 5471a758e1SMarek Vasut }; 5571a758e1SMarek Vasut 5671a758e1SMarek Vasut #define MXSMMC_MAX_TIMEOUT 10000 5720255900SMarek Vasut #define MXSMMC_SMALL_TRANSFER 512 5871a758e1SMarek Vasut 5990bc2bf2SMarek Vasut static int mxsmmc_cd(struct mxsmmc_priv *priv) 6090bc2bf2SMarek Vasut { 6190bc2bf2SMarek Vasut struct mxs_ssp_regs *ssp_regs = priv->regs; 6290bc2bf2SMarek Vasut 6390bc2bf2SMarek Vasut if (priv->mmc_cd) 6490bc2bf2SMarek Vasut return priv->mmc_cd(priv->id); 6590bc2bf2SMarek Vasut 6690bc2bf2SMarek Vasut return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT); 6790bc2bf2SMarek Vasut } 6890bc2bf2SMarek Vasut 6986983328SMarek Vasut static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 7086983328SMarek Vasut { 7186983328SMarek Vasut struct mxs_ssp_regs *ssp_regs = priv->regs; 7286983328SMarek Vasut uint32_t *data_ptr; 7386983328SMarek Vasut int timeout = MXSMMC_MAX_TIMEOUT; 7486983328SMarek Vasut uint32_t reg; 7586983328SMarek Vasut uint32_t data_count = data->blocksize * data->blocks; 7686983328SMarek Vasut 7786983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 7886983328SMarek Vasut data_ptr = (uint32_t *)data->dest; 7986983328SMarek Vasut while (data_count && --timeout) { 8086983328SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 8186983328SMarek Vasut if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 8286983328SMarek Vasut *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 8386983328SMarek Vasut data_count -= 4; 8486983328SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 8586983328SMarek Vasut } else 8686983328SMarek Vasut udelay(1000); 8786983328SMarek Vasut } 8886983328SMarek Vasut } else { 8986983328SMarek Vasut data_ptr = (uint32_t *)data->src; 9086983328SMarek Vasut timeout *= 100; 9186983328SMarek Vasut while (data_count && --timeout) { 9286983328SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 9386983328SMarek Vasut if (!(reg & SSP_STATUS_FIFO_FULL)) { 9486983328SMarek Vasut writel(*data_ptr++, &ssp_regs->hw_ssp_data); 9586983328SMarek Vasut data_count -= 4; 9686983328SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 9786983328SMarek Vasut } else 9886983328SMarek Vasut udelay(1000); 9986983328SMarek Vasut } 10086983328SMarek Vasut } 10186983328SMarek Vasut 10286983328SMarek Vasut return timeout ? 0 : COMM_ERR; 10386983328SMarek Vasut } 10420255900SMarek Vasut 10586983328SMarek Vasut static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 10686983328SMarek Vasut { 10786983328SMarek Vasut uint32_t data_count = data->blocksize * data->blocks; 10886983328SMarek Vasut int dmach; 109abb85be7SMarek Vasut struct mxs_dma_desc *desc = priv->desc; 11084d35b28SStephen Warren void *addr; 11184d35b28SStephen Warren unsigned int flags; 11284d35b28SStephen Warren struct bounce_buffer bbstate; 113abb85be7SMarek Vasut 114abb85be7SMarek Vasut memset(desc, 0, sizeof(struct mxs_dma_desc)); 115abb85be7SMarek Vasut desc->address = (dma_addr_t)desc; 11686983328SMarek Vasut 11786983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 11886983328SMarek Vasut priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 1194e6d81d1SMarek Vasut addr = data->dest; 1204e6d81d1SMarek Vasut flags = GEN_BB_WRITE; 12186983328SMarek Vasut } else { 12286983328SMarek Vasut priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 1234e6d81d1SMarek Vasut addr = (void *)data->src; 1244e6d81d1SMarek Vasut flags = GEN_BB_READ; 1254e6d81d1SMarek Vasut } 12686983328SMarek Vasut 12784d35b28SStephen Warren bounce_buffer_start(&bbstate, addr, data_count, flags); 1284e6d81d1SMarek Vasut 12984d35b28SStephen Warren priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer; 13097ed12ceSMarek Vasut 13186983328SMarek Vasut priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 13286983328SMarek Vasut (data_count << MXS_DMA_DESC_BYTES_OFFSET); 13386983328SMarek Vasut 134*3430e0bdSMarek Vasut dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; 13586983328SMarek Vasut mxs_dma_desc_append(dmach, priv->desc); 1364e6d81d1SMarek Vasut if (mxs_dma_go(dmach)) { 13784d35b28SStephen Warren bounce_buffer_stop(&bbstate); 13886983328SMarek Vasut return COMM_ERR; 1394e6d81d1SMarek Vasut } 14086983328SMarek Vasut 14184d35b28SStephen Warren bounce_buffer_stop(&bbstate); 1424e6d81d1SMarek Vasut 14386983328SMarek Vasut return 0; 14486983328SMarek Vasut } 14586983328SMarek Vasut 14671a758e1SMarek Vasut /* 14771a758e1SMarek Vasut * Sends a command out on the bus. Takes the mmc pointer, 14871a758e1SMarek Vasut * a command pointer, and an optional data pointer. 14971a758e1SMarek Vasut */ 15071a758e1SMarek Vasut static int 15171a758e1SMarek Vasut mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 15271a758e1SMarek Vasut { 15371a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 1549c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 15571a758e1SMarek Vasut uint32_t reg; 15671a758e1SMarek Vasut int timeout; 15771a758e1SMarek Vasut uint32_t ctrl0; 15886983328SMarek Vasut int ret; 15971a758e1SMarek Vasut 16071a758e1SMarek Vasut debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 16171a758e1SMarek Vasut 16271a758e1SMarek Vasut /* Check bus busy */ 16371a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 16471a758e1SMarek Vasut while (--timeout) { 16571a758e1SMarek Vasut udelay(1000); 16671a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 16771a758e1SMarek Vasut if (!(reg & 16871a758e1SMarek Vasut (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 16971a758e1SMarek Vasut SSP_STATUS_CMD_BUSY))) { 17071a758e1SMarek Vasut break; 17171a758e1SMarek Vasut } 17271a758e1SMarek Vasut } 17371a758e1SMarek Vasut 17471a758e1SMarek Vasut if (!timeout) { 17571a758e1SMarek Vasut printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 17671a758e1SMarek Vasut return TIMEOUT; 17771a758e1SMarek Vasut } 17871a758e1SMarek Vasut 17971a758e1SMarek Vasut /* See if card is present */ 18090bc2bf2SMarek Vasut if (!mxsmmc_cd(priv)) { 18171a758e1SMarek Vasut printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 18271a758e1SMarek Vasut return NO_CARD_ERR; 18371a758e1SMarek Vasut } 18471a758e1SMarek Vasut 18571a758e1SMarek Vasut /* Start building CTRL0 contents */ 18671a758e1SMarek Vasut ctrl0 = priv->buswidth; 18771a758e1SMarek Vasut 18871a758e1SMarek Vasut /* Set up command */ 18971a758e1SMarek Vasut if (!(cmd->resp_type & MMC_RSP_CRC)) 19071a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_IGNORE_CRC; 19171a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 19271a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_GET_RESP; 19371a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 19471a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_LONG_RESP; 19571a758e1SMarek Vasut 196abb85be7SMarek Vasut if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) 197abb85be7SMarek Vasut writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 198abb85be7SMarek Vasut else 199abb85be7SMarek Vasut writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 200abb85be7SMarek Vasut 20171a758e1SMarek Vasut /* Command index */ 20271a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_cmd0); 20371a758e1SMarek Vasut reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 20471a758e1SMarek Vasut reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 20571a758e1SMarek Vasut if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 20671a758e1SMarek Vasut reg |= SSP_CMD0_APPEND_8CYC; 20771a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_cmd0); 20871a758e1SMarek Vasut 20971a758e1SMarek Vasut /* Command argument */ 21071a758e1SMarek Vasut writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 21171a758e1SMarek Vasut 21271a758e1SMarek Vasut /* Set up data */ 21371a758e1SMarek Vasut if (data) { 21471a758e1SMarek Vasut /* READ or WRITE */ 21571a758e1SMarek Vasut if (data->flags & MMC_DATA_READ) { 21671a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_READ; 217c7527b70SMarek Vasut } else if (priv->mmc_is_wp && 218c7527b70SMarek Vasut priv->mmc_is_wp(mmc->block_dev.dev)) { 21971a758e1SMarek Vasut printf("MMC%d: Can not write a locked card!\n", 22071a758e1SMarek Vasut mmc->block_dev.dev); 22171a758e1SMarek Vasut return UNUSABLE_ERR; 22271a758e1SMarek Vasut } 22371a758e1SMarek Vasut 22471a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_DATA_XFER; 225e5b380acSMarek Vasut 226e5b380acSMarek Vasut reg = data->blocksize * data->blocks; 227e5b380acSMarek Vasut #if defined(CONFIG_MX23) 228e5b380acSMarek Vasut ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK; 229e5b380acSMarek Vasut 230e5b380acSMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_cmd0, 231e5b380acSMarek Vasut SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK, 232e5b380acSMarek Vasut ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) | 233e5b380acSMarek Vasut ((ffs(data->blocksize) - 1) << 234e5b380acSMarek Vasut SSP_CMD0_BLOCK_SIZE_OFFSET)); 235e5b380acSMarek Vasut #elif defined(CONFIG_MX28) 236e5b380acSMarek Vasut writel(reg, &ssp_regs->hw_ssp_xfer_size); 237e5b380acSMarek Vasut 23871a758e1SMarek Vasut reg = ((data->blocks - 1) << 23971a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 24071a758e1SMarek Vasut ((ffs(data->blocksize) - 1) << 24171a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 24271a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_block_size); 243e5b380acSMarek Vasut #endif 24471a758e1SMarek Vasut } 24571a758e1SMarek Vasut 24671a758e1SMarek Vasut /* Kick off the command */ 24771a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 24871a758e1SMarek Vasut writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 24971a758e1SMarek Vasut 25071a758e1SMarek Vasut /* Wait for the command to complete */ 25171a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 25271a758e1SMarek Vasut while (--timeout) { 25371a758e1SMarek Vasut udelay(1000); 25471a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 25571a758e1SMarek Vasut if (!(reg & SSP_STATUS_CMD_BUSY)) 25671a758e1SMarek Vasut break; 25771a758e1SMarek Vasut } 25871a758e1SMarek Vasut 25971a758e1SMarek Vasut if (!timeout) { 26071a758e1SMarek Vasut printf("MMC%d: Command %d busy\n", 26171a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx); 26271a758e1SMarek Vasut return TIMEOUT; 26371a758e1SMarek Vasut } 26471a758e1SMarek Vasut 26571a758e1SMarek Vasut /* Check command timeout */ 26671a758e1SMarek Vasut if (reg & SSP_STATUS_RESP_TIMEOUT) { 26771a758e1SMarek Vasut printf("MMC%d: Command %d timeout (status 0x%08x)\n", 26871a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 26971a758e1SMarek Vasut return TIMEOUT; 27071a758e1SMarek Vasut } 27171a758e1SMarek Vasut 27271a758e1SMarek Vasut /* Check command errors */ 27371a758e1SMarek Vasut if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 27471a758e1SMarek Vasut printf("MMC%d: Command %d error (status 0x%08x)!\n", 27571a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 27671a758e1SMarek Vasut return COMM_ERR; 27771a758e1SMarek Vasut } 27871a758e1SMarek Vasut 27971a758e1SMarek Vasut /* Copy response to response buffer */ 28071a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) { 28171a758e1SMarek Vasut cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 28271a758e1SMarek Vasut cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 28371a758e1SMarek Vasut cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 28471a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 28571a758e1SMarek Vasut } else 28671a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 28771a758e1SMarek Vasut 28871a758e1SMarek Vasut /* Return if no data to process */ 28971a758e1SMarek Vasut if (!data) 29071a758e1SMarek Vasut return 0; 29171a758e1SMarek Vasut 29220255900SMarek Vasut if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { 29386983328SMarek Vasut ret = mxsmmc_send_cmd_pio(priv, data); 29486983328SMarek Vasut if (ret) { 29520255900SMarek Vasut printf("MMC%d: Data timeout with command %d " 29620255900SMarek Vasut "(status 0x%08x)!\n", 2974cc76c60SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 29886983328SMarek Vasut return ret; 2994cc76c60SMarek Vasut } 300abb85be7SMarek Vasut } else { 301abb85be7SMarek Vasut ret = mxsmmc_send_cmd_dma(priv, data); 302abb85be7SMarek Vasut if (ret) { 303abb85be7SMarek Vasut printf("MMC%d: DMA transfer failed\n", 304abb85be7SMarek Vasut mmc->block_dev.dev); 305abb85be7SMarek Vasut return ret; 306abb85be7SMarek Vasut } 30720255900SMarek Vasut } 3083687c415SMarek Vasut 30971a758e1SMarek Vasut /* Check data errors */ 31071a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 31171a758e1SMarek Vasut if (reg & 31271a758e1SMarek Vasut (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 31371a758e1SMarek Vasut SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 31471a758e1SMarek Vasut printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 31571a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 31671a758e1SMarek Vasut return COMM_ERR; 31771a758e1SMarek Vasut } 31871a758e1SMarek Vasut 31971a758e1SMarek Vasut return 0; 32071a758e1SMarek Vasut } 32171a758e1SMarek Vasut 32271a758e1SMarek Vasut static void mxsmmc_set_ios(struct mmc *mmc) 32371a758e1SMarek Vasut { 32471a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 3259c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 32671a758e1SMarek Vasut 32771a758e1SMarek Vasut /* Set the clock speed */ 32871a758e1SMarek Vasut if (mmc->clock) 329bf48fcb6SOtavio Salvador mxs_set_ssp_busclock(priv->id, mmc->clock / 1000); 33071a758e1SMarek Vasut 33171a758e1SMarek Vasut switch (mmc->bus_width) { 33271a758e1SMarek Vasut case 1: 33371a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 33471a758e1SMarek Vasut break; 33571a758e1SMarek Vasut case 4: 33671a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 33771a758e1SMarek Vasut break; 33871a758e1SMarek Vasut case 8: 33971a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 34071a758e1SMarek Vasut break; 34171a758e1SMarek Vasut } 34271a758e1SMarek Vasut 34371a758e1SMarek Vasut /* Set the bus width */ 34471a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 34571a758e1SMarek Vasut SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 34671a758e1SMarek Vasut 34771a758e1SMarek Vasut debug("MMC%d: Set %d bits bus width\n", 34871a758e1SMarek Vasut mmc->block_dev.dev, mmc->bus_width); 34971a758e1SMarek Vasut } 35071a758e1SMarek Vasut 35171a758e1SMarek Vasut static int mxsmmc_init(struct mmc *mmc) 35271a758e1SMarek Vasut { 35371a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 3549c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 35571a758e1SMarek Vasut 35671a758e1SMarek Vasut /* Reset SSP */ 357fa7a51cbSOtavio Salvador mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 35871a758e1SMarek Vasut 3598000d8a8SOtavio Salvador /* Reconfigure the SSP block for MMC operation */ 3608000d8a8SOtavio Salvador writel(SSP_CTRL1_SSP_MODE_SD_MMC | 3618000d8a8SOtavio Salvador SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | 3628000d8a8SOtavio Salvador SSP_CTRL1_DMA_ENABLE | 3638000d8a8SOtavio Salvador SSP_CTRL1_POLARITY | 3648000d8a8SOtavio Salvador SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 3658000d8a8SOtavio Salvador SSP_CTRL1_DATA_CRC_IRQ_EN | 3668000d8a8SOtavio Salvador SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 3678000d8a8SOtavio Salvador SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 3688000d8a8SOtavio Salvador SSP_CTRL1_RESP_ERR_IRQ_EN, 3698000d8a8SOtavio Salvador &ssp_regs->hw_ssp_ctrl1_set); 37071a758e1SMarek Vasut 37171a758e1SMarek Vasut /* Set initial bit clock 400 KHz */ 372bf48fcb6SOtavio Salvador mxs_set_ssp_busclock(priv->id, 400); 37371a758e1SMarek Vasut 37471a758e1SMarek Vasut /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 37571a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 37671a758e1SMarek Vasut udelay(200); 37771a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 37871a758e1SMarek Vasut 37971a758e1SMarek Vasut return 0; 38071a758e1SMarek Vasut } 38171a758e1SMarek Vasut 38290bc2bf2SMarek Vasut int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) 38371a758e1SMarek Vasut { 38471a758e1SMarek Vasut struct mmc *mmc = NULL; 38571a758e1SMarek Vasut struct mxsmmc_priv *priv = NULL; 38696666a39SMarek Vasut int ret; 387*3430e0bdSMarek Vasut const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id); 3881a3c5ffeSMarek Vasut 389*3430e0bdSMarek Vasut if (!mxs_ssp_bus_id_valid(id)) 3901a3c5ffeSMarek Vasut return -ENODEV; 39171a758e1SMarek Vasut 39271a758e1SMarek Vasut mmc = malloc(sizeof(struct mmc)); 39371a758e1SMarek Vasut if (!mmc) 39471a758e1SMarek Vasut return -ENOMEM; 39571a758e1SMarek Vasut 39671a758e1SMarek Vasut priv = malloc(sizeof(struct mxsmmc_priv)); 39771a758e1SMarek Vasut if (!priv) { 39871a758e1SMarek Vasut free(mmc); 39971a758e1SMarek Vasut return -ENOMEM; 40071a758e1SMarek Vasut } 40171a758e1SMarek Vasut 4023687c415SMarek Vasut priv->desc = mxs_dma_desc_alloc(); 4033687c415SMarek Vasut if (!priv->desc) { 4043687c415SMarek Vasut free(priv); 4053687c415SMarek Vasut free(mmc); 4063687c415SMarek Vasut return -ENOMEM; 4073687c415SMarek Vasut } 4083687c415SMarek Vasut 409*3430e0bdSMarek Vasut ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id); 41096666a39SMarek Vasut if (ret) 41196666a39SMarek Vasut return ret; 41296666a39SMarek Vasut 41371a758e1SMarek Vasut priv->mmc_is_wp = wp; 41490bc2bf2SMarek Vasut priv->mmc_cd = cd; 41571a758e1SMarek Vasut priv->id = id; 41614e26bcfSMarek Vasut priv->regs = mxs_ssp_regs_by_bus(id); 41771a758e1SMarek Vasut 41871a758e1SMarek Vasut sprintf(mmc->name, "MXS MMC"); 41971a758e1SMarek Vasut mmc->send_cmd = mxsmmc_send_cmd; 42071a758e1SMarek Vasut mmc->set_ios = mxsmmc_set_ios; 42171a758e1SMarek Vasut mmc->init = mxsmmc_init; 42248972d90SThierry Reding mmc->getcd = NULL; 42371a758e1SMarek Vasut mmc->priv = priv; 42471a758e1SMarek Vasut 42571a758e1SMarek Vasut mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 42671a758e1SMarek Vasut 42771a758e1SMarek Vasut mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 42871a758e1SMarek Vasut MMC_MODE_HS_52MHz | MMC_MODE_HS; 42971a758e1SMarek Vasut 43071a758e1SMarek Vasut /* 43171a758e1SMarek Vasut * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 43271a758e1SMarek Vasut * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 43371a758e1SMarek Vasut * CLOCK_DIVIDE has to be an even value from 2 to 254, and 43471a758e1SMarek Vasut * CLOCK_RATE could be any integer from 0 to 255. 43571a758e1SMarek Vasut */ 43671a758e1SMarek Vasut mmc->f_min = 400000; 4371a3c5ffeSMarek Vasut mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; 438e7205905SMarek Vasut mmc->b_max = 0x20; 43971a758e1SMarek Vasut 44071a758e1SMarek Vasut mmc_register(mmc); 44171a758e1SMarek Vasut return 0; 44271a758e1SMarek Vasut } 443