171a758e1SMarek Vasut /* 271a758e1SMarek Vasut * Freescale i.MX28 SSP MMC driver 371a758e1SMarek Vasut * 471a758e1SMarek Vasut * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 571a758e1SMarek Vasut * on behalf of DENX Software Engineering GmbH 671a758e1SMarek Vasut * 771a758e1SMarek Vasut * Based on code from LTIB: 871a758e1SMarek Vasut * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 971a758e1SMarek Vasut * Terry Lv 1071a758e1SMarek Vasut * 1171a758e1SMarek Vasut * Copyright 2007, Freescale Semiconductor, Inc 1271a758e1SMarek Vasut * Andy Fleming 1371a758e1SMarek Vasut * 1471a758e1SMarek Vasut * Based vaguely on the pxa mmc code: 1571a758e1SMarek Vasut * (C) Copyright 2003 1671a758e1SMarek Vasut * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 1771a758e1SMarek Vasut * 1871a758e1SMarek Vasut * See file CREDITS for list of people who contributed to this 1971a758e1SMarek Vasut * project. 2071a758e1SMarek Vasut * 2171a758e1SMarek Vasut * This program is free software; you can redistribute it and/or 2271a758e1SMarek Vasut * modify it under the terms of the GNU General Public License as 2371a758e1SMarek Vasut * published by the Free Software Foundation; either version 2 of 2471a758e1SMarek Vasut * the License, or (at your option) any later version. 2571a758e1SMarek Vasut * 2671a758e1SMarek Vasut * This program is distributed in the hope that it will be useful, 2771a758e1SMarek Vasut * but WITHOUT ANY WARRANTY; without even the implied warranty of 2871a758e1SMarek Vasut * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2971a758e1SMarek Vasut * GNU General Public License for more details. 3071a758e1SMarek Vasut * 3171a758e1SMarek Vasut * You should have received a copy of the GNU General Public License 3271a758e1SMarek Vasut * along with this program; if not, write to the Free Software 3371a758e1SMarek Vasut * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 3471a758e1SMarek Vasut * MA 02111-1307 USA 3571a758e1SMarek Vasut */ 3671a758e1SMarek Vasut #include <common.h> 3771a758e1SMarek Vasut #include <malloc.h> 3871a758e1SMarek Vasut #include <mmc.h> 3971a758e1SMarek Vasut #include <asm/errno.h> 4071a758e1SMarek Vasut #include <asm/io.h> 4171a758e1SMarek Vasut #include <asm/arch/clock.h> 4271a758e1SMarek Vasut #include <asm/arch/imx-regs.h> 4371a758e1SMarek Vasut #include <asm/arch/sys_proto.h> 443687c415SMarek Vasut #include <asm/arch/dma.h> 4571a758e1SMarek Vasut 4671a758e1SMarek Vasut struct mxsmmc_priv { 4771a758e1SMarek Vasut int id; 489c471142SOtavio Salvador struct mxs_ssp_regs *regs; 4971a758e1SMarek Vasut uint32_t clkseq_bypass; 5071a758e1SMarek Vasut uint32_t *clkctrl_ssp; 5171a758e1SMarek Vasut uint32_t buswidth; 5271a758e1SMarek Vasut int (*mmc_is_wp)(int); 533687c415SMarek Vasut struct mxs_dma_desc *desc; 5471a758e1SMarek Vasut }; 5571a758e1SMarek Vasut 5671a758e1SMarek Vasut #define MXSMMC_MAX_TIMEOUT 10000 57*20255900SMarek Vasut #define MXSMMC_SMALL_TRANSFER 512 5871a758e1SMarek Vasut 5986983328SMarek Vasut static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) 6086983328SMarek Vasut { 6186983328SMarek Vasut struct mxs_ssp_regs *ssp_regs = priv->regs; 6286983328SMarek Vasut uint32_t *data_ptr; 6386983328SMarek Vasut int timeout = MXSMMC_MAX_TIMEOUT; 6486983328SMarek Vasut uint32_t reg; 6586983328SMarek Vasut uint32_t data_count = data->blocksize * data->blocks; 6686983328SMarek Vasut 6786983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 6886983328SMarek Vasut data_ptr = (uint32_t *)data->dest; 6986983328SMarek Vasut while (data_count && --timeout) { 7086983328SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 7186983328SMarek Vasut if (!(reg & SSP_STATUS_FIFO_EMPTY)) { 7286983328SMarek Vasut *data_ptr++ = readl(&ssp_regs->hw_ssp_data); 7386983328SMarek Vasut data_count -= 4; 7486983328SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 7586983328SMarek Vasut } else 7686983328SMarek Vasut udelay(1000); 7786983328SMarek Vasut } 7886983328SMarek Vasut } else { 7986983328SMarek Vasut data_ptr = (uint32_t *)data->src; 8086983328SMarek Vasut timeout *= 100; 8186983328SMarek Vasut while (data_count && --timeout) { 8286983328SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 8386983328SMarek Vasut if (!(reg & SSP_STATUS_FIFO_FULL)) { 8486983328SMarek Vasut writel(*data_ptr++, &ssp_regs->hw_ssp_data); 8586983328SMarek Vasut data_count -= 4; 8686983328SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 8786983328SMarek Vasut } else 8886983328SMarek Vasut udelay(1000); 8986983328SMarek Vasut } 9086983328SMarek Vasut } 9186983328SMarek Vasut 9286983328SMarek Vasut return timeout ? 0 : COMM_ERR; 9386983328SMarek Vasut } 94*20255900SMarek Vasut 9586983328SMarek Vasut static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) 9686983328SMarek Vasut { 9786983328SMarek Vasut uint32_t data_count = data->blocksize * data->blocks; 9886983328SMarek Vasut uint32_t cache_data_count; 9986983328SMarek Vasut int dmach; 10086983328SMarek Vasut 10186983328SMarek Vasut if (data_count % ARCH_DMA_MINALIGN) 10286983328SMarek Vasut cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); 10386983328SMarek Vasut else 10486983328SMarek Vasut cache_data_count = data_count; 10586983328SMarek Vasut 10686983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 10786983328SMarek Vasut priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; 10886983328SMarek Vasut priv->desc->cmd.address = (dma_addr_t)data->dest; 10986983328SMarek Vasut } else { 11086983328SMarek Vasut priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; 11186983328SMarek Vasut priv->desc->cmd.address = (dma_addr_t)data->src; 11286983328SMarek Vasut 11386983328SMarek Vasut /* Flush data to DRAM so DMA can pick them up */ 11486983328SMarek Vasut flush_dcache_range((uint32_t)priv->desc->cmd.address, 11586983328SMarek Vasut (uint32_t)(priv->desc->cmd.address + cache_data_count)); 11686983328SMarek Vasut } 11786983328SMarek Vasut 11886983328SMarek Vasut priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | 11986983328SMarek Vasut (data_count << MXS_DMA_DESC_BYTES_OFFSET); 12086983328SMarek Vasut 12186983328SMarek Vasut 12286983328SMarek Vasut dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; 12386983328SMarek Vasut mxs_dma_desc_append(dmach, priv->desc); 12486983328SMarek Vasut if (mxs_dma_go(dmach)) 12586983328SMarek Vasut return COMM_ERR; 12686983328SMarek Vasut 12786983328SMarek Vasut /* The data arrived into DRAM, invalidate cache over them */ 12886983328SMarek Vasut if (data->flags & MMC_DATA_READ) { 12986983328SMarek Vasut invalidate_dcache_range((uint32_t)priv->desc->cmd.address, 13086983328SMarek Vasut (uint32_t)(priv->desc->cmd.address + cache_data_count)); 13186983328SMarek Vasut } 13286983328SMarek Vasut 13386983328SMarek Vasut return 0; 13486983328SMarek Vasut } 13586983328SMarek Vasut 13671a758e1SMarek Vasut /* 13771a758e1SMarek Vasut * Sends a command out on the bus. Takes the mmc pointer, 13871a758e1SMarek Vasut * a command pointer, and an optional data pointer. 13971a758e1SMarek Vasut */ 14071a758e1SMarek Vasut static int 14171a758e1SMarek Vasut mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 14271a758e1SMarek Vasut { 14371a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 1449c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 14571a758e1SMarek Vasut uint32_t reg; 14671a758e1SMarek Vasut int timeout; 14771a758e1SMarek Vasut uint32_t ctrl0; 14886983328SMarek Vasut int ret; 14971a758e1SMarek Vasut 15071a758e1SMarek Vasut debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); 15171a758e1SMarek Vasut 15271a758e1SMarek Vasut /* Check bus busy */ 15371a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 15471a758e1SMarek Vasut while (--timeout) { 15571a758e1SMarek Vasut udelay(1000); 15671a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 15771a758e1SMarek Vasut if (!(reg & 15871a758e1SMarek Vasut (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | 15971a758e1SMarek Vasut SSP_STATUS_CMD_BUSY))) { 16071a758e1SMarek Vasut break; 16171a758e1SMarek Vasut } 16271a758e1SMarek Vasut } 16371a758e1SMarek Vasut 16471a758e1SMarek Vasut if (!timeout) { 16571a758e1SMarek Vasut printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev); 16671a758e1SMarek Vasut return TIMEOUT; 16771a758e1SMarek Vasut } 16871a758e1SMarek Vasut 16971a758e1SMarek Vasut /* See if card is present */ 17071a758e1SMarek Vasut if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) { 17171a758e1SMarek Vasut printf("MMC%d: No card detected!\n", mmc->block_dev.dev); 17271a758e1SMarek Vasut return NO_CARD_ERR; 17371a758e1SMarek Vasut } 17471a758e1SMarek Vasut 17571a758e1SMarek Vasut /* Start building CTRL0 contents */ 17671a758e1SMarek Vasut ctrl0 = priv->buswidth; 17771a758e1SMarek Vasut 17871a758e1SMarek Vasut /* Set up command */ 17971a758e1SMarek Vasut if (!(cmd->resp_type & MMC_RSP_CRC)) 18071a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_IGNORE_CRC; 18171a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ 18271a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_GET_RESP; 18371a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ 18471a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_LONG_RESP; 18571a758e1SMarek Vasut 18671a758e1SMarek Vasut /* Command index */ 18771a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_cmd0); 18871a758e1SMarek Vasut reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); 18971a758e1SMarek Vasut reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; 19071a758e1SMarek Vasut if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 19171a758e1SMarek Vasut reg |= SSP_CMD0_APPEND_8CYC; 19271a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_cmd0); 19371a758e1SMarek Vasut 19471a758e1SMarek Vasut /* Command argument */ 19571a758e1SMarek Vasut writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); 19671a758e1SMarek Vasut 19771a758e1SMarek Vasut /* Set up data */ 19871a758e1SMarek Vasut if (data) { 19971a758e1SMarek Vasut /* READ or WRITE */ 20071a758e1SMarek Vasut if (data->flags & MMC_DATA_READ) { 20171a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_READ; 202c7527b70SMarek Vasut } else if (priv->mmc_is_wp && 203c7527b70SMarek Vasut priv->mmc_is_wp(mmc->block_dev.dev)) { 20471a758e1SMarek Vasut printf("MMC%d: Can not write a locked card!\n", 20571a758e1SMarek Vasut mmc->block_dev.dev); 20671a758e1SMarek Vasut return UNUSABLE_ERR; 20771a758e1SMarek Vasut } 20871a758e1SMarek Vasut 20971a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_DATA_XFER; 21071a758e1SMarek Vasut reg = ((data->blocks - 1) << 21171a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | 21271a758e1SMarek Vasut ((ffs(data->blocksize) - 1) << 21371a758e1SMarek Vasut SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); 21471a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_block_size); 21571a758e1SMarek Vasut 21671a758e1SMarek Vasut reg = data->blocksize * data->blocks; 21771a758e1SMarek Vasut writel(reg, &ssp_regs->hw_ssp_xfer_size); 21871a758e1SMarek Vasut } 21971a758e1SMarek Vasut 22071a758e1SMarek Vasut /* Kick off the command */ 22171a758e1SMarek Vasut ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; 22271a758e1SMarek Vasut writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); 22371a758e1SMarek Vasut 22471a758e1SMarek Vasut /* Wait for the command to complete */ 22571a758e1SMarek Vasut timeout = MXSMMC_MAX_TIMEOUT; 22671a758e1SMarek Vasut while (--timeout) { 22771a758e1SMarek Vasut udelay(1000); 22871a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 22971a758e1SMarek Vasut if (!(reg & SSP_STATUS_CMD_BUSY)) 23071a758e1SMarek Vasut break; 23171a758e1SMarek Vasut } 23271a758e1SMarek Vasut 23371a758e1SMarek Vasut if (!timeout) { 23471a758e1SMarek Vasut printf("MMC%d: Command %d busy\n", 23571a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx); 23671a758e1SMarek Vasut return TIMEOUT; 23771a758e1SMarek Vasut } 23871a758e1SMarek Vasut 23971a758e1SMarek Vasut /* Check command timeout */ 24071a758e1SMarek Vasut if (reg & SSP_STATUS_RESP_TIMEOUT) { 24171a758e1SMarek Vasut printf("MMC%d: Command %d timeout (status 0x%08x)\n", 24271a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 24371a758e1SMarek Vasut return TIMEOUT; 24471a758e1SMarek Vasut } 24571a758e1SMarek Vasut 24671a758e1SMarek Vasut /* Check command errors */ 24771a758e1SMarek Vasut if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { 24871a758e1SMarek Vasut printf("MMC%d: Command %d error (status 0x%08x)!\n", 24971a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 25071a758e1SMarek Vasut return COMM_ERR; 25171a758e1SMarek Vasut } 25271a758e1SMarek Vasut 25371a758e1SMarek Vasut /* Copy response to response buffer */ 25471a758e1SMarek Vasut if (cmd->resp_type & MMC_RSP_136) { 25571a758e1SMarek Vasut cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); 25671a758e1SMarek Vasut cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); 25771a758e1SMarek Vasut cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); 25871a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); 25971a758e1SMarek Vasut } else 26071a758e1SMarek Vasut cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); 26171a758e1SMarek Vasut 26271a758e1SMarek Vasut /* Return if no data to process */ 26371a758e1SMarek Vasut if (!data) 26471a758e1SMarek Vasut return 0; 26571a758e1SMarek Vasut 266*20255900SMarek Vasut if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { 267401650a1SMarek Vasut writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); 268401650a1SMarek Vasut 26986983328SMarek Vasut ret = mxsmmc_send_cmd_dma(priv, data); 27086983328SMarek Vasut if (ret) { 271*20255900SMarek Vasut printf("MMC%d: DMA transfer failed\n", 272*20255900SMarek Vasut mmc->block_dev.dev); 27386983328SMarek Vasut return ret; 2743687c415SMarek Vasut } 275*20255900SMarek Vasut } else { 276401650a1SMarek Vasut writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); 277401650a1SMarek Vasut 27886983328SMarek Vasut ret = mxsmmc_send_cmd_pio(priv, data); 27986983328SMarek Vasut if (ret) { 280*20255900SMarek Vasut printf("MMC%d: Data timeout with command %d " 281*20255900SMarek Vasut "(status 0x%08x)!\n", 2824cc76c60SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 28386983328SMarek Vasut return ret; 2844cc76c60SMarek Vasut } 285*20255900SMarek Vasut } 2863687c415SMarek Vasut 28771a758e1SMarek Vasut /* Check data errors */ 28871a758e1SMarek Vasut reg = readl(&ssp_regs->hw_ssp_status); 28971a758e1SMarek Vasut if (reg & 29071a758e1SMarek Vasut (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | 29171a758e1SMarek Vasut SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { 29271a758e1SMarek Vasut printf("MMC%d: Data error with command %d (status 0x%08x)!\n", 29371a758e1SMarek Vasut mmc->block_dev.dev, cmd->cmdidx, reg); 29471a758e1SMarek Vasut return COMM_ERR; 29571a758e1SMarek Vasut } 29671a758e1SMarek Vasut 29771a758e1SMarek Vasut return 0; 29871a758e1SMarek Vasut } 29971a758e1SMarek Vasut 30071a758e1SMarek Vasut static void mxsmmc_set_ios(struct mmc *mmc) 30171a758e1SMarek Vasut { 30271a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 3039c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 30471a758e1SMarek Vasut 30571a758e1SMarek Vasut /* Set the clock speed */ 30671a758e1SMarek Vasut if (mmc->clock) 30771a758e1SMarek Vasut mx28_set_ssp_busclock(priv->id, mmc->clock / 1000); 30871a758e1SMarek Vasut 30971a758e1SMarek Vasut switch (mmc->bus_width) { 31071a758e1SMarek Vasut case 1: 31171a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT; 31271a758e1SMarek Vasut break; 31371a758e1SMarek Vasut case 4: 31471a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT; 31571a758e1SMarek Vasut break; 31671a758e1SMarek Vasut case 8: 31771a758e1SMarek Vasut priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT; 31871a758e1SMarek Vasut break; 31971a758e1SMarek Vasut } 32071a758e1SMarek Vasut 32171a758e1SMarek Vasut /* Set the bus width */ 32271a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0, 32371a758e1SMarek Vasut SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth); 32471a758e1SMarek Vasut 32571a758e1SMarek Vasut debug("MMC%d: Set %d bits bus width\n", 32671a758e1SMarek Vasut mmc->block_dev.dev, mmc->bus_width); 32771a758e1SMarek Vasut } 32871a758e1SMarek Vasut 32971a758e1SMarek Vasut static int mxsmmc_init(struct mmc *mmc) 33071a758e1SMarek Vasut { 33171a758e1SMarek Vasut struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 3329c471142SOtavio Salvador struct mxs_ssp_regs *ssp_regs = priv->regs; 33371a758e1SMarek Vasut 33471a758e1SMarek Vasut /* Reset SSP */ 33571a758e1SMarek Vasut mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); 33671a758e1SMarek Vasut 33771a758e1SMarek Vasut /* 8 bits word length in MMC mode */ 33871a758e1SMarek Vasut clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 33971a758e1SMarek Vasut SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK, 3403687c415SMarek Vasut SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | 3413687c415SMarek Vasut SSP_CTRL1_DMA_ENABLE); 34271a758e1SMarek Vasut 34371a758e1SMarek Vasut /* Set initial bit clock 400 KHz */ 34471a758e1SMarek Vasut mx28_set_ssp_busclock(priv->id, 400); 34571a758e1SMarek Vasut 34671a758e1SMarek Vasut /* Send initial 74 clock cycles (185 us @ 400 KHz)*/ 34771a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set); 34871a758e1SMarek Vasut udelay(200); 34971a758e1SMarek Vasut writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr); 35071a758e1SMarek Vasut 35171a758e1SMarek Vasut return 0; 35271a758e1SMarek Vasut } 35371a758e1SMarek Vasut 35471a758e1SMarek Vasut int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) 35571a758e1SMarek Vasut { 3569c471142SOtavio Salvador struct mxs_clkctrl_regs *clkctrl_regs = 3579c471142SOtavio Salvador (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 35871a758e1SMarek Vasut struct mmc *mmc = NULL; 35971a758e1SMarek Vasut struct mxsmmc_priv *priv = NULL; 36096666a39SMarek Vasut int ret; 36171a758e1SMarek Vasut 36271a758e1SMarek Vasut mmc = malloc(sizeof(struct mmc)); 36371a758e1SMarek Vasut if (!mmc) 36471a758e1SMarek Vasut return -ENOMEM; 36571a758e1SMarek Vasut 36671a758e1SMarek Vasut priv = malloc(sizeof(struct mxsmmc_priv)); 36771a758e1SMarek Vasut if (!priv) { 36871a758e1SMarek Vasut free(mmc); 36971a758e1SMarek Vasut return -ENOMEM; 37071a758e1SMarek Vasut } 37171a758e1SMarek Vasut 3723687c415SMarek Vasut priv->desc = mxs_dma_desc_alloc(); 3733687c415SMarek Vasut if (!priv->desc) { 3743687c415SMarek Vasut free(priv); 3753687c415SMarek Vasut free(mmc); 3763687c415SMarek Vasut return -ENOMEM; 3773687c415SMarek Vasut } 3783687c415SMarek Vasut 37996666a39SMarek Vasut ret = mxs_dma_init_channel(id); 38096666a39SMarek Vasut if (ret) 38196666a39SMarek Vasut return ret; 38296666a39SMarek Vasut 38371a758e1SMarek Vasut priv->mmc_is_wp = wp; 38471a758e1SMarek Vasut priv->id = id; 38571a758e1SMarek Vasut switch (id) { 38671a758e1SMarek Vasut case 0: 3879c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE; 38871a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; 38971a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; 39071a758e1SMarek Vasut break; 39171a758e1SMarek Vasut case 1: 3929c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE; 39371a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; 39471a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; 39571a758e1SMarek Vasut break; 39671a758e1SMarek Vasut case 2: 3979c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE; 39871a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; 39971a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; 40071a758e1SMarek Vasut break; 40171a758e1SMarek Vasut case 3: 4029c471142SOtavio Salvador priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE; 40371a758e1SMarek Vasut priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; 40471a758e1SMarek Vasut priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; 40571a758e1SMarek Vasut break; 40671a758e1SMarek Vasut } 40771a758e1SMarek Vasut 40871a758e1SMarek Vasut sprintf(mmc->name, "MXS MMC"); 40971a758e1SMarek Vasut mmc->send_cmd = mxsmmc_send_cmd; 41071a758e1SMarek Vasut mmc->set_ios = mxsmmc_set_ios; 41171a758e1SMarek Vasut mmc->init = mxsmmc_init; 41248972d90SThierry Reding mmc->getcd = NULL; 41371a758e1SMarek Vasut mmc->priv = priv; 41471a758e1SMarek Vasut 41571a758e1SMarek Vasut mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 41671a758e1SMarek Vasut 41771a758e1SMarek Vasut mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | 41871a758e1SMarek Vasut MMC_MODE_HS_52MHz | MMC_MODE_HS; 41971a758e1SMarek Vasut 42071a758e1SMarek Vasut /* 42171a758e1SMarek Vasut * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz 42271a758e1SMarek Vasut * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), 42371a758e1SMarek Vasut * CLOCK_DIVIDE has to be an even value from 2 to 254, and 42471a758e1SMarek Vasut * CLOCK_RATE could be any integer from 0 to 255. 42571a758e1SMarek Vasut */ 42671a758e1SMarek Vasut mmc->f_min = 400000; 42771a758e1SMarek Vasut mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; 428e7205905SMarek Vasut mmc->b_max = 0x20; 42971a758e1SMarek Vasut 43071a758e1SMarek Vasut mmc_register(mmc); 43171a758e1SMarek Vasut return 0; 43271a758e1SMarek Vasut } 433