1 /* 2 * Marvell MMC/SD/SDIO driver 3 * 4 * (C) Copyright 2012 5 * Marvell Semiconductor <www.marvell.com> 6 * Written-by: Maen Suleiman, Gerald Kerma 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <part.h> 14 #include <mmc.h> 15 #include <asm/io.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/kirkwood.h> 18 #include <mvebu_mmc.h> 19 20 #define DRIVER_NAME "MVEBU_MMC" 21 22 static void mvebu_mmc_write(u32 offs, u32 val) 23 { 24 writel(val, CONFIG_SYS_MMC_BASE + (offs)); 25 } 26 27 static u32 mvebu_mmc_read(u32 offs) 28 { 29 return readl(CONFIG_SYS_MMC_BASE + (offs)); 30 } 31 32 static int mvebu_mmc_setup_data(struct mmc_data *data) 33 { 34 u32 ctrl_reg; 35 36 debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME, 37 (data->flags & MMC_DATA_READ) ? "read" : "write", 38 data->blocks, data->blocksize); 39 40 /* default to maximum timeout */ 41 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL); 42 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); 43 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg); 44 45 if (data->flags & MMC_DATA_READ) { 46 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff); 47 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16); 48 } else { 49 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff); 50 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16); 51 } 52 53 mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks); 54 mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize); 55 56 return 0; 57 } 58 59 static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 60 struct mmc_data *data) 61 { 62 int timeout = 10; 63 ushort waittype = 0; 64 ushort resptype = 0; 65 ushort xfertype = 0; 66 ushort resp_indx = 0; 67 68 debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", 69 cmd->cmdidx, cmd->resp_type, cmd->cmdarg); 70 71 udelay(10*1000); 72 73 debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME, 74 cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE)); 75 76 /* Checking if card is busy */ 77 while ((mvebu_mmc_read(SDIO_HW_STATE) & CARD_BUSY)) { 78 if (timeout == 0) { 79 printf("%s: card busy!\n", DRIVER_NAME); 80 return -1; 81 } 82 timeout--; 83 udelay(1000); 84 } 85 86 /* Set up for a data transfer if we have one */ 87 if (data) { 88 int err = mvebu_mmc_setup_data(data); 89 90 if (err) 91 return err; 92 } 93 94 resptype = SDIO_CMD_INDEX(cmd->cmdidx); 95 96 /* Analyzing resptype/xfertype/waittype for the command */ 97 if (cmd->resp_type & MMC_RSP_BUSY) 98 resptype |= SDIO_CMD_RSP_48BUSY; 99 else if (cmd->resp_type & MMC_RSP_136) 100 resptype |= SDIO_CMD_RSP_136; 101 else if (cmd->resp_type & MMC_RSP_PRESENT) 102 resptype |= SDIO_CMD_RSP_48; 103 else 104 resptype |= SDIO_CMD_RSP_NONE; 105 106 if (cmd->resp_type & MMC_RSP_CRC) 107 resptype |= SDIO_CMD_CHECK_CMDCRC; 108 109 if (cmd->resp_type & MMC_RSP_OPCODE) 110 resptype |= SDIO_CMD_INDX_CHECK; 111 112 if (cmd->resp_type & MMC_RSP_PRESENT) { 113 resptype |= SDIO_UNEXPECTED_RESP; 114 waittype |= SDIO_NOR_UNEXP_RSP; 115 } 116 117 if (data) { 118 resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16; 119 xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN; 120 if (data->flags & MMC_DATA_READ) { 121 xfertype |= SDIO_XFER_MODE_TO_HOST; 122 waittype = SDIO_NOR_DMA_INI; 123 } else { 124 waittype |= SDIO_NOR_XFER_DONE; 125 } 126 } else { 127 waittype |= SDIO_NOR_CMD_DONE; 128 } 129 130 /* Setting cmd arguments */ 131 mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff); 132 mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16); 133 134 /* Setting Xfer mode */ 135 mvebu_mmc_write(SDIO_XFER_MODE, xfertype); 136 137 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT); 138 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); 139 140 /* Sending command */ 141 mvebu_mmc_write(SDIO_CMD, resptype); 142 143 mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK); 144 mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK); 145 146 /* Waiting for completion */ 147 timeout = 1000000; 148 149 while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) { 150 if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) { 151 debug("%s: error! cmdidx : %d, err reg: %04x\n", 152 DRIVER_NAME, cmd->cmdidx, 153 mvebu_mmc_read(SDIO_ERR_INTR_STATUS)); 154 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) & 155 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) 156 return TIMEOUT; 157 return COMM_ERR; 158 } 159 160 timeout--; 161 udelay(1); 162 if (timeout <= 0) { 163 printf("%s: command timed out\n", DRIVER_NAME); 164 return TIMEOUT; 165 } 166 } 167 168 /* Handling response */ 169 if (cmd->resp_type & MMC_RSP_136) { 170 uint response[8]; 171 172 for (resp_indx = 0; resp_indx < 8; resp_indx++) 173 response[resp_indx] 174 = mvebu_mmc_read(SDIO_RSP(resp_indx)); 175 176 cmd->response[0] = ((response[0] & 0x03ff) << 22) | 177 ((response[1] & 0xffff) << 6) | 178 ((response[2] & 0xfc00) >> 10); 179 cmd->response[1] = ((response[2] & 0x03ff) << 22) | 180 ((response[3] & 0xffff) << 6) | 181 ((response[4] & 0xfc00) >> 10); 182 cmd->response[2] = ((response[4] & 0x03ff) << 22) | 183 ((response[5] & 0xffff) << 6) | 184 ((response[6] & 0xfc00) >> 10); 185 cmd->response[3] = ((response[6] & 0x03ff) << 22) | 186 ((response[7] & 0x3fff) << 8); 187 } else if (cmd->resp_type & MMC_RSP_PRESENT) { 188 uint response[3]; 189 190 for (resp_indx = 0; resp_indx < 3; resp_indx++) 191 response[resp_indx] 192 = mvebu_mmc_read(SDIO_RSP(resp_indx)); 193 194 cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) | 195 ((response[1] & 0xffff) << (14 - 8)) | 196 ((response[0] & 0x03ff) << (30 - 8)); 197 cmd->response[1] = ((response[0] & 0xfc00) >> 10); 198 cmd->response[2] = 0; 199 cmd->response[3] = 0; 200 } 201 202 debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type); 203 debug("[0x%x] ", cmd->response[0]); 204 debug("[0x%x] ", cmd->response[1]); 205 debug("[0x%x] ", cmd->response[2]); 206 debug("[0x%x] ", cmd->response[3]); 207 debug("\n"); 208 209 return 0; 210 } 211 212 static void mvebu_mmc_power_up(void) 213 { 214 debug("%s: power up\n", DRIVER_NAME); 215 216 /* disable interrupts */ 217 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0); 218 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0); 219 220 /* SW reset */ 221 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); 222 223 mvebu_mmc_write(SDIO_XFER_MODE, 0); 224 225 /* enable status */ 226 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); 227 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); 228 229 /* enable interrupts status */ 230 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK); 231 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); 232 } 233 234 static void mvebu_mmc_set_clk(unsigned int clock) 235 { 236 unsigned int m; 237 238 if (clock == 0) { 239 debug("%s: clock off\n", DRIVER_NAME); 240 mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK); 241 mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX); 242 } else { 243 m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1; 244 if (m > MVEBU_MMC_BASE_DIV_MAX) 245 m = MVEBU_MMC_BASE_DIV_MAX; 246 mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX); 247 } 248 249 udelay(10*1000); 250 } 251 252 static void mvebu_mmc_set_bus(unsigned int bus) 253 { 254 u32 ctrl_reg = 0; 255 256 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL); 257 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; 258 259 switch (bus) { 260 case 4: 261 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; 262 break; 263 case 1: 264 default: 265 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT; 266 } 267 268 /* default transfer mode */ 269 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN; 270 ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST; 271 272 /* default to maximum timeout */ 273 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); 274 275 ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN; 276 277 ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY; 278 279 debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg, 280 (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ? 281 "push-pull" : "open-drain", 282 (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ? 283 "4bit-width" : "1bit-width", 284 (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ? 285 "high-speed" : ""); 286 287 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg); 288 udelay(10*1000); 289 } 290 291 static void mvebu_mmc_set_ios(struct mmc *mmc) 292 { 293 debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME, 294 mmc->bus_width, mmc->clock); 295 mvebu_mmc_set_bus(mmc->bus_width); 296 mvebu_mmc_set_clk(mmc->clock); 297 } 298 299 static int mvebu_mmc_initialize(struct mmc *mmc) 300 { 301 debug("%s: mvebu_mmc_initialize", DRIVER_NAME); 302 303 /* 304 * Setting host parameters 305 * Initial Host Ctrl : Timeout : max , Normal Speed mode, 306 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line 307 */ 308 mvebu_mmc_write(SDIO_HOST_CTRL, 309 SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) | 310 SDIO_HOST_CTRL_DATA_WIDTH_4_BITS | 311 SDIO_HOST_CTRL_BIG_ENDIAN | 312 SDIO_HOST_CTRL_PUSH_PULL_EN | 313 SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY); 314 315 mvebu_mmc_write(SDIO_CLK_CTRL, 0); 316 317 /* enable status */ 318 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); 319 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); 320 321 /* disable interrupts */ 322 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0); 323 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0); 324 325 /* SW reset */ 326 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); 327 328 udelay(10*1000); 329 330 return 0; 331 } 332 333 static const struct mmc_ops mvebu_mmc_ops = { 334 .send_cmd = mvebu_mmc_send_cmd, 335 .set_ios = mvebu_mmc_set_ios, 336 .init = mvebu_mmc_initialize, 337 }; 338 339 static struct mmc_config mvebu_mmc_cfg = { 340 .name = DRIVER_NAME, 341 .ops = &mvebu_mmc_ops, 342 .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX, 343 .f_max = MVEBU_MMC_CLOCKRATE_MAX, 344 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, 345 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS, 346 .part_type = PART_TYPE_DOS, 347 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 348 }; 349 350 int mvebu_mmc_init(bd_t *bis) 351 { 352 struct mmc *mmc; 353 354 mvebu_mmc_power_up(); 355 356 mmc = mmc_create(&mvebu_mmc_cfg, bis); 357 if (mmc == NULL) 358 return -1; 359 360 return 0; 361 } 362