1 /* 2 * Marvell MMC/SD/SDIO driver 3 * 4 * (C) Copyright 2012 5 * Marvell Semiconductor <www.marvell.com> 6 * Written-by: Maen Suleiman, Gerald Kerma 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <part.h> 14 #include <mmc.h> 15 #include <asm/io.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/kirkwood.h> 18 #include <mvebu_mmc.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define DRIVER_NAME "MVEBU_MMC" 23 24 #define MVEBU_TARGET_DRAM 0 25 26 static void mvebu_mmc_write(u32 offs, u32 val) 27 { 28 writel(val, CONFIG_SYS_MMC_BASE + (offs)); 29 } 30 31 static u32 mvebu_mmc_read(u32 offs) 32 { 33 return readl(CONFIG_SYS_MMC_BASE + (offs)); 34 } 35 36 static int mvebu_mmc_setup_data(struct mmc_data *data) 37 { 38 u32 ctrl_reg; 39 40 debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME, 41 (data->flags & MMC_DATA_READ) ? "read" : "write", 42 data->blocks, data->blocksize); 43 44 /* default to maximum timeout */ 45 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL); 46 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); 47 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg); 48 49 if (data->flags & MMC_DATA_READ) { 50 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff); 51 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16); 52 } else { 53 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff); 54 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16); 55 } 56 57 mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks); 58 mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize); 59 60 return 0; 61 } 62 63 static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 64 struct mmc_data *data) 65 { 66 int timeout = 10; 67 ushort waittype = 0; 68 ushort resptype = 0; 69 ushort xfertype = 0; 70 ushort resp_indx = 0; 71 72 debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", 73 cmd->cmdidx, cmd->resp_type, cmd->cmdarg); 74 75 udelay(10*1000); 76 77 debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME, 78 cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE)); 79 80 /* Checking if card is busy */ 81 while ((mvebu_mmc_read(SDIO_HW_STATE) & CARD_BUSY)) { 82 if (timeout == 0) { 83 printf("%s: card busy!\n", DRIVER_NAME); 84 return -1; 85 } 86 timeout--; 87 udelay(1000); 88 } 89 90 /* Set up for a data transfer if we have one */ 91 if (data) { 92 int err = mvebu_mmc_setup_data(data); 93 94 if (err) 95 return err; 96 } 97 98 resptype = SDIO_CMD_INDEX(cmd->cmdidx); 99 100 /* Analyzing resptype/xfertype/waittype for the command */ 101 if (cmd->resp_type & MMC_RSP_BUSY) 102 resptype |= SDIO_CMD_RSP_48BUSY; 103 else if (cmd->resp_type & MMC_RSP_136) 104 resptype |= SDIO_CMD_RSP_136; 105 else if (cmd->resp_type & MMC_RSP_PRESENT) 106 resptype |= SDIO_CMD_RSP_48; 107 else 108 resptype |= SDIO_CMD_RSP_NONE; 109 110 if (cmd->resp_type & MMC_RSP_CRC) 111 resptype |= SDIO_CMD_CHECK_CMDCRC; 112 113 if (cmd->resp_type & MMC_RSP_OPCODE) 114 resptype |= SDIO_CMD_INDX_CHECK; 115 116 if (cmd->resp_type & MMC_RSP_PRESENT) { 117 resptype |= SDIO_UNEXPECTED_RESP; 118 waittype |= SDIO_NOR_UNEXP_RSP; 119 } 120 121 if (data) { 122 resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16; 123 xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN; 124 if (data->flags & MMC_DATA_READ) { 125 xfertype |= SDIO_XFER_MODE_TO_HOST; 126 waittype = SDIO_NOR_DMA_INI; 127 } else { 128 waittype |= SDIO_NOR_XFER_DONE; 129 } 130 } else { 131 waittype |= SDIO_NOR_CMD_DONE; 132 } 133 134 /* Setting cmd arguments */ 135 mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff); 136 mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16); 137 138 /* Setting Xfer mode */ 139 mvebu_mmc_write(SDIO_XFER_MODE, xfertype); 140 141 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT); 142 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); 143 144 /* Sending command */ 145 mvebu_mmc_write(SDIO_CMD, resptype); 146 147 mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK); 148 mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK); 149 150 /* Waiting for completion */ 151 timeout = 1000000; 152 153 while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) { 154 if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) { 155 debug("%s: error! cmdidx : %d, err reg: %04x\n", 156 DRIVER_NAME, cmd->cmdidx, 157 mvebu_mmc_read(SDIO_ERR_INTR_STATUS)); 158 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) & 159 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) 160 return TIMEOUT; 161 return COMM_ERR; 162 } 163 164 timeout--; 165 udelay(1); 166 if (timeout <= 0) { 167 printf("%s: command timed out\n", DRIVER_NAME); 168 return TIMEOUT; 169 } 170 } 171 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) & 172 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) 173 return TIMEOUT; 174 175 /* Handling response */ 176 if (cmd->resp_type & MMC_RSP_136) { 177 uint response[8]; 178 179 for (resp_indx = 0; resp_indx < 8; resp_indx++) 180 response[resp_indx] 181 = mvebu_mmc_read(SDIO_RSP(resp_indx)); 182 183 cmd->response[0] = ((response[0] & 0x03ff) << 22) | 184 ((response[1] & 0xffff) << 6) | 185 ((response[2] & 0xfc00) >> 10); 186 cmd->response[1] = ((response[2] & 0x03ff) << 22) | 187 ((response[3] & 0xffff) << 6) | 188 ((response[4] & 0xfc00) >> 10); 189 cmd->response[2] = ((response[4] & 0x03ff) << 22) | 190 ((response[5] & 0xffff) << 6) | 191 ((response[6] & 0xfc00) >> 10); 192 cmd->response[3] = ((response[6] & 0x03ff) << 22) | 193 ((response[7] & 0x3fff) << 8); 194 } else if (cmd->resp_type & MMC_RSP_PRESENT) { 195 uint response[3]; 196 197 for (resp_indx = 0; resp_indx < 3; resp_indx++) 198 response[resp_indx] 199 = mvebu_mmc_read(SDIO_RSP(resp_indx)); 200 201 cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) | 202 ((response[1] & 0xffff) << (14 - 8)) | 203 ((response[0] & 0x03ff) << (30 - 8)); 204 cmd->response[1] = ((response[0] & 0xfc00) >> 10); 205 cmd->response[2] = 0; 206 cmd->response[3] = 0; 207 } 208 209 debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type); 210 debug("[0x%x] ", cmd->response[0]); 211 debug("[0x%x] ", cmd->response[1]); 212 debug("[0x%x] ", cmd->response[2]); 213 debug("[0x%x] ", cmd->response[3]); 214 debug("\n"); 215 216 return 0; 217 } 218 219 static void mvebu_mmc_power_up(void) 220 { 221 debug("%s: power up\n", DRIVER_NAME); 222 223 /* disable interrupts */ 224 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0); 225 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0); 226 227 /* SW reset */ 228 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); 229 230 mvebu_mmc_write(SDIO_XFER_MODE, 0); 231 232 /* enable status */ 233 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); 234 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); 235 236 /* enable interrupts status */ 237 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK); 238 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); 239 } 240 241 static void mvebu_mmc_set_clk(unsigned int clock) 242 { 243 unsigned int m; 244 245 if (clock == 0) { 246 debug("%s: clock off\n", DRIVER_NAME); 247 mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK); 248 mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX); 249 } else { 250 m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1; 251 if (m > MVEBU_MMC_BASE_DIV_MAX) 252 m = MVEBU_MMC_BASE_DIV_MAX; 253 mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX); 254 } 255 256 udelay(10*1000); 257 } 258 259 static void mvebu_mmc_set_bus(unsigned int bus) 260 { 261 u32 ctrl_reg = 0; 262 263 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL); 264 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; 265 266 switch (bus) { 267 case 4: 268 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; 269 break; 270 case 1: 271 default: 272 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT; 273 } 274 275 /* default transfer mode */ 276 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN; 277 ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST; 278 279 /* default to maximum timeout */ 280 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); 281 ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN; 282 283 ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN; 284 285 ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY; 286 287 debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg, 288 (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ? 289 "push-pull" : "open-drain", 290 (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ? 291 "4bit-width" : "1bit-width", 292 (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ? 293 "high-speed" : ""); 294 295 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg); 296 udelay(10*1000); 297 } 298 299 static void mvebu_mmc_set_ios(struct mmc *mmc) 300 { 301 debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME, 302 mmc->bus_width, mmc->clock); 303 mvebu_mmc_set_bus(mmc->bus_width); 304 mvebu_mmc_set_clk(mmc->clock); 305 } 306 307 /* 308 * Set window register. 309 */ 310 static void mvebu_window_setup(void) 311 { 312 int i; 313 314 for (i = 0; i < 4; i++) { 315 mvebu_mmc_write(WINDOW_CTRL(i), 0); 316 mvebu_mmc_write(WINDOW_BASE(i), 0); 317 } 318 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 319 u32 size, base, attrib; 320 321 /* Enable DRAM bank */ 322 switch (i) { 323 case 0: 324 attrib = KWCPU_ATTR_DRAM_CS0; 325 break; 326 case 1: 327 attrib = KWCPU_ATTR_DRAM_CS1; 328 break; 329 case 2: 330 attrib = KWCPU_ATTR_DRAM_CS2; 331 break; 332 case 3: 333 attrib = KWCPU_ATTR_DRAM_CS3; 334 break; 335 default: 336 /* invalide bank, disable access */ 337 attrib = 0; 338 break; 339 } 340 341 size = gd->bd->bi_dram[i].size; 342 base = gd->bd->bi_dram[i].start; 343 if (size && attrib) { 344 mvebu_mmc_write(WINDOW_CTRL(i), 345 MVCPU_WIN_CTRL_DATA(size, 346 MVEBU_TARGET_DRAM, 347 attrib, 348 MVCPU_WIN_ENABLE)); 349 } else { 350 mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE); 351 } 352 mvebu_mmc_write(WINDOW_BASE(i), base); 353 } 354 } 355 356 static int mvebu_mmc_initialize(struct mmc *mmc) 357 { 358 debug("%s: mvebu_mmc_initialize", DRIVER_NAME); 359 360 /* 361 * Setting host parameters 362 * Initial Host Ctrl : Timeout : max , Normal Speed mode, 363 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line 364 */ 365 mvebu_mmc_write(SDIO_HOST_CTRL, 366 SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) | 367 SDIO_HOST_CTRL_DATA_WIDTH_4_BITS | 368 SDIO_HOST_CTRL_BIG_ENDIAN | 369 SDIO_HOST_CTRL_PUSH_PULL_EN | 370 SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY); 371 372 mvebu_mmc_write(SDIO_CLK_CTRL, 0); 373 374 /* enable status */ 375 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); 376 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); 377 378 /* disable interrupts */ 379 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0); 380 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0); 381 382 mvebu_window_setup(); 383 384 /* SW reset */ 385 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); 386 387 udelay(10*1000); 388 389 return 0; 390 } 391 392 static const struct mmc_ops mvebu_mmc_ops = { 393 .send_cmd = mvebu_mmc_send_cmd, 394 .set_ios = mvebu_mmc_set_ios, 395 .init = mvebu_mmc_initialize, 396 }; 397 398 static struct mmc_config mvebu_mmc_cfg = { 399 .name = DRIVER_NAME, 400 .ops = &mvebu_mmc_ops, 401 .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX, 402 .f_max = MVEBU_MMC_CLOCKRATE_MAX, 403 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, 404 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC | 405 MMC_MODE_HS_52MHz, 406 .part_type = PART_TYPE_DOS, 407 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 408 }; 409 410 int mvebu_mmc_init(bd_t *bis) 411 { 412 struct mmc *mmc; 413 414 mvebu_mmc_power_up(); 415 416 mmc = mmc_create(&mvebu_mmc_cfg, bis); 417 if (mmc == NULL) 418 return -1; 419 420 return 0; 421 } 422