1 /* 2 * Marvell SD Host Controller Interface 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <sdhci.h> 10 #include <linux/mbus.h> 11 12 #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4)) 13 #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4)) 14 15 static void sdhci_mvebu_mbus_config(void __iomem *base) 16 { 17 const struct mbus_dram_target_info *dram; 18 int i; 19 20 dram = mvebu_mbus_dram_info(); 21 22 for (i = 0; i < 4; i++) { 23 writel(0, base + SDHCI_WINDOW_CTRL(i)); 24 writel(0, base + SDHCI_WINDOW_BASE(i)); 25 } 26 27 for (i = 0; i < dram->num_cs; i++) { 28 const struct mbus_dram_window *cs = dram->cs + i; 29 30 /* Write size, attributes and target id to control register */ 31 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | 32 (dram->mbus_dram_target_id << 4) | 1, 33 base + SDHCI_WINDOW_CTRL(i)); 34 35 /* Write base address to base register */ 36 writel(cs->base, base + SDHCI_WINDOW_BASE(i)); 37 } 38 } 39 40 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 41 static struct sdhci_ops mv_ops; 42 43 #if defined(CONFIG_SHEEVA_88SV331xV5) 44 #define SD_CE_ATA_2 0xEA 45 #define MMC_CARD 0x1000 46 #define MMC_WIDTH 0x0100 47 static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 48 { 49 struct mmc *mmc = host->mmc; 50 u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2; 51 52 if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) { 53 if (mmc->bus_width == 8) 54 writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata); 55 else 56 writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata); 57 } 58 59 writeb(val, host->ioaddr + reg); 60 } 61 62 #else 63 #define mv_sdhci_writeb NULL 64 #endif /* CONFIG_SHEEVA_88SV331xV5 */ 65 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 66 67 static char *MVSDH_NAME = "mv_sdh"; 68 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) 69 { 70 struct sdhci_host *host = NULL; 71 host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); 72 if (!host) { 73 printf("sdh_host malloc fail!\n"); 74 return 1; 75 } 76 77 host->name = MVSDH_NAME; 78 host->ioaddr = (void *)regbase; 79 host->quirks = quirks; 80 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 81 memset(&mv_ops, 0, sizeof(struct sdhci_ops)); 82 mv_ops.write_b = mv_sdhci_writeb; 83 host->ops = &mv_ops; 84 #endif 85 86 if (CONFIG_IS_ENABLED(ARCH_MVEBU)) { 87 /* Configure SDHCI MBUS mbus bridge windows */ 88 sdhci_mvebu_mbus_config((void __iomem *)regbase); 89 } 90 91 if (quirks & SDHCI_QUIRK_REG32_RW) 92 host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; 93 else 94 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 95 return add_sdhci(host, max_clk, min_clk); 96 } 97