15b37212aSStefan Roese /* 25b37212aSStefan Roese * Marvell SD Host Controller Interface 35b37212aSStefan Roese * 45b37212aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 55b37212aSStefan Roese */ 65b37212aSStefan Roese 7e75787d9SLei Wen #include <common.h> 8e75787d9SLei Wen #include <malloc.h> 9e75787d9SLei Wen #include <sdhci.h> 105b37212aSStefan Roese #include <linux/mbus.h> 115b37212aSStefan Roese 125b37212aSStefan Roese #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4)) 135b37212aSStefan Roese #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4)) 145b37212aSStefan Roese 155b37212aSStefan Roese static void sdhci_mvebu_mbus_config(void __iomem *base) 165b37212aSStefan Roese { 175b37212aSStefan Roese const struct mbus_dram_target_info *dram; 185b37212aSStefan Roese int i; 195b37212aSStefan Roese 205b37212aSStefan Roese dram = mvebu_mbus_dram_info(); 215b37212aSStefan Roese 225b37212aSStefan Roese for (i = 0; i < 4; i++) { 235b37212aSStefan Roese writel(0, base + SDHCI_WINDOW_CTRL(i)); 245b37212aSStefan Roese writel(0, base + SDHCI_WINDOW_BASE(i)); 255b37212aSStefan Roese } 265b37212aSStefan Roese 275b37212aSStefan Roese for (i = 0; i < dram->num_cs; i++) { 285b37212aSStefan Roese const struct mbus_dram_window *cs = dram->cs + i; 295b37212aSStefan Roese 305b37212aSStefan Roese /* Write size, attributes and target id to control register */ 315b37212aSStefan Roese writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | 325b37212aSStefan Roese (dram->mbus_dram_target_id << 4) | 1, 335b37212aSStefan Roese base + SDHCI_WINDOW_CTRL(i)); 345b37212aSStefan Roese 355b37212aSStefan Roese /* Write base address to base register */ 365b37212aSStefan Roese writel(cs->base, base + SDHCI_WINDOW_BASE(i)); 375b37212aSStefan Roese } 385b37212aSStefan Roese } 39e75787d9SLei Wen 4002d3ad3eSLei Wen #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 4102d3ad3eSLei Wen static struct sdhci_ops mv_ops; 4202d3ad3eSLei Wen 4302d3ad3eSLei Wen #if defined(CONFIG_SHEEVA_88SV331xV5) 4402d3ad3eSLei Wen #define SD_CE_ATA_2 0xEA 4502d3ad3eSLei Wen #define MMC_CARD 0x1000 4602d3ad3eSLei Wen #define MMC_WIDTH 0x0100 4702d3ad3eSLei Wen static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 4802d3ad3eSLei Wen { 4902d3ad3eSLei Wen struct mmc *mmc = host->mmc; 503a48944bSRob Herring u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2; 5102d3ad3eSLei Wen 5202d3ad3eSLei Wen if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) { 5302d3ad3eSLei Wen if (mmc->bus_width == 8) 5402d3ad3eSLei Wen writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata); 5502d3ad3eSLei Wen else 5602d3ad3eSLei Wen writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata); 5702d3ad3eSLei Wen } 5802d3ad3eSLei Wen 5902d3ad3eSLei Wen writeb(val, host->ioaddr + reg); 6002d3ad3eSLei Wen } 6102d3ad3eSLei Wen 6202d3ad3eSLei Wen #else 6302d3ad3eSLei Wen #define mv_sdhci_writeb NULL 6402d3ad3eSLei Wen #endif /* CONFIG_SHEEVA_88SV331xV5 */ 6502d3ad3eSLei Wen #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 6602d3ad3eSLei Wen 67e75787d9SLei Wen static char *MVSDH_NAME = "mv_sdh"; 683a48944bSRob Herring int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) 69e75787d9SLei Wen { 70e75787d9SLei Wen struct sdhci_host *host = NULL; 71*ca4e7d67SMatt Pelland host = calloc(1, sizeof(*host)); 72e75787d9SLei Wen if (!host) { 73e75787d9SLei Wen printf("sdh_host malloc fail!\n"); 742cb5d67cSJaehoon Chung return -ENOMEM; 75e75787d9SLei Wen } 76e75787d9SLei Wen 77e75787d9SLei Wen host->name = MVSDH_NAME; 78e75787d9SLei Wen host->ioaddr = (void *)regbase; 79e75787d9SLei Wen host->quirks = quirks; 806d0e34bfSStefan Herbrechtsmeier host->max_clk = max_clk; 8102d3ad3eSLei Wen #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 8202d3ad3eSLei Wen memset(&mv_ops, 0, sizeof(struct sdhci_ops)); 8302d3ad3eSLei Wen mv_ops.write_b = mv_sdhci_writeb; 8402d3ad3eSLei Wen host->ops = &mv_ops; 8502d3ad3eSLei Wen #endif 865b37212aSStefan Roese 875b37212aSStefan Roese if (CONFIG_IS_ENABLED(ARCH_MVEBU)) { 885b37212aSStefan Roese /* Configure SDHCI MBUS mbus bridge windows */ 895b37212aSStefan Roese sdhci_mvebu_mbus_config((void __iomem *)regbase); 905b37212aSStefan Roese } 915b37212aSStefan Roese 926d0e34bfSStefan Herbrechtsmeier return add_sdhci(host, 0, min_clk); 93e75787d9SLei Wen } 94