1 /* 2 * Qualcomm SDHCI driver - SD/eMMC controller 3 * 4 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> 5 * 6 * Based on Linux driver 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <sdhci.h> 15 #include <wait_bit.h> 16 #include <asm/io.h> 17 #include <linux/bitops.h> 18 19 /* Non-standard registers needed for SDHCI startup */ 20 #define SDCC_MCI_POWER 0x0 21 #define SDCC_MCI_POWER_SW_RST BIT(7) 22 23 /* This is undocumented register */ 24 #define SDCC_MCI_VERSION 0x50 25 #define SDCC_MCI_VERSION_MAJOR_SHIFT 28 26 #define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT) 27 #define SDCC_MCI_VERSION_MINOR_MASK 0xff 28 29 #define SDCC_MCI_STATUS2 0x6C 30 #define SDCC_MCI_STATUS2_MCI_ACT 0x1 31 #define SDCC_MCI_HC_MODE 0x78 32 33 /* Offset to SDHCI registers */ 34 #define SDCC_SDHCI_OFFSET 0x900 35 36 /* Non standard (?) SDHCI register */ 37 #define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c 38 39 struct msm_sdhc { 40 struct sdhci_host host; 41 void *base; 42 }; 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 static int msm_sdc_clk_init(struct udevice *dev) 47 { 48 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, 49 "clock-frequency", 400000); 50 uint clkd[2]; /* clk_id and clk_no */ 51 int clk_offset; 52 struct udevice *clk_dev; 53 struct clk clk; 54 int ret; 55 56 ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, 57 2); 58 if (ret) 59 return ret; 60 61 clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); 62 if (clk_offset < 0) 63 return clk_offset; 64 65 ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev); 66 if (ret) 67 return ret; 68 69 clk.id = clkd[1]; 70 ret = clk_request(clk_dev, &clk); 71 if (ret < 0) 72 return ret; 73 74 ret = clk_set_rate(&clk, clk_rate); 75 clk_free(&clk); 76 if (ret < 0) 77 return ret; 78 79 return 0; 80 } 81 82 static int msm_sdc_probe(struct udevice *dev) 83 { 84 struct msm_sdhc *prv = dev_get_priv(dev); 85 struct sdhci_host *host = &prv->host; 86 u32 core_version, core_minor, core_major; 87 int ret; 88 89 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; 90 91 /* Init clocks */ 92 ret = msm_sdc_clk_init(dev); 93 if (ret) 94 return ret; 95 96 /* Reset the core and Enable SDHC mode */ 97 writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST, 98 prv->base + SDCC_MCI_POWER); 99 100 101 /* Wait for reset to be written to register */ 102 if (wait_for_bit(__func__, prv->base + SDCC_MCI_STATUS2, 103 SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) { 104 printf("msm_sdhci: reset request failed\n"); 105 return -EIO; 106 } 107 108 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ 109 if (wait_for_bit(__func__, prv->base + SDCC_MCI_POWER, 110 SDCC_MCI_POWER_SW_RST, false, 2, false)) { 111 printf("msm_sdhci: stuck in reset\n"); 112 return -ETIMEDOUT; 113 } 114 115 /* Enable host-controller mode */ 116 writel(1, prv->base + SDCC_MCI_HC_MODE); 117 118 core_version = readl(prv->base + SDCC_MCI_VERSION); 119 120 core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK); 121 core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT; 122 123 core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK; 124 125 /* 126 * Support for some capabilities is not advertised by newer 127 * controller versions and must be explicitly enabled. 128 */ 129 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { 130 u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES); 131 caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; 132 writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); 133 } 134 135 /* Set host controller version */ 136 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 137 138 /* automatically detect max and min speed */ 139 ret = add_sdhci(host, 0, 0); 140 if (ret) 141 return ret; 142 host->mmc->dev = dev; 143 144 return 0; 145 } 146 147 static int msm_sdc_remove(struct udevice *dev) 148 { 149 struct msm_sdhc *priv = dev_get_priv(dev); 150 151 /* Disable host-controller mode */ 152 writel(0, priv->base + SDCC_MCI_HC_MODE); 153 154 return 0; 155 } 156 157 static int msm_ofdata_to_platdata(struct udevice *dev) 158 { 159 struct udevice *parent = dev->parent; 160 struct msm_sdhc *priv = dev_get_priv(dev); 161 struct sdhci_host *host = &priv->host; 162 163 host->name = strdup(dev->name); 164 host->ioaddr = (void *)dev_get_addr(dev); 165 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 166 "bus-width", 4); 167 host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0); 168 priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob, 169 parent->of_offset, 170 dev->of_offset, 171 "reg", 1, NULL); 172 if (priv->base == (void *)FDT_ADDR_T_NONE || 173 host->ioaddr == (void *)FDT_ADDR_T_NONE) 174 return -EINVAL; 175 176 return 0; 177 } 178 179 static const struct udevice_id msm_mmc_ids[] = { 180 { .compatible = "qcom,sdhci-msm-v4" }, 181 { } 182 }; 183 184 U_BOOT_DRIVER(msm_sdc_drv) = { 185 .name = "msm_sdc", 186 .id = UCLASS_MMC, 187 .of_match = msm_mmc_ids, 188 .ofdata_to_platdata = msm_ofdata_to_platdata, 189 .probe = msm_sdc_probe, 190 .remove = msm_sdc_remove, 191 .priv_auto_alloc_size = sizeof(struct msm_sdhc), 192 }; 193