1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include "mmc_private.h" 23 24 static struct list_head mmc_devices; 25 static int cur_dev_num = -1; 26 27 __weak int board_mmc_getwp(struct mmc *mmc) 28 { 29 return -1; 30 } 31 32 int mmc_getwp(struct mmc *mmc) 33 { 34 int wp; 35 36 wp = board_mmc_getwp(mmc); 37 38 if (wp < 0) { 39 if (mmc->cfg->ops->getwp) 40 wp = mmc->cfg->ops->getwp(mmc); 41 else 42 wp = 0; 43 } 44 45 return wp; 46 } 47 48 __weak int board_mmc_getcd(struct mmc *mmc) 49 { 50 return -1; 51 } 52 53 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 54 { 55 int ret; 56 57 #ifdef CONFIG_MMC_TRACE 58 int i; 59 u8 *ptr; 60 61 printf("CMD_SEND:%d\n", cmd->cmdidx); 62 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 63 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 64 switch (cmd->resp_type) { 65 case MMC_RSP_NONE: 66 printf("\t\tMMC_RSP_NONE\n"); 67 break; 68 case MMC_RSP_R1: 69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 70 cmd->response[0]); 71 break; 72 case MMC_RSP_R1b: 73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 74 cmd->response[0]); 75 break; 76 case MMC_RSP_R2: 77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 78 cmd->response[0]); 79 printf("\t\t \t\t 0x%08X \n", 80 cmd->response[1]); 81 printf("\t\t \t\t 0x%08X \n", 82 cmd->response[2]); 83 printf("\t\t \t\t 0x%08X \n", 84 cmd->response[3]); 85 printf("\n"); 86 printf("\t\t\t\t\tDUMPING DATA\n"); 87 for (i = 0; i < 4; i++) { 88 int j; 89 printf("\t\t\t\t\t%03d - ", i*4); 90 ptr = (u8 *)&cmd->response[i]; 91 ptr += 3; 92 for (j = 0; j < 4; j++) 93 printf("%02X ", *ptr--); 94 printf("\n"); 95 } 96 break; 97 case MMC_RSP_R3: 98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 99 cmd->response[0]); 100 break; 101 default: 102 printf("\t\tERROR MMC rsp not supported\n"); 103 break; 104 } 105 #else 106 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 107 #endif 108 return ret; 109 } 110 111 int mmc_send_status(struct mmc *mmc, int timeout) 112 { 113 struct mmc_cmd cmd; 114 int err, retries = 5; 115 #ifdef CONFIG_MMC_TRACE 116 int status; 117 #endif 118 119 cmd.cmdidx = MMC_CMD_SEND_STATUS; 120 cmd.resp_type = MMC_RSP_R1; 121 if (!mmc_host_is_spi(mmc)) 122 cmd.cmdarg = mmc->rca << 16; 123 124 while (1) { 125 err = mmc_send_cmd(mmc, &cmd, NULL); 126 if (!err) { 127 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 128 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 129 MMC_STATE_PRG) 130 break; 131 else if (cmd.response[0] & MMC_STATUS_MASK) { 132 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 133 printf("Status Error: 0x%08X\n", 134 cmd.response[0]); 135 #endif 136 return COMM_ERR; 137 } 138 } else if (--retries < 0) 139 return err; 140 141 if (timeout-- <= 0) 142 break; 143 144 udelay(1000); 145 } 146 147 #ifdef CONFIG_MMC_TRACE 148 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 149 printf("CURR STATE:%d\n", status); 150 #endif 151 if (timeout <= 0) { 152 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 153 printf("Timeout waiting card ready\n"); 154 #endif 155 return TIMEOUT; 156 } 157 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) 158 return SWITCH_ERR; 159 160 return 0; 161 } 162 163 int mmc_set_blocklen(struct mmc *mmc, int len) 164 { 165 struct mmc_cmd cmd; 166 167 if (mmc->ddr_mode) 168 return 0; 169 170 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 171 cmd.resp_type = MMC_RSP_R1; 172 cmd.cmdarg = len; 173 174 return mmc_send_cmd(mmc, &cmd, NULL); 175 } 176 177 struct mmc *find_mmc_device(int dev_num) 178 { 179 struct mmc *m; 180 struct list_head *entry; 181 182 list_for_each(entry, &mmc_devices) { 183 m = list_entry(entry, struct mmc, link); 184 185 if (m->block_dev.dev == dev_num) 186 return m; 187 } 188 189 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 190 printf("MMC Device %d not found\n", dev_num); 191 #endif 192 193 return NULL; 194 } 195 196 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 197 lbaint_t blkcnt) 198 { 199 struct mmc_cmd cmd; 200 struct mmc_data data; 201 202 if (blkcnt > 1) 203 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 204 else 205 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 206 207 if (mmc->high_capacity) 208 cmd.cmdarg = start; 209 else 210 cmd.cmdarg = start * mmc->read_bl_len; 211 212 cmd.resp_type = MMC_RSP_R1; 213 214 data.dest = dst; 215 data.blocks = blkcnt; 216 data.blocksize = mmc->read_bl_len; 217 data.flags = MMC_DATA_READ; 218 219 if (mmc_send_cmd(mmc, &cmd, &data)) 220 return 0; 221 222 if (blkcnt > 1) { 223 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 224 cmd.cmdarg = 0; 225 cmd.resp_type = MMC_RSP_R1b; 226 if (mmc_send_cmd(mmc, &cmd, NULL)) { 227 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 228 printf("mmc fail to send stop cmd\n"); 229 #endif 230 return 0; 231 } 232 } 233 234 return blkcnt; 235 } 236 237 static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) 238 { 239 lbaint_t cur, blocks_todo = blkcnt; 240 241 if (blkcnt == 0) 242 return 0; 243 244 struct mmc *mmc = find_mmc_device(dev_num); 245 if (!mmc) 246 return 0; 247 248 if ((start + blkcnt) > mmc->block_dev.lba) { 249 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 250 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 251 start + blkcnt, mmc->block_dev.lba); 252 #endif 253 return 0; 254 } 255 256 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 257 debug("%s: Failed to set blocklen\n", __func__); 258 return 0; 259 } 260 261 do { 262 cur = (blocks_todo > mmc->cfg->b_max) ? 263 mmc->cfg->b_max : blocks_todo; 264 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 265 debug("%s: Failed to read blocks\n", __func__); 266 return 0; 267 } 268 blocks_todo -= cur; 269 start += cur; 270 dst += cur * mmc->read_bl_len; 271 } while (blocks_todo > 0); 272 273 return blkcnt; 274 } 275 276 static int mmc_go_idle(struct mmc *mmc) 277 { 278 struct mmc_cmd cmd; 279 int err; 280 281 udelay(1000); 282 283 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 284 cmd.cmdarg = 0; 285 cmd.resp_type = MMC_RSP_NONE; 286 287 err = mmc_send_cmd(mmc, &cmd, NULL); 288 289 if (err) 290 return err; 291 292 udelay(2000); 293 294 return 0; 295 } 296 297 static int sd_send_op_cond(struct mmc *mmc) 298 { 299 int timeout = 1000; 300 int err; 301 struct mmc_cmd cmd; 302 303 while (1) { 304 cmd.cmdidx = MMC_CMD_APP_CMD; 305 cmd.resp_type = MMC_RSP_R1; 306 cmd.cmdarg = 0; 307 308 err = mmc_send_cmd(mmc, &cmd, NULL); 309 310 if (err) 311 return err; 312 313 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 314 cmd.resp_type = MMC_RSP_R3; 315 316 /* 317 * Most cards do not answer if some reserved bits 318 * in the ocr are set. However, Some controller 319 * can set bit 7 (reserved for low voltages), but 320 * how to manage low voltages SD card is not yet 321 * specified. 322 */ 323 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 324 (mmc->cfg->voltages & 0xff8000); 325 326 if (mmc->version == SD_VERSION_2) 327 cmd.cmdarg |= OCR_HCS; 328 329 err = mmc_send_cmd(mmc, &cmd, NULL); 330 331 if (err) 332 return err; 333 334 if (cmd.response[0] & OCR_BUSY) 335 break; 336 337 if (timeout-- <= 0) 338 return UNUSABLE_ERR; 339 340 udelay(1000); 341 } 342 343 if (mmc->version != SD_VERSION_2) 344 mmc->version = SD_VERSION_1_0; 345 346 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 347 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 348 cmd.resp_type = MMC_RSP_R3; 349 cmd.cmdarg = 0; 350 351 err = mmc_send_cmd(mmc, &cmd, NULL); 352 353 if (err) 354 return err; 355 } 356 357 mmc->ocr = cmd.response[0]; 358 359 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 360 mmc->rca = 0; 361 362 return 0; 363 } 364 365 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 366 { 367 struct mmc_cmd cmd; 368 int err; 369 370 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 371 cmd.resp_type = MMC_RSP_R3; 372 cmd.cmdarg = 0; 373 if (use_arg && !mmc_host_is_spi(mmc)) 374 cmd.cmdarg = OCR_HCS | 375 (mmc->cfg->voltages & 376 (mmc->ocr & OCR_VOLTAGE_MASK)) | 377 (mmc->ocr & OCR_ACCESS_MODE); 378 379 err = mmc_send_cmd(mmc, &cmd, NULL); 380 if (err) 381 return err; 382 mmc->ocr = cmd.response[0]; 383 return 0; 384 } 385 386 static int mmc_send_op_cond(struct mmc *mmc) 387 { 388 int err, i; 389 390 /* Some cards seem to need this */ 391 mmc_go_idle(mmc); 392 393 /* Asking to the card its capabilities */ 394 for (i = 0; i < 2; i++) { 395 err = mmc_send_op_cond_iter(mmc, i != 0); 396 if (err) 397 return err; 398 399 /* exit if not busy (flag seems to be inverted) */ 400 if (mmc->ocr & OCR_BUSY) 401 break; 402 } 403 mmc->op_cond_pending = 1; 404 return 0; 405 } 406 407 static int mmc_complete_op_cond(struct mmc *mmc) 408 { 409 struct mmc_cmd cmd; 410 int timeout = 1000; 411 uint start; 412 int err; 413 414 mmc->op_cond_pending = 0; 415 if (!(mmc->ocr & OCR_BUSY)) { 416 start = get_timer(0); 417 while (1) { 418 err = mmc_send_op_cond_iter(mmc, 1); 419 if (err) 420 return err; 421 if (mmc->ocr & OCR_BUSY) 422 break; 423 if (get_timer(start) > timeout) 424 return UNUSABLE_ERR; 425 udelay(100); 426 } 427 } 428 429 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 430 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 431 cmd.resp_type = MMC_RSP_R3; 432 cmd.cmdarg = 0; 433 434 err = mmc_send_cmd(mmc, &cmd, NULL); 435 436 if (err) 437 return err; 438 439 mmc->ocr = cmd.response[0]; 440 } 441 442 mmc->version = MMC_VERSION_UNKNOWN; 443 444 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 445 mmc->rca = 1; 446 447 return 0; 448 } 449 450 451 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 452 { 453 struct mmc_cmd cmd; 454 struct mmc_data data; 455 int err; 456 457 /* Get the Card Status Register */ 458 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 459 cmd.resp_type = MMC_RSP_R1; 460 cmd.cmdarg = 0; 461 462 data.dest = (char *)ext_csd; 463 data.blocks = 1; 464 data.blocksize = MMC_MAX_BLOCK_LEN; 465 data.flags = MMC_DATA_READ; 466 467 err = mmc_send_cmd(mmc, &cmd, &data); 468 469 return err; 470 } 471 472 473 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 474 { 475 struct mmc_cmd cmd; 476 int timeout = 1000; 477 int ret; 478 479 cmd.cmdidx = MMC_CMD_SWITCH; 480 cmd.resp_type = MMC_RSP_R1b; 481 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 482 (index << 16) | 483 (value << 8); 484 485 ret = mmc_send_cmd(mmc, &cmd, NULL); 486 487 /* Waiting for the ready status */ 488 if (!ret) 489 ret = mmc_send_status(mmc, timeout); 490 491 return ret; 492 493 } 494 495 static int mmc_change_freq(struct mmc *mmc) 496 { 497 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 498 char cardtype; 499 int err; 500 501 mmc->card_caps = 0; 502 503 if (mmc_host_is_spi(mmc)) 504 return 0; 505 506 /* Only version 4 supports high-speed */ 507 if (mmc->version < MMC_VERSION_4) 508 return 0; 509 510 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 511 512 err = mmc_send_ext_csd(mmc, ext_csd); 513 514 if (err) 515 return err; 516 517 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 518 519 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 520 521 if (err) 522 return err == SWITCH_ERR ? 0 : err; 523 524 /* Now check to see that it worked */ 525 err = mmc_send_ext_csd(mmc, ext_csd); 526 527 if (err) 528 return err; 529 530 /* No high-speed support */ 531 if (!ext_csd[EXT_CSD_HS_TIMING]) 532 return 0; 533 534 /* High Speed is set, there are two types: 52MHz and 26MHz */ 535 if (cardtype & EXT_CSD_CARD_TYPE_52) { 536 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 537 mmc->card_caps |= MMC_MODE_DDR_52MHz; 538 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 539 } else { 540 mmc->card_caps |= MMC_MODE_HS; 541 } 542 543 return 0; 544 } 545 546 static int mmc_set_capacity(struct mmc *mmc, int part_num) 547 { 548 switch (part_num) { 549 case 0: 550 mmc->capacity = mmc->capacity_user; 551 break; 552 case 1: 553 case 2: 554 mmc->capacity = mmc->capacity_boot; 555 break; 556 case 3: 557 mmc->capacity = mmc->capacity_rpmb; 558 break; 559 case 4: 560 case 5: 561 case 6: 562 case 7: 563 mmc->capacity = mmc->capacity_gp[part_num - 4]; 564 break; 565 default: 566 return -1; 567 } 568 569 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 570 571 return 0; 572 } 573 574 int mmc_select_hwpart(int dev_num, int hwpart) 575 { 576 struct mmc *mmc = find_mmc_device(dev_num); 577 int ret; 578 579 if (!mmc) 580 return -ENODEV; 581 582 if (mmc->part_num == hwpart) 583 return 0; 584 585 if (mmc->part_config == MMCPART_NOAVAILABLE) { 586 printf("Card doesn't support part_switch\n"); 587 return -EMEDIUMTYPE; 588 } 589 590 ret = mmc_switch_part(dev_num, hwpart); 591 if (ret) 592 return ret; 593 594 mmc->part_num = hwpart; 595 596 return 0; 597 } 598 599 600 int mmc_switch_part(int dev_num, unsigned int part_num) 601 { 602 struct mmc *mmc = find_mmc_device(dev_num); 603 int ret; 604 605 if (!mmc) 606 return -1; 607 608 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 609 (mmc->part_config & ~PART_ACCESS_MASK) 610 | (part_num & PART_ACCESS_MASK)); 611 612 /* 613 * Set the capacity if the switch succeeded or was intended 614 * to return to representing the raw device. 615 */ 616 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) 617 ret = mmc_set_capacity(mmc, part_num); 618 619 return ret; 620 } 621 622 int mmc_hwpart_config(struct mmc *mmc, 623 const struct mmc_hwpart_conf *conf, 624 enum mmc_hwpart_conf_mode mode) 625 { 626 u8 part_attrs = 0; 627 u32 enh_size_mult; 628 u32 enh_start_addr; 629 u32 gp_size_mult[4]; 630 u32 max_enh_size_mult; 631 u32 tot_enh_size_mult = 0; 632 u8 wr_rel_set; 633 int i, pidx, err; 634 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 635 636 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 637 return -EINVAL; 638 639 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 640 printf("eMMC >= 4.4 required for enhanced user data area\n"); 641 return -EMEDIUMTYPE; 642 } 643 644 if (!(mmc->part_support & PART_SUPPORT)) { 645 printf("Card does not support partitioning\n"); 646 return -EMEDIUMTYPE; 647 } 648 649 if (!mmc->hc_wp_grp_size) { 650 printf("Card does not define HC WP group size\n"); 651 return -EMEDIUMTYPE; 652 } 653 654 /* check partition alignment and total enhanced size */ 655 if (conf->user.enh_size) { 656 if (conf->user.enh_size % mmc->hc_wp_grp_size || 657 conf->user.enh_start % mmc->hc_wp_grp_size) { 658 printf("User data enhanced area not HC WP group " 659 "size aligned\n"); 660 return -EINVAL; 661 } 662 part_attrs |= EXT_CSD_ENH_USR; 663 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 664 if (mmc->high_capacity) { 665 enh_start_addr = conf->user.enh_start; 666 } else { 667 enh_start_addr = (conf->user.enh_start << 9); 668 } 669 } else { 670 enh_size_mult = 0; 671 enh_start_addr = 0; 672 } 673 tot_enh_size_mult += enh_size_mult; 674 675 for (pidx = 0; pidx < 4; pidx++) { 676 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 677 printf("GP%i partition not HC WP group size " 678 "aligned\n", pidx+1); 679 return -EINVAL; 680 } 681 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 682 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 683 part_attrs |= EXT_CSD_ENH_GP(pidx); 684 tot_enh_size_mult += gp_size_mult[pidx]; 685 } 686 } 687 688 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 689 printf("Card does not support enhanced attribute\n"); 690 return -EMEDIUMTYPE; 691 } 692 693 err = mmc_send_ext_csd(mmc, ext_csd); 694 if (err) 695 return err; 696 697 max_enh_size_mult = 698 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 699 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 700 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 701 if (tot_enh_size_mult > max_enh_size_mult) { 702 printf("Total enhanced size exceeds maximum (%u > %u)\n", 703 tot_enh_size_mult, max_enh_size_mult); 704 return -EMEDIUMTYPE; 705 } 706 707 /* The default value of EXT_CSD_WR_REL_SET is device 708 * dependent, the values can only be changed if the 709 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 710 * changed only once and before partitioning is completed. */ 711 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 712 if (conf->user.wr_rel_change) { 713 if (conf->user.wr_rel_set) 714 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 715 else 716 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 717 } 718 for (pidx = 0; pidx < 4; pidx++) { 719 if (conf->gp_part[pidx].wr_rel_change) { 720 if (conf->gp_part[pidx].wr_rel_set) 721 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 722 else 723 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 724 } 725 } 726 727 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 728 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 729 puts("Card does not support host controlled partition write " 730 "reliability settings\n"); 731 return -EMEDIUMTYPE; 732 } 733 734 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 735 EXT_CSD_PARTITION_SETTING_COMPLETED) { 736 printf("Card already partitioned\n"); 737 return -EPERM; 738 } 739 740 if (mode == MMC_HWPART_CONF_CHECK) 741 return 0; 742 743 /* Partitioning requires high-capacity size definitions */ 744 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 745 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 746 EXT_CSD_ERASE_GROUP_DEF, 1); 747 748 if (err) 749 return err; 750 751 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 752 753 /* update erase group size to be high-capacity */ 754 mmc->erase_grp_size = 755 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 756 757 } 758 759 /* all OK, write the configuration */ 760 for (i = 0; i < 4; i++) { 761 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 762 EXT_CSD_ENH_START_ADDR+i, 763 (enh_start_addr >> (i*8)) & 0xFF); 764 if (err) 765 return err; 766 } 767 for (i = 0; i < 3; i++) { 768 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 769 EXT_CSD_ENH_SIZE_MULT+i, 770 (enh_size_mult >> (i*8)) & 0xFF); 771 if (err) 772 return err; 773 } 774 for (pidx = 0; pidx < 4; pidx++) { 775 for (i = 0; i < 3; i++) { 776 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 777 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 778 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 779 if (err) 780 return err; 781 } 782 } 783 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 784 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 785 if (err) 786 return err; 787 788 if (mode == MMC_HWPART_CONF_SET) 789 return 0; 790 791 /* The WR_REL_SET is a write-once register but shall be 792 * written before setting PART_SETTING_COMPLETED. As it is 793 * write-once we can only write it when completing the 794 * partitioning. */ 795 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 796 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 797 EXT_CSD_WR_REL_SET, wr_rel_set); 798 if (err) 799 return err; 800 } 801 802 /* Setting PART_SETTING_COMPLETED confirms the partition 803 * configuration but it only becomes effective after power 804 * cycle, so we do not adjust the partition related settings 805 * in the mmc struct. */ 806 807 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 808 EXT_CSD_PARTITION_SETTING, 809 EXT_CSD_PARTITION_SETTING_COMPLETED); 810 if (err) 811 return err; 812 813 return 0; 814 } 815 816 int mmc_getcd(struct mmc *mmc) 817 { 818 int cd; 819 820 cd = board_mmc_getcd(mmc); 821 822 if (cd < 0) { 823 if (mmc->cfg->ops->getcd) 824 cd = mmc->cfg->ops->getcd(mmc); 825 else 826 cd = 1; 827 } 828 829 return cd; 830 } 831 832 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 833 { 834 struct mmc_cmd cmd; 835 struct mmc_data data; 836 837 /* Switch the frequency */ 838 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 839 cmd.resp_type = MMC_RSP_R1; 840 cmd.cmdarg = (mode << 31) | 0xffffff; 841 cmd.cmdarg &= ~(0xf << (group * 4)); 842 cmd.cmdarg |= value << (group * 4); 843 844 data.dest = (char *)resp; 845 data.blocksize = 64; 846 data.blocks = 1; 847 data.flags = MMC_DATA_READ; 848 849 return mmc_send_cmd(mmc, &cmd, &data); 850 } 851 852 853 static int sd_change_freq(struct mmc *mmc) 854 { 855 int err; 856 struct mmc_cmd cmd; 857 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 858 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 859 struct mmc_data data; 860 int timeout; 861 862 mmc->card_caps = 0; 863 864 if (mmc_host_is_spi(mmc)) 865 return 0; 866 867 /* Read the SCR to find out if this card supports higher speeds */ 868 cmd.cmdidx = MMC_CMD_APP_CMD; 869 cmd.resp_type = MMC_RSP_R1; 870 cmd.cmdarg = mmc->rca << 16; 871 872 err = mmc_send_cmd(mmc, &cmd, NULL); 873 874 if (err) 875 return err; 876 877 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 878 cmd.resp_type = MMC_RSP_R1; 879 cmd.cmdarg = 0; 880 881 timeout = 3; 882 883 retry_scr: 884 data.dest = (char *)scr; 885 data.blocksize = 8; 886 data.blocks = 1; 887 data.flags = MMC_DATA_READ; 888 889 err = mmc_send_cmd(mmc, &cmd, &data); 890 891 if (err) { 892 if (timeout--) 893 goto retry_scr; 894 895 return err; 896 } 897 898 mmc->scr[0] = __be32_to_cpu(scr[0]); 899 mmc->scr[1] = __be32_to_cpu(scr[1]); 900 901 switch ((mmc->scr[0] >> 24) & 0xf) { 902 case 0: 903 mmc->version = SD_VERSION_1_0; 904 break; 905 case 1: 906 mmc->version = SD_VERSION_1_10; 907 break; 908 case 2: 909 mmc->version = SD_VERSION_2; 910 if ((mmc->scr[0] >> 15) & 0x1) 911 mmc->version = SD_VERSION_3; 912 break; 913 default: 914 mmc->version = SD_VERSION_1_0; 915 break; 916 } 917 918 if (mmc->scr[0] & SD_DATA_4BIT) 919 mmc->card_caps |= MMC_MODE_4BIT; 920 921 /* Version 1.0 doesn't support switching */ 922 if (mmc->version == SD_VERSION_1_0) 923 return 0; 924 925 timeout = 4; 926 while (timeout--) { 927 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 928 (u8 *)switch_status); 929 930 if (err) 931 return err; 932 933 /* The high-speed function is busy. Try again */ 934 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 935 break; 936 } 937 938 /* If high-speed isn't supported, we return */ 939 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 940 return 0; 941 942 /* 943 * If the host doesn't support SD_HIGHSPEED, do not switch card to 944 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 945 * This can avoid furthur problem when the card runs in different 946 * mode between the host. 947 */ 948 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 949 (mmc->cfg->host_caps & MMC_MODE_HS))) 950 return 0; 951 952 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 953 954 if (err) 955 return err; 956 957 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 958 mmc->card_caps |= MMC_MODE_HS; 959 960 return 0; 961 } 962 963 /* frequency bases */ 964 /* divided by 10 to be nice to platforms without floating point */ 965 static const int fbase[] = { 966 10000, 967 100000, 968 1000000, 969 10000000, 970 }; 971 972 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 973 * to platforms without floating point. 974 */ 975 static const int multipliers[] = { 976 0, /* reserved */ 977 10, 978 12, 979 13, 980 15, 981 20, 982 25, 983 30, 984 35, 985 40, 986 45, 987 50, 988 55, 989 60, 990 70, 991 80, 992 }; 993 994 static void mmc_set_ios(struct mmc *mmc) 995 { 996 if (mmc->cfg->ops->set_ios) 997 mmc->cfg->ops->set_ios(mmc); 998 } 999 1000 void mmc_set_clock(struct mmc *mmc, uint clock) 1001 { 1002 if (clock > mmc->cfg->f_max) 1003 clock = mmc->cfg->f_max; 1004 1005 if (clock < mmc->cfg->f_min) 1006 clock = mmc->cfg->f_min; 1007 1008 mmc->clock = clock; 1009 1010 mmc_set_ios(mmc); 1011 } 1012 1013 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1014 { 1015 mmc->bus_width = width; 1016 1017 mmc_set_ios(mmc); 1018 } 1019 1020 static int mmc_startup(struct mmc *mmc) 1021 { 1022 int err, i; 1023 uint mult, freq; 1024 u64 cmult, csize, capacity; 1025 struct mmc_cmd cmd; 1026 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1027 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1028 int timeout = 1000; 1029 bool has_parts = false; 1030 bool part_completed; 1031 1032 #ifdef CONFIG_MMC_SPI_CRC_ON 1033 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1034 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1035 cmd.resp_type = MMC_RSP_R1; 1036 cmd.cmdarg = 1; 1037 err = mmc_send_cmd(mmc, &cmd, NULL); 1038 1039 if (err) 1040 return err; 1041 } 1042 #endif 1043 1044 /* Put the Card in Identify Mode */ 1045 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1046 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1047 cmd.resp_type = MMC_RSP_R2; 1048 cmd.cmdarg = 0; 1049 1050 err = mmc_send_cmd(mmc, &cmd, NULL); 1051 1052 if (err) 1053 return err; 1054 1055 memcpy(mmc->cid, cmd.response, 16); 1056 1057 /* 1058 * For MMC cards, set the Relative Address. 1059 * For SD cards, get the Relatvie Address. 1060 * This also puts the cards into Standby State 1061 */ 1062 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1063 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1064 cmd.cmdarg = mmc->rca << 16; 1065 cmd.resp_type = MMC_RSP_R6; 1066 1067 err = mmc_send_cmd(mmc, &cmd, NULL); 1068 1069 if (err) 1070 return err; 1071 1072 if (IS_SD(mmc)) 1073 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1074 } 1075 1076 /* Get the Card-Specific Data */ 1077 cmd.cmdidx = MMC_CMD_SEND_CSD; 1078 cmd.resp_type = MMC_RSP_R2; 1079 cmd.cmdarg = mmc->rca << 16; 1080 1081 err = mmc_send_cmd(mmc, &cmd, NULL); 1082 1083 /* Waiting for the ready status */ 1084 mmc_send_status(mmc, timeout); 1085 1086 if (err) 1087 return err; 1088 1089 mmc->csd[0] = cmd.response[0]; 1090 mmc->csd[1] = cmd.response[1]; 1091 mmc->csd[2] = cmd.response[2]; 1092 mmc->csd[3] = cmd.response[3]; 1093 1094 if (mmc->version == MMC_VERSION_UNKNOWN) { 1095 int version = (cmd.response[0] >> 26) & 0xf; 1096 1097 switch (version) { 1098 case 0: 1099 mmc->version = MMC_VERSION_1_2; 1100 break; 1101 case 1: 1102 mmc->version = MMC_VERSION_1_4; 1103 break; 1104 case 2: 1105 mmc->version = MMC_VERSION_2_2; 1106 break; 1107 case 3: 1108 mmc->version = MMC_VERSION_3; 1109 break; 1110 case 4: 1111 mmc->version = MMC_VERSION_4; 1112 break; 1113 default: 1114 mmc->version = MMC_VERSION_1_2; 1115 break; 1116 } 1117 } 1118 1119 /* divide frequency by 10, since the mults are 10x bigger */ 1120 freq = fbase[(cmd.response[0] & 0x7)]; 1121 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1122 1123 mmc->tran_speed = freq * mult; 1124 1125 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1126 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1127 1128 if (IS_SD(mmc)) 1129 mmc->write_bl_len = mmc->read_bl_len; 1130 else 1131 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1132 1133 if (mmc->high_capacity) { 1134 csize = (mmc->csd[1] & 0x3f) << 16 1135 | (mmc->csd[2] & 0xffff0000) >> 16; 1136 cmult = 8; 1137 } else { 1138 csize = (mmc->csd[1] & 0x3ff) << 2 1139 | (mmc->csd[2] & 0xc0000000) >> 30; 1140 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1141 } 1142 1143 mmc->capacity_user = (csize + 1) << (cmult + 2); 1144 mmc->capacity_user *= mmc->read_bl_len; 1145 mmc->capacity_boot = 0; 1146 mmc->capacity_rpmb = 0; 1147 for (i = 0; i < 4; i++) 1148 mmc->capacity_gp[i] = 0; 1149 1150 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1151 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1152 1153 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1154 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1155 1156 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1157 cmd.cmdidx = MMC_CMD_SET_DSR; 1158 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1159 cmd.resp_type = MMC_RSP_NONE; 1160 if (mmc_send_cmd(mmc, &cmd, NULL)) 1161 printf("MMC: SET_DSR failed\n"); 1162 } 1163 1164 /* Select the card, and put it into Transfer Mode */ 1165 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1166 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1167 cmd.resp_type = MMC_RSP_R1; 1168 cmd.cmdarg = mmc->rca << 16; 1169 err = mmc_send_cmd(mmc, &cmd, NULL); 1170 1171 if (err) 1172 return err; 1173 } 1174 1175 /* 1176 * For SD, its erase group is always one sector 1177 */ 1178 mmc->erase_grp_size = 1; 1179 mmc->part_config = MMCPART_NOAVAILABLE; 1180 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1181 /* check ext_csd version and capacity */ 1182 err = mmc_send_ext_csd(mmc, ext_csd); 1183 if (err) 1184 return err; 1185 if (ext_csd[EXT_CSD_REV] >= 2) { 1186 /* 1187 * According to the JEDEC Standard, the value of 1188 * ext_csd's capacity is valid if the value is more 1189 * than 2GB 1190 */ 1191 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1192 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1193 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1194 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1195 capacity *= MMC_MAX_BLOCK_LEN; 1196 if ((capacity >> 20) > 2 * 1024) 1197 mmc->capacity_user = capacity; 1198 } 1199 1200 switch (ext_csd[EXT_CSD_REV]) { 1201 case 1: 1202 mmc->version = MMC_VERSION_4_1; 1203 break; 1204 case 2: 1205 mmc->version = MMC_VERSION_4_2; 1206 break; 1207 case 3: 1208 mmc->version = MMC_VERSION_4_3; 1209 break; 1210 case 5: 1211 mmc->version = MMC_VERSION_4_41; 1212 break; 1213 case 6: 1214 mmc->version = MMC_VERSION_4_5; 1215 break; 1216 case 7: 1217 mmc->version = MMC_VERSION_5_0; 1218 break; 1219 } 1220 1221 /* The partition data may be non-zero but it is only 1222 * effective if PARTITION_SETTING_COMPLETED is set in 1223 * EXT_CSD, so ignore any data if this bit is not set, 1224 * except for enabling the high-capacity group size 1225 * definition (see below). */ 1226 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1227 EXT_CSD_PARTITION_SETTING_COMPLETED); 1228 1229 /* store the partition info of emmc */ 1230 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1231 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1232 ext_csd[EXT_CSD_BOOT_MULT]) 1233 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1234 if (part_completed && 1235 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1236 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1237 1238 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1239 1240 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1241 1242 for (i = 0; i < 4; i++) { 1243 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1244 uint mult = (ext_csd[idx + 2] << 16) + 1245 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1246 if (mult) 1247 has_parts = true; 1248 if (!part_completed) 1249 continue; 1250 mmc->capacity_gp[i] = mult; 1251 mmc->capacity_gp[i] *= 1252 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1253 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1254 mmc->capacity_gp[i] <<= 19; 1255 } 1256 1257 if (part_completed) { 1258 mmc->enh_user_size = 1259 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1260 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1261 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1262 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1263 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1264 mmc->enh_user_size <<= 19; 1265 mmc->enh_user_start = 1266 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1267 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1268 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1269 ext_csd[EXT_CSD_ENH_START_ADDR]; 1270 if (mmc->high_capacity) 1271 mmc->enh_user_start <<= 9; 1272 } 1273 1274 /* 1275 * Host needs to enable ERASE_GRP_DEF bit if device is 1276 * partitioned. This bit will be lost every time after a reset 1277 * or power off. This will affect erase size. 1278 */ 1279 if (part_completed) 1280 has_parts = true; 1281 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1282 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1283 has_parts = true; 1284 if (has_parts) { 1285 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1286 EXT_CSD_ERASE_GROUP_DEF, 1); 1287 1288 if (err) 1289 return err; 1290 else 1291 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1292 } 1293 1294 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1295 /* Read out group size from ext_csd */ 1296 mmc->erase_grp_size = 1297 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1298 /* 1299 * if high capacity and partition setting completed 1300 * SEC_COUNT is valid even if it is smaller than 2 GiB 1301 * JEDEC Standard JESD84-B45, 6.2.4 1302 */ 1303 if (mmc->high_capacity && part_completed) { 1304 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1305 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1306 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1307 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1308 capacity *= MMC_MAX_BLOCK_LEN; 1309 mmc->capacity_user = capacity; 1310 } 1311 } else { 1312 /* Calculate the group size from the csd value. */ 1313 int erase_gsz, erase_gmul; 1314 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1315 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1316 mmc->erase_grp_size = (erase_gsz + 1) 1317 * (erase_gmul + 1); 1318 } 1319 1320 mmc->hc_wp_grp_size = 1024 1321 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1322 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1323 1324 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1325 } 1326 1327 err = mmc_set_capacity(mmc, mmc->part_num); 1328 if (err) 1329 return err; 1330 1331 if (IS_SD(mmc)) 1332 err = sd_change_freq(mmc); 1333 else 1334 err = mmc_change_freq(mmc); 1335 1336 if (err) 1337 return err; 1338 1339 /* Restrict card's capabilities by what the host can do */ 1340 mmc->card_caps &= mmc->cfg->host_caps; 1341 1342 if (IS_SD(mmc)) { 1343 if (mmc->card_caps & MMC_MODE_4BIT) { 1344 cmd.cmdidx = MMC_CMD_APP_CMD; 1345 cmd.resp_type = MMC_RSP_R1; 1346 cmd.cmdarg = mmc->rca << 16; 1347 1348 err = mmc_send_cmd(mmc, &cmd, NULL); 1349 if (err) 1350 return err; 1351 1352 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1353 cmd.resp_type = MMC_RSP_R1; 1354 cmd.cmdarg = 2; 1355 err = mmc_send_cmd(mmc, &cmd, NULL); 1356 if (err) 1357 return err; 1358 1359 mmc_set_bus_width(mmc, 4); 1360 } 1361 1362 if (mmc->card_caps & MMC_MODE_HS) 1363 mmc->tran_speed = 50000000; 1364 else 1365 mmc->tran_speed = 25000000; 1366 } else if (mmc->version >= MMC_VERSION_4) { 1367 /* Only version 4 of MMC supports wider bus widths */ 1368 int idx; 1369 1370 /* An array of possible bus widths in order of preference */ 1371 static unsigned ext_csd_bits[] = { 1372 EXT_CSD_DDR_BUS_WIDTH_8, 1373 EXT_CSD_DDR_BUS_WIDTH_4, 1374 EXT_CSD_BUS_WIDTH_8, 1375 EXT_CSD_BUS_WIDTH_4, 1376 EXT_CSD_BUS_WIDTH_1, 1377 }; 1378 1379 /* An array to map CSD bus widths to host cap bits */ 1380 static unsigned ext_to_hostcaps[] = { 1381 [EXT_CSD_DDR_BUS_WIDTH_4] = 1382 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1383 [EXT_CSD_DDR_BUS_WIDTH_8] = 1384 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1385 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1386 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1387 }; 1388 1389 /* An array to map chosen bus width to an integer */ 1390 static unsigned widths[] = { 1391 8, 4, 8, 4, 1, 1392 }; 1393 1394 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1395 unsigned int extw = ext_csd_bits[idx]; 1396 unsigned int caps = ext_to_hostcaps[extw]; 1397 1398 /* 1399 * If the bus width is still not changed, 1400 * don't try to set the default again. 1401 * Otherwise, recover from switch attempts 1402 * by switching to 1-bit bus width. 1403 */ 1404 if (extw == EXT_CSD_BUS_WIDTH_1 && 1405 mmc->bus_width == 1) { 1406 err = 0; 1407 break; 1408 } 1409 1410 /* 1411 * Check to make sure the card and controller support 1412 * these capabilities 1413 */ 1414 if ((mmc->card_caps & caps) != caps) 1415 continue; 1416 1417 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1418 EXT_CSD_BUS_WIDTH, extw); 1419 1420 if (err) 1421 continue; 1422 1423 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1424 mmc_set_bus_width(mmc, widths[idx]); 1425 1426 err = mmc_send_ext_csd(mmc, test_csd); 1427 1428 if (err) 1429 continue; 1430 1431 /* Only compare read only fields */ 1432 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1433 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1434 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1435 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1436 ext_csd[EXT_CSD_REV] 1437 == test_csd[EXT_CSD_REV] && 1438 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1439 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1440 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1441 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1442 break; 1443 else 1444 err = SWITCH_ERR; 1445 } 1446 1447 if (err) 1448 return err; 1449 1450 if (mmc->card_caps & MMC_MODE_HS) { 1451 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1452 mmc->tran_speed = 52000000; 1453 else 1454 mmc->tran_speed = 26000000; 1455 } 1456 } 1457 1458 mmc_set_clock(mmc, mmc->tran_speed); 1459 1460 /* Fix the block length for DDR mode */ 1461 if (mmc->ddr_mode) { 1462 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1463 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1464 } 1465 1466 /* fill in device description */ 1467 mmc->block_dev.lun = 0; 1468 mmc->block_dev.type = 0; 1469 mmc->block_dev.blksz = mmc->read_bl_len; 1470 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); 1471 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 1472 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1473 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", 1474 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1475 (mmc->cid[3] >> 16) & 0xffff); 1476 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1477 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1478 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1479 (mmc->cid[2] >> 24) & 0xff); 1480 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1481 (mmc->cid[2] >> 16) & 0xf); 1482 #else 1483 mmc->block_dev.vendor[0] = 0; 1484 mmc->block_dev.product[0] = 0; 1485 mmc->block_dev.revision[0] = 0; 1486 #endif 1487 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1488 init_part(&mmc->block_dev); 1489 #endif 1490 1491 return 0; 1492 } 1493 1494 static int mmc_send_if_cond(struct mmc *mmc) 1495 { 1496 struct mmc_cmd cmd; 1497 int err; 1498 1499 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1500 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1501 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1502 cmd.resp_type = MMC_RSP_R7; 1503 1504 err = mmc_send_cmd(mmc, &cmd, NULL); 1505 1506 if (err) 1507 return err; 1508 1509 if ((cmd.response[0] & 0xff) != 0xaa) 1510 return UNUSABLE_ERR; 1511 else 1512 mmc->version = SD_VERSION_2; 1513 1514 return 0; 1515 } 1516 1517 /* not used any more */ 1518 int __deprecated mmc_register(struct mmc *mmc) 1519 { 1520 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1521 printf("%s is deprecated! use mmc_create() instead.\n", __func__); 1522 #endif 1523 return -1; 1524 } 1525 1526 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) 1527 { 1528 struct mmc *mmc; 1529 1530 /* quick validation */ 1531 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || 1532 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) 1533 return NULL; 1534 1535 mmc = calloc(1, sizeof(*mmc)); 1536 if (mmc == NULL) 1537 return NULL; 1538 1539 mmc->cfg = cfg; 1540 mmc->priv = priv; 1541 1542 /* the following chunk was mmc_register() */ 1543 1544 /* Setup dsr related values */ 1545 mmc->dsr_imp = 0; 1546 mmc->dsr = 0xffffffff; 1547 /* Setup the universal parts of the block interface just once */ 1548 mmc->block_dev.if_type = IF_TYPE_MMC; 1549 mmc->block_dev.dev = cur_dev_num++; 1550 mmc->block_dev.removable = 1; 1551 mmc->block_dev.block_read = mmc_bread; 1552 mmc->block_dev.block_write = mmc_bwrite; 1553 mmc->block_dev.block_erase = mmc_berase; 1554 1555 /* setup initial part type */ 1556 mmc->block_dev.part_type = mmc->cfg->part_type; 1557 1558 INIT_LIST_HEAD(&mmc->link); 1559 1560 list_add_tail(&mmc->link, &mmc_devices); 1561 1562 return mmc; 1563 } 1564 1565 void mmc_destroy(struct mmc *mmc) 1566 { 1567 /* only freeing memory for now */ 1568 free(mmc); 1569 } 1570 1571 #ifdef CONFIG_PARTITIONS 1572 block_dev_desc_t *mmc_get_dev(int dev) 1573 { 1574 struct mmc *mmc = find_mmc_device(dev); 1575 if (!mmc || mmc_init(mmc)) 1576 return NULL; 1577 1578 return &mmc->block_dev; 1579 } 1580 #endif 1581 1582 /* board-specific MMC power initializations. */ 1583 __weak void board_mmc_power_init(void) 1584 { 1585 } 1586 1587 int mmc_start_init(struct mmc *mmc) 1588 { 1589 int err; 1590 1591 /* we pretend there's no card when init is NULL */ 1592 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1593 mmc->has_init = 0; 1594 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1595 printf("MMC: no card present\n"); 1596 #endif 1597 return NO_CARD_ERR; 1598 } 1599 1600 if (mmc->has_init) 1601 return 0; 1602 1603 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1604 mmc_adapter_card_type_ident(); 1605 #endif 1606 board_mmc_power_init(); 1607 1608 /* made sure it's not NULL earlier */ 1609 err = mmc->cfg->ops->init(mmc); 1610 1611 if (err) 1612 return err; 1613 1614 mmc->ddr_mode = 0; 1615 mmc_set_bus_width(mmc, 1); 1616 mmc_set_clock(mmc, 1); 1617 1618 /* Reset the Card */ 1619 err = mmc_go_idle(mmc); 1620 1621 if (err) 1622 return err; 1623 1624 /* The internal partition reset to user partition(0) at every CMD0*/ 1625 mmc->part_num = 0; 1626 1627 /* Test for SD version 2 */ 1628 err = mmc_send_if_cond(mmc); 1629 1630 /* Now try to get the SD card's operating condition */ 1631 err = sd_send_op_cond(mmc); 1632 1633 /* If the command timed out, we check for an MMC card */ 1634 if (err == TIMEOUT) { 1635 err = mmc_send_op_cond(mmc); 1636 1637 if (err) { 1638 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1639 printf("Card did not respond to voltage select!\n"); 1640 #endif 1641 return UNUSABLE_ERR; 1642 } 1643 } 1644 1645 if (!err) 1646 mmc->init_in_progress = 1; 1647 1648 return err; 1649 } 1650 1651 static int mmc_complete_init(struct mmc *mmc) 1652 { 1653 int err = 0; 1654 1655 mmc->init_in_progress = 0; 1656 if (mmc->op_cond_pending) 1657 err = mmc_complete_op_cond(mmc); 1658 1659 if (!err) 1660 err = mmc_startup(mmc); 1661 if (err) 1662 mmc->has_init = 0; 1663 else 1664 mmc->has_init = 1; 1665 return err; 1666 } 1667 1668 int mmc_init(struct mmc *mmc) 1669 { 1670 int err = 0; 1671 unsigned start; 1672 1673 if (mmc->has_init) 1674 return 0; 1675 1676 start = get_timer(0); 1677 1678 if (!mmc->init_in_progress) 1679 err = mmc_start_init(mmc); 1680 1681 if (!err) 1682 err = mmc_complete_init(mmc); 1683 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1684 return err; 1685 } 1686 1687 int mmc_set_dsr(struct mmc *mmc, u16 val) 1688 { 1689 mmc->dsr = val; 1690 return 0; 1691 } 1692 1693 /* CPU-specific MMC initializations */ 1694 __weak int cpu_mmc_init(bd_t *bis) 1695 { 1696 return -1; 1697 } 1698 1699 /* board-specific MMC initializations. */ 1700 __weak int board_mmc_init(bd_t *bis) 1701 { 1702 return -1; 1703 } 1704 1705 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1706 1707 void print_mmc_devices(char separator) 1708 { 1709 struct mmc *m; 1710 struct list_head *entry; 1711 char *mmc_type; 1712 1713 list_for_each(entry, &mmc_devices) { 1714 m = list_entry(entry, struct mmc, link); 1715 1716 if (m->has_init) 1717 mmc_type = IS_SD(m) ? "SD" : "eMMC"; 1718 else 1719 mmc_type = NULL; 1720 1721 printf("%s: %d", m->cfg->name, m->block_dev.dev); 1722 if (mmc_type) 1723 printf(" (%s)", mmc_type); 1724 1725 if (entry->next != &mmc_devices) { 1726 printf("%c", separator); 1727 if (separator != '\n') 1728 puts (" "); 1729 } 1730 } 1731 1732 printf("\n"); 1733 } 1734 1735 #else 1736 void print_mmc_devices(char separator) { } 1737 #endif 1738 1739 int get_mmc_num(void) 1740 { 1741 return cur_dev_num; 1742 } 1743 1744 void mmc_set_preinit(struct mmc *mmc, int preinit) 1745 { 1746 mmc->preinit = preinit; 1747 } 1748 1749 static void do_preinit(void) 1750 { 1751 struct mmc *m; 1752 struct list_head *entry; 1753 1754 list_for_each(entry, &mmc_devices) { 1755 m = list_entry(entry, struct mmc, link); 1756 1757 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1758 mmc_set_preinit(m, 1); 1759 #endif 1760 if (m->preinit) 1761 mmc_start_init(m); 1762 } 1763 } 1764 1765 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) 1766 static int mmc_probe(bd_t *bis) 1767 { 1768 return 0; 1769 } 1770 #elif defined(CONFIG_DM_MMC) 1771 static int mmc_probe(bd_t *bis) 1772 { 1773 int ret; 1774 struct uclass *uc; 1775 struct udevice *m; 1776 1777 ret = uclass_get(UCLASS_MMC, &uc); 1778 if (ret) 1779 return ret; 1780 1781 uclass_foreach_dev(m, uc) { 1782 ret = device_probe(m); 1783 if (ret) 1784 printf("%s - probe failed: %d\n", m->name, ret); 1785 } 1786 1787 return 0; 1788 } 1789 #else 1790 static int mmc_probe(bd_t *bis) 1791 { 1792 if (board_mmc_init(bis) < 0) 1793 cpu_mmc_init(bis); 1794 1795 return 0; 1796 } 1797 #endif 1798 1799 int mmc_initialize(bd_t *bis) 1800 { 1801 static int initialized = 0; 1802 int ret; 1803 if (initialized) /* Avoid initializing mmc multiple times */ 1804 return 0; 1805 initialized = 1; 1806 1807 INIT_LIST_HEAD (&mmc_devices); 1808 cur_dev_num = 0; 1809 1810 ret = mmc_probe(bis); 1811 if (ret) 1812 return ret; 1813 1814 #ifndef CONFIG_SPL_BUILD 1815 print_mmc_devices(','); 1816 #endif 1817 1818 do_preinit(); 1819 return 0; 1820 } 1821 1822 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1823 /* 1824 * This function changes the size of boot partition and the size of rpmb 1825 * partition present on EMMC devices. 1826 * 1827 * Input Parameters: 1828 * struct *mmc: pointer for the mmc device strcuture 1829 * bootsize: size of boot partition 1830 * rpmbsize: size of rpmb partition 1831 * 1832 * Returns 0 on success. 1833 */ 1834 1835 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1836 unsigned long rpmbsize) 1837 { 1838 int err; 1839 struct mmc_cmd cmd; 1840 1841 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1842 cmd.cmdidx = MMC_CMD_RES_MAN; 1843 cmd.resp_type = MMC_RSP_R1b; 1844 cmd.cmdarg = MMC_CMD62_ARG1; 1845 1846 err = mmc_send_cmd(mmc, &cmd, NULL); 1847 if (err) { 1848 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1849 return err; 1850 } 1851 1852 /* Boot partition changing mode */ 1853 cmd.cmdidx = MMC_CMD_RES_MAN; 1854 cmd.resp_type = MMC_RSP_R1b; 1855 cmd.cmdarg = MMC_CMD62_ARG2; 1856 1857 err = mmc_send_cmd(mmc, &cmd, NULL); 1858 if (err) { 1859 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1860 return err; 1861 } 1862 /* boot partition size is multiple of 128KB */ 1863 bootsize = (bootsize * 1024) / 128; 1864 1865 /* Arg: boot partition size */ 1866 cmd.cmdidx = MMC_CMD_RES_MAN; 1867 cmd.resp_type = MMC_RSP_R1b; 1868 cmd.cmdarg = bootsize; 1869 1870 err = mmc_send_cmd(mmc, &cmd, NULL); 1871 if (err) { 1872 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1873 return err; 1874 } 1875 /* RPMB partition size is multiple of 128KB */ 1876 rpmbsize = (rpmbsize * 1024) / 128; 1877 /* Arg: RPMB partition size */ 1878 cmd.cmdidx = MMC_CMD_RES_MAN; 1879 cmd.resp_type = MMC_RSP_R1b; 1880 cmd.cmdarg = rpmbsize; 1881 1882 err = mmc_send_cmd(mmc, &cmd, NULL); 1883 if (err) { 1884 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1885 return err; 1886 } 1887 return 0; 1888 } 1889 1890 /* 1891 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1892 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1893 * and BOOT_MODE. 1894 * 1895 * Returns 0 on success. 1896 */ 1897 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1898 { 1899 int err; 1900 1901 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1902 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1903 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1904 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1905 1906 if (err) 1907 return err; 1908 return 0; 1909 } 1910 1911 /* 1912 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1913 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1914 * PARTITION_ACCESS. 1915 * 1916 * Returns 0 on success. 1917 */ 1918 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1919 { 1920 int err; 1921 1922 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1923 EXT_CSD_BOOT_ACK(ack) | 1924 EXT_CSD_BOOT_PART_NUM(part_num) | 1925 EXT_CSD_PARTITION_ACCESS(access)); 1926 1927 if (err) 1928 return err; 1929 return 0; 1930 } 1931 1932 /* 1933 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1934 * for enable. Note that this is a write-once field for non-zero values. 1935 * 1936 * Returns 0 on success. 1937 */ 1938 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1939 { 1940 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1941 enable); 1942 } 1943 #endif 1944