1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include "mmc_private.h" 23 24 __weak int board_mmc_getwp(struct mmc *mmc) 25 { 26 return -1; 27 } 28 29 int mmc_getwp(struct mmc *mmc) 30 { 31 int wp; 32 33 wp = board_mmc_getwp(mmc); 34 35 if (wp < 0) { 36 if (mmc->cfg->ops->getwp) 37 wp = mmc->cfg->ops->getwp(mmc); 38 else 39 wp = 0; 40 } 41 42 return wp; 43 } 44 45 __weak int board_mmc_getcd(struct mmc *mmc) 46 { 47 return -1; 48 } 49 50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 51 { 52 int ret; 53 54 #ifdef CONFIG_MMC_TRACE 55 int i; 56 u8 *ptr; 57 58 printf("CMD_SEND:%d\n", cmd->cmdidx); 59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 61 if (ret) { 62 printf("\t\tRET\t\t\t %d\n", ret); 63 } else { 64 switch (cmd->resp_type) { 65 case MMC_RSP_NONE: 66 printf("\t\tMMC_RSP_NONE\n"); 67 break; 68 case MMC_RSP_R1: 69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 70 cmd->response[0]); 71 break; 72 case MMC_RSP_R1b: 73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 74 cmd->response[0]); 75 break; 76 case MMC_RSP_R2: 77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 78 cmd->response[0]); 79 printf("\t\t \t\t 0x%08X \n", 80 cmd->response[1]); 81 printf("\t\t \t\t 0x%08X \n", 82 cmd->response[2]); 83 printf("\t\t \t\t 0x%08X \n", 84 cmd->response[3]); 85 printf("\n"); 86 printf("\t\t\t\t\tDUMPING DATA\n"); 87 for (i = 0; i < 4; i++) { 88 int j; 89 printf("\t\t\t\t\t%03d - ", i*4); 90 ptr = (u8 *)&cmd->response[i]; 91 ptr += 3; 92 for (j = 0; j < 4; j++) 93 printf("%02X ", *ptr--); 94 printf("\n"); 95 } 96 break; 97 case MMC_RSP_R3: 98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 99 cmd->response[0]); 100 break; 101 default: 102 printf("\t\tERROR MMC rsp not supported\n"); 103 break; 104 } 105 } 106 #else 107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 108 #endif 109 return ret; 110 } 111 112 int mmc_send_status(struct mmc *mmc, int timeout) 113 { 114 struct mmc_cmd cmd; 115 int err, retries = 5; 116 #ifdef CONFIG_MMC_TRACE 117 int status; 118 #endif 119 120 cmd.cmdidx = MMC_CMD_SEND_STATUS; 121 cmd.resp_type = MMC_RSP_R1; 122 if (!mmc_host_is_spi(mmc)) 123 cmd.cmdarg = mmc->rca << 16; 124 125 while (1) { 126 err = mmc_send_cmd(mmc, &cmd, NULL); 127 if (!err) { 128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 129 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 130 MMC_STATE_PRG) 131 break; 132 else if (cmd.response[0] & MMC_STATUS_MASK) { 133 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 134 printf("Status Error: 0x%08X\n", 135 cmd.response[0]); 136 #endif 137 return COMM_ERR; 138 } 139 } else if (--retries < 0) 140 return err; 141 142 if (timeout-- <= 0) 143 break; 144 145 udelay(1000); 146 } 147 148 #ifdef CONFIG_MMC_TRACE 149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 150 printf("CURR STATE:%d\n", status); 151 #endif 152 if (timeout <= 0) { 153 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 154 printf("Timeout waiting card ready\n"); 155 #endif 156 return TIMEOUT; 157 } 158 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) 159 return SWITCH_ERR; 160 161 return 0; 162 } 163 164 int mmc_set_blocklen(struct mmc *mmc, int len) 165 { 166 struct mmc_cmd cmd; 167 168 if (mmc->ddr_mode) 169 return 0; 170 171 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 172 cmd.resp_type = MMC_RSP_R1; 173 cmd.cmdarg = len; 174 175 return mmc_send_cmd(mmc, &cmd, NULL); 176 } 177 178 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 179 lbaint_t blkcnt) 180 { 181 struct mmc_cmd cmd; 182 struct mmc_data data; 183 184 if (blkcnt > 1) 185 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 186 else 187 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 188 189 if (mmc->high_capacity) 190 cmd.cmdarg = start; 191 else 192 cmd.cmdarg = start * mmc->read_bl_len; 193 194 cmd.resp_type = MMC_RSP_R1; 195 196 data.dest = dst; 197 data.blocks = blkcnt; 198 data.blocksize = mmc->read_bl_len; 199 data.flags = MMC_DATA_READ; 200 201 if (mmc_send_cmd(mmc, &cmd, &data)) 202 return 0; 203 204 if (blkcnt > 1) { 205 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 206 cmd.cmdarg = 0; 207 cmd.resp_type = MMC_RSP_R1b; 208 if (mmc_send_cmd(mmc, &cmd, NULL)) { 209 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 210 printf("mmc fail to send stop cmd\n"); 211 #endif 212 return 0; 213 } 214 } 215 216 return blkcnt; 217 } 218 219 #ifdef CONFIG_BLK 220 static ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, 221 void *dst) 222 #else 223 static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, 224 lbaint_t blkcnt, void *dst) 225 #endif 226 { 227 #ifdef CONFIG_BLK 228 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 229 #endif 230 int dev_num = block_dev->devnum; 231 int err; 232 lbaint_t cur, blocks_todo = blkcnt; 233 234 if (blkcnt == 0) 235 return 0; 236 237 struct mmc *mmc = find_mmc_device(dev_num); 238 if (!mmc) 239 return 0; 240 241 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 242 if (err < 0) 243 return 0; 244 245 if ((start + blkcnt) > block_dev->lba) { 246 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 247 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 248 start + blkcnt, block_dev->lba); 249 #endif 250 return 0; 251 } 252 253 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 254 debug("%s: Failed to set blocklen\n", __func__); 255 return 0; 256 } 257 258 do { 259 cur = (blocks_todo > mmc->cfg->b_max) ? 260 mmc->cfg->b_max : blocks_todo; 261 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 262 debug("%s: Failed to read blocks\n", __func__); 263 return 0; 264 } 265 blocks_todo -= cur; 266 start += cur; 267 dst += cur * mmc->read_bl_len; 268 } while (blocks_todo > 0); 269 270 return blkcnt; 271 } 272 273 static int mmc_go_idle(struct mmc *mmc) 274 { 275 struct mmc_cmd cmd; 276 int err; 277 278 udelay(1000); 279 280 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 281 cmd.cmdarg = 0; 282 cmd.resp_type = MMC_RSP_NONE; 283 284 err = mmc_send_cmd(mmc, &cmd, NULL); 285 286 if (err) 287 return err; 288 289 udelay(2000); 290 291 return 0; 292 } 293 294 static int sd_send_op_cond(struct mmc *mmc) 295 { 296 int timeout = 1000; 297 int err; 298 struct mmc_cmd cmd; 299 300 while (1) { 301 cmd.cmdidx = MMC_CMD_APP_CMD; 302 cmd.resp_type = MMC_RSP_R1; 303 cmd.cmdarg = 0; 304 305 err = mmc_send_cmd(mmc, &cmd, NULL); 306 307 if (err) 308 return err; 309 310 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 311 cmd.resp_type = MMC_RSP_R3; 312 313 /* 314 * Most cards do not answer if some reserved bits 315 * in the ocr are set. However, Some controller 316 * can set bit 7 (reserved for low voltages), but 317 * how to manage low voltages SD card is not yet 318 * specified. 319 */ 320 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 321 (mmc->cfg->voltages & 0xff8000); 322 323 if (mmc->version == SD_VERSION_2) 324 cmd.cmdarg |= OCR_HCS; 325 326 err = mmc_send_cmd(mmc, &cmd, NULL); 327 328 if (err) 329 return err; 330 331 if (cmd.response[0] & OCR_BUSY) 332 break; 333 334 if (timeout-- <= 0) 335 return UNUSABLE_ERR; 336 337 udelay(1000); 338 } 339 340 if (mmc->version != SD_VERSION_2) 341 mmc->version = SD_VERSION_1_0; 342 343 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 344 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 345 cmd.resp_type = MMC_RSP_R3; 346 cmd.cmdarg = 0; 347 348 err = mmc_send_cmd(mmc, &cmd, NULL); 349 350 if (err) 351 return err; 352 } 353 354 mmc->ocr = cmd.response[0]; 355 356 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 357 mmc->rca = 0; 358 359 return 0; 360 } 361 362 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 363 { 364 struct mmc_cmd cmd; 365 int err; 366 367 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 368 cmd.resp_type = MMC_RSP_R3; 369 cmd.cmdarg = 0; 370 if (use_arg && !mmc_host_is_spi(mmc)) 371 cmd.cmdarg = OCR_HCS | 372 (mmc->cfg->voltages & 373 (mmc->ocr & OCR_VOLTAGE_MASK)) | 374 (mmc->ocr & OCR_ACCESS_MODE); 375 376 err = mmc_send_cmd(mmc, &cmd, NULL); 377 if (err) 378 return err; 379 mmc->ocr = cmd.response[0]; 380 return 0; 381 } 382 383 static int mmc_send_op_cond(struct mmc *mmc) 384 { 385 int err, i; 386 387 /* Some cards seem to need this */ 388 mmc_go_idle(mmc); 389 390 /* Asking to the card its capabilities */ 391 for (i = 0; i < 2; i++) { 392 err = mmc_send_op_cond_iter(mmc, i != 0); 393 if (err) 394 return err; 395 396 /* exit if not busy (flag seems to be inverted) */ 397 if (mmc->ocr & OCR_BUSY) 398 break; 399 } 400 mmc->op_cond_pending = 1; 401 return 0; 402 } 403 404 static int mmc_complete_op_cond(struct mmc *mmc) 405 { 406 struct mmc_cmd cmd; 407 int timeout = 1000; 408 uint start; 409 int err; 410 411 mmc->op_cond_pending = 0; 412 if (!(mmc->ocr & OCR_BUSY)) { 413 start = get_timer(0); 414 while (1) { 415 err = mmc_send_op_cond_iter(mmc, 1); 416 if (err) 417 return err; 418 if (mmc->ocr & OCR_BUSY) 419 break; 420 if (get_timer(start) > timeout) 421 return UNUSABLE_ERR; 422 udelay(100); 423 } 424 } 425 426 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 427 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 428 cmd.resp_type = MMC_RSP_R3; 429 cmd.cmdarg = 0; 430 431 err = mmc_send_cmd(mmc, &cmd, NULL); 432 433 if (err) 434 return err; 435 436 mmc->ocr = cmd.response[0]; 437 } 438 439 mmc->version = MMC_VERSION_UNKNOWN; 440 441 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 442 mmc->rca = 1; 443 444 return 0; 445 } 446 447 448 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 449 { 450 struct mmc_cmd cmd; 451 struct mmc_data data; 452 int err; 453 454 /* Get the Card Status Register */ 455 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 456 cmd.resp_type = MMC_RSP_R1; 457 cmd.cmdarg = 0; 458 459 data.dest = (char *)ext_csd; 460 data.blocks = 1; 461 data.blocksize = MMC_MAX_BLOCK_LEN; 462 data.flags = MMC_DATA_READ; 463 464 err = mmc_send_cmd(mmc, &cmd, &data); 465 466 return err; 467 } 468 469 470 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 471 { 472 struct mmc_cmd cmd; 473 int timeout = 1000; 474 int ret; 475 476 cmd.cmdidx = MMC_CMD_SWITCH; 477 cmd.resp_type = MMC_RSP_R1b; 478 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 479 (index << 16) | 480 (value << 8); 481 482 ret = mmc_send_cmd(mmc, &cmd, NULL); 483 484 /* Waiting for the ready status */ 485 if (!ret) 486 ret = mmc_send_status(mmc, timeout); 487 488 return ret; 489 490 } 491 492 static int mmc_change_freq(struct mmc *mmc) 493 { 494 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 495 char cardtype; 496 int err; 497 498 mmc->card_caps = 0; 499 500 if (mmc_host_is_spi(mmc)) 501 return 0; 502 503 /* Only version 4 supports high-speed */ 504 if (mmc->version < MMC_VERSION_4) 505 return 0; 506 507 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 508 509 err = mmc_send_ext_csd(mmc, ext_csd); 510 511 if (err) 512 return err; 513 514 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 515 516 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 517 518 if (err) 519 return err == SWITCH_ERR ? 0 : err; 520 521 /* Now check to see that it worked */ 522 err = mmc_send_ext_csd(mmc, ext_csd); 523 524 if (err) 525 return err; 526 527 /* No high-speed support */ 528 if (!ext_csd[EXT_CSD_HS_TIMING]) 529 return 0; 530 531 /* High Speed is set, there are two types: 52MHz and 26MHz */ 532 if (cardtype & EXT_CSD_CARD_TYPE_52) { 533 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 534 mmc->card_caps |= MMC_MODE_DDR_52MHz; 535 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 536 } else { 537 mmc->card_caps |= MMC_MODE_HS; 538 } 539 540 return 0; 541 } 542 543 static int mmc_set_capacity(struct mmc *mmc, int part_num) 544 { 545 switch (part_num) { 546 case 0: 547 mmc->capacity = mmc->capacity_user; 548 break; 549 case 1: 550 case 2: 551 mmc->capacity = mmc->capacity_boot; 552 break; 553 case 3: 554 mmc->capacity = mmc->capacity_rpmb; 555 break; 556 case 4: 557 case 5: 558 case 6: 559 case 7: 560 mmc->capacity = mmc->capacity_gp[part_num - 4]; 561 break; 562 default: 563 return -1; 564 } 565 566 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 567 568 return 0; 569 } 570 571 static int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 572 { 573 int ret; 574 575 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 576 (mmc->part_config & ~PART_ACCESS_MASK) 577 | (part_num & PART_ACCESS_MASK)); 578 579 /* 580 * Set the capacity if the switch succeeded or was intended 581 * to return to representing the raw device. 582 */ 583 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 584 ret = mmc_set_capacity(mmc, part_num); 585 mmc_get_blk_desc(mmc)->hwpart = part_num; 586 } 587 588 return ret; 589 } 590 591 #ifdef CONFIG_BLK 592 static int mmc_select_hwpart(struct udevice *bdev, int hwpart) 593 { 594 struct udevice *mmc_dev = dev_get_parent(bdev); 595 struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); 596 struct blk_desc *desc = dev_get_uclass_platdata(bdev); 597 int ret; 598 599 if (desc->hwpart == hwpart) 600 return 0; 601 602 if (mmc->part_config == MMCPART_NOAVAILABLE) 603 return -EMEDIUMTYPE; 604 605 ret = mmc_switch_part(mmc, hwpart); 606 if (ret) 607 return ret; 608 609 return 0; 610 } 611 #else 612 static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart) 613 { 614 struct mmc *mmc = find_mmc_device(desc->devnum); 615 int ret; 616 617 if (!mmc) 618 return -ENODEV; 619 620 if (mmc->block_dev.hwpart == hwpart) 621 return 0; 622 623 if (mmc->part_config == MMCPART_NOAVAILABLE) 624 return -EMEDIUMTYPE; 625 626 ret = mmc_switch_part(mmc, hwpart); 627 if (ret) 628 return ret; 629 630 return 0; 631 } 632 #endif 633 634 int mmc_hwpart_config(struct mmc *mmc, 635 const struct mmc_hwpart_conf *conf, 636 enum mmc_hwpart_conf_mode mode) 637 { 638 u8 part_attrs = 0; 639 u32 enh_size_mult; 640 u32 enh_start_addr; 641 u32 gp_size_mult[4]; 642 u32 max_enh_size_mult; 643 u32 tot_enh_size_mult = 0; 644 u8 wr_rel_set; 645 int i, pidx, err; 646 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 647 648 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 649 return -EINVAL; 650 651 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 652 printf("eMMC >= 4.4 required for enhanced user data area\n"); 653 return -EMEDIUMTYPE; 654 } 655 656 if (!(mmc->part_support & PART_SUPPORT)) { 657 printf("Card does not support partitioning\n"); 658 return -EMEDIUMTYPE; 659 } 660 661 if (!mmc->hc_wp_grp_size) { 662 printf("Card does not define HC WP group size\n"); 663 return -EMEDIUMTYPE; 664 } 665 666 /* check partition alignment and total enhanced size */ 667 if (conf->user.enh_size) { 668 if (conf->user.enh_size % mmc->hc_wp_grp_size || 669 conf->user.enh_start % mmc->hc_wp_grp_size) { 670 printf("User data enhanced area not HC WP group " 671 "size aligned\n"); 672 return -EINVAL; 673 } 674 part_attrs |= EXT_CSD_ENH_USR; 675 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 676 if (mmc->high_capacity) { 677 enh_start_addr = conf->user.enh_start; 678 } else { 679 enh_start_addr = (conf->user.enh_start << 9); 680 } 681 } else { 682 enh_size_mult = 0; 683 enh_start_addr = 0; 684 } 685 tot_enh_size_mult += enh_size_mult; 686 687 for (pidx = 0; pidx < 4; pidx++) { 688 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 689 printf("GP%i partition not HC WP group size " 690 "aligned\n", pidx+1); 691 return -EINVAL; 692 } 693 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 694 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 695 part_attrs |= EXT_CSD_ENH_GP(pidx); 696 tot_enh_size_mult += gp_size_mult[pidx]; 697 } 698 } 699 700 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 701 printf("Card does not support enhanced attribute\n"); 702 return -EMEDIUMTYPE; 703 } 704 705 err = mmc_send_ext_csd(mmc, ext_csd); 706 if (err) 707 return err; 708 709 max_enh_size_mult = 710 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 711 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 712 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 713 if (tot_enh_size_mult > max_enh_size_mult) { 714 printf("Total enhanced size exceeds maximum (%u > %u)\n", 715 tot_enh_size_mult, max_enh_size_mult); 716 return -EMEDIUMTYPE; 717 } 718 719 /* The default value of EXT_CSD_WR_REL_SET is device 720 * dependent, the values can only be changed if the 721 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 722 * changed only once and before partitioning is completed. */ 723 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 724 if (conf->user.wr_rel_change) { 725 if (conf->user.wr_rel_set) 726 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 727 else 728 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 729 } 730 for (pidx = 0; pidx < 4; pidx++) { 731 if (conf->gp_part[pidx].wr_rel_change) { 732 if (conf->gp_part[pidx].wr_rel_set) 733 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 734 else 735 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 736 } 737 } 738 739 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 740 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 741 puts("Card does not support host controlled partition write " 742 "reliability settings\n"); 743 return -EMEDIUMTYPE; 744 } 745 746 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 747 EXT_CSD_PARTITION_SETTING_COMPLETED) { 748 printf("Card already partitioned\n"); 749 return -EPERM; 750 } 751 752 if (mode == MMC_HWPART_CONF_CHECK) 753 return 0; 754 755 /* Partitioning requires high-capacity size definitions */ 756 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 757 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 758 EXT_CSD_ERASE_GROUP_DEF, 1); 759 760 if (err) 761 return err; 762 763 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 764 765 /* update erase group size to be high-capacity */ 766 mmc->erase_grp_size = 767 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 768 769 } 770 771 /* all OK, write the configuration */ 772 for (i = 0; i < 4; i++) { 773 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 774 EXT_CSD_ENH_START_ADDR+i, 775 (enh_start_addr >> (i*8)) & 0xFF); 776 if (err) 777 return err; 778 } 779 for (i = 0; i < 3; i++) { 780 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 781 EXT_CSD_ENH_SIZE_MULT+i, 782 (enh_size_mult >> (i*8)) & 0xFF); 783 if (err) 784 return err; 785 } 786 for (pidx = 0; pidx < 4; pidx++) { 787 for (i = 0; i < 3; i++) { 788 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 789 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 790 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 791 if (err) 792 return err; 793 } 794 } 795 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 796 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 797 if (err) 798 return err; 799 800 if (mode == MMC_HWPART_CONF_SET) 801 return 0; 802 803 /* The WR_REL_SET is a write-once register but shall be 804 * written before setting PART_SETTING_COMPLETED. As it is 805 * write-once we can only write it when completing the 806 * partitioning. */ 807 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 808 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 809 EXT_CSD_WR_REL_SET, wr_rel_set); 810 if (err) 811 return err; 812 } 813 814 /* Setting PART_SETTING_COMPLETED confirms the partition 815 * configuration but it only becomes effective after power 816 * cycle, so we do not adjust the partition related settings 817 * in the mmc struct. */ 818 819 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 820 EXT_CSD_PARTITION_SETTING, 821 EXT_CSD_PARTITION_SETTING_COMPLETED); 822 if (err) 823 return err; 824 825 return 0; 826 } 827 828 int mmc_getcd(struct mmc *mmc) 829 { 830 int cd; 831 832 cd = board_mmc_getcd(mmc); 833 834 if (cd < 0) { 835 if (mmc->cfg->ops->getcd) 836 cd = mmc->cfg->ops->getcd(mmc); 837 else 838 cd = 1; 839 } 840 841 return cd; 842 } 843 844 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 845 { 846 struct mmc_cmd cmd; 847 struct mmc_data data; 848 849 /* Switch the frequency */ 850 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 851 cmd.resp_type = MMC_RSP_R1; 852 cmd.cmdarg = (mode << 31) | 0xffffff; 853 cmd.cmdarg &= ~(0xf << (group * 4)); 854 cmd.cmdarg |= value << (group * 4); 855 856 data.dest = (char *)resp; 857 data.blocksize = 64; 858 data.blocks = 1; 859 data.flags = MMC_DATA_READ; 860 861 return mmc_send_cmd(mmc, &cmd, &data); 862 } 863 864 865 static int sd_change_freq(struct mmc *mmc) 866 { 867 int err; 868 struct mmc_cmd cmd; 869 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 870 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 871 struct mmc_data data; 872 int timeout; 873 874 mmc->card_caps = 0; 875 876 if (mmc_host_is_spi(mmc)) 877 return 0; 878 879 /* Read the SCR to find out if this card supports higher speeds */ 880 cmd.cmdidx = MMC_CMD_APP_CMD; 881 cmd.resp_type = MMC_RSP_R1; 882 cmd.cmdarg = mmc->rca << 16; 883 884 err = mmc_send_cmd(mmc, &cmd, NULL); 885 886 if (err) 887 return err; 888 889 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 890 cmd.resp_type = MMC_RSP_R1; 891 cmd.cmdarg = 0; 892 893 timeout = 3; 894 895 retry_scr: 896 data.dest = (char *)scr; 897 data.blocksize = 8; 898 data.blocks = 1; 899 data.flags = MMC_DATA_READ; 900 901 err = mmc_send_cmd(mmc, &cmd, &data); 902 903 if (err) { 904 if (timeout--) 905 goto retry_scr; 906 907 return err; 908 } 909 910 mmc->scr[0] = __be32_to_cpu(scr[0]); 911 mmc->scr[1] = __be32_to_cpu(scr[1]); 912 913 switch ((mmc->scr[0] >> 24) & 0xf) { 914 case 0: 915 mmc->version = SD_VERSION_1_0; 916 break; 917 case 1: 918 mmc->version = SD_VERSION_1_10; 919 break; 920 case 2: 921 mmc->version = SD_VERSION_2; 922 if ((mmc->scr[0] >> 15) & 0x1) 923 mmc->version = SD_VERSION_3; 924 break; 925 default: 926 mmc->version = SD_VERSION_1_0; 927 break; 928 } 929 930 if (mmc->scr[0] & SD_DATA_4BIT) 931 mmc->card_caps |= MMC_MODE_4BIT; 932 933 /* Version 1.0 doesn't support switching */ 934 if (mmc->version == SD_VERSION_1_0) 935 return 0; 936 937 timeout = 4; 938 while (timeout--) { 939 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 940 (u8 *)switch_status); 941 942 if (err) 943 return err; 944 945 /* The high-speed function is busy. Try again */ 946 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 947 break; 948 } 949 950 /* If high-speed isn't supported, we return */ 951 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 952 return 0; 953 954 /* 955 * If the host doesn't support SD_HIGHSPEED, do not switch card to 956 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 957 * This can avoid furthur problem when the card runs in different 958 * mode between the host. 959 */ 960 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 961 (mmc->cfg->host_caps & MMC_MODE_HS))) 962 return 0; 963 964 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 965 966 if (err) 967 return err; 968 969 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 970 mmc->card_caps |= MMC_MODE_HS; 971 972 return 0; 973 } 974 975 /* frequency bases */ 976 /* divided by 10 to be nice to platforms without floating point */ 977 static const int fbase[] = { 978 10000, 979 100000, 980 1000000, 981 10000000, 982 }; 983 984 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 985 * to platforms without floating point. 986 */ 987 static const int multipliers[] = { 988 0, /* reserved */ 989 10, 990 12, 991 13, 992 15, 993 20, 994 25, 995 30, 996 35, 997 40, 998 45, 999 50, 1000 55, 1001 60, 1002 70, 1003 80, 1004 }; 1005 1006 static void mmc_set_ios(struct mmc *mmc) 1007 { 1008 if (mmc->cfg->ops->set_ios) 1009 mmc->cfg->ops->set_ios(mmc); 1010 } 1011 1012 void mmc_set_clock(struct mmc *mmc, uint clock) 1013 { 1014 if (clock > mmc->cfg->f_max) 1015 clock = mmc->cfg->f_max; 1016 1017 if (clock < mmc->cfg->f_min) 1018 clock = mmc->cfg->f_min; 1019 1020 mmc->clock = clock; 1021 1022 mmc_set_ios(mmc); 1023 } 1024 1025 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1026 { 1027 mmc->bus_width = width; 1028 1029 mmc_set_ios(mmc); 1030 } 1031 1032 static int mmc_startup(struct mmc *mmc) 1033 { 1034 int err, i; 1035 uint mult, freq; 1036 u64 cmult, csize, capacity; 1037 struct mmc_cmd cmd; 1038 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1039 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1040 int timeout = 1000; 1041 bool has_parts = false; 1042 bool part_completed; 1043 struct blk_desc *bdesc; 1044 1045 #ifdef CONFIG_MMC_SPI_CRC_ON 1046 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1047 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1048 cmd.resp_type = MMC_RSP_R1; 1049 cmd.cmdarg = 1; 1050 err = mmc_send_cmd(mmc, &cmd, NULL); 1051 1052 if (err) 1053 return err; 1054 } 1055 #endif 1056 1057 /* Put the Card in Identify Mode */ 1058 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1059 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1060 cmd.resp_type = MMC_RSP_R2; 1061 cmd.cmdarg = 0; 1062 1063 err = mmc_send_cmd(mmc, &cmd, NULL); 1064 1065 if (err) 1066 return err; 1067 1068 memcpy(mmc->cid, cmd.response, 16); 1069 1070 /* 1071 * For MMC cards, set the Relative Address. 1072 * For SD cards, get the Relatvie Address. 1073 * This also puts the cards into Standby State 1074 */ 1075 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1076 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1077 cmd.cmdarg = mmc->rca << 16; 1078 cmd.resp_type = MMC_RSP_R6; 1079 1080 err = mmc_send_cmd(mmc, &cmd, NULL); 1081 1082 if (err) 1083 return err; 1084 1085 if (IS_SD(mmc)) 1086 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1087 } 1088 1089 /* Get the Card-Specific Data */ 1090 cmd.cmdidx = MMC_CMD_SEND_CSD; 1091 cmd.resp_type = MMC_RSP_R2; 1092 cmd.cmdarg = mmc->rca << 16; 1093 1094 err = mmc_send_cmd(mmc, &cmd, NULL); 1095 1096 /* Waiting for the ready status */ 1097 mmc_send_status(mmc, timeout); 1098 1099 if (err) 1100 return err; 1101 1102 mmc->csd[0] = cmd.response[0]; 1103 mmc->csd[1] = cmd.response[1]; 1104 mmc->csd[2] = cmd.response[2]; 1105 mmc->csd[3] = cmd.response[3]; 1106 1107 if (mmc->version == MMC_VERSION_UNKNOWN) { 1108 int version = (cmd.response[0] >> 26) & 0xf; 1109 1110 switch (version) { 1111 case 0: 1112 mmc->version = MMC_VERSION_1_2; 1113 break; 1114 case 1: 1115 mmc->version = MMC_VERSION_1_4; 1116 break; 1117 case 2: 1118 mmc->version = MMC_VERSION_2_2; 1119 break; 1120 case 3: 1121 mmc->version = MMC_VERSION_3; 1122 break; 1123 case 4: 1124 mmc->version = MMC_VERSION_4; 1125 break; 1126 default: 1127 mmc->version = MMC_VERSION_1_2; 1128 break; 1129 } 1130 } 1131 1132 /* divide frequency by 10, since the mults are 10x bigger */ 1133 freq = fbase[(cmd.response[0] & 0x7)]; 1134 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1135 1136 mmc->tran_speed = freq * mult; 1137 1138 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1139 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1140 1141 if (IS_SD(mmc)) 1142 mmc->write_bl_len = mmc->read_bl_len; 1143 else 1144 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1145 1146 if (mmc->high_capacity) { 1147 csize = (mmc->csd[1] & 0x3f) << 16 1148 | (mmc->csd[2] & 0xffff0000) >> 16; 1149 cmult = 8; 1150 } else { 1151 csize = (mmc->csd[1] & 0x3ff) << 2 1152 | (mmc->csd[2] & 0xc0000000) >> 30; 1153 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1154 } 1155 1156 mmc->capacity_user = (csize + 1) << (cmult + 2); 1157 mmc->capacity_user *= mmc->read_bl_len; 1158 mmc->capacity_boot = 0; 1159 mmc->capacity_rpmb = 0; 1160 for (i = 0; i < 4; i++) 1161 mmc->capacity_gp[i] = 0; 1162 1163 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1164 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1165 1166 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1167 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1168 1169 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1170 cmd.cmdidx = MMC_CMD_SET_DSR; 1171 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1172 cmd.resp_type = MMC_RSP_NONE; 1173 if (mmc_send_cmd(mmc, &cmd, NULL)) 1174 printf("MMC: SET_DSR failed\n"); 1175 } 1176 1177 /* Select the card, and put it into Transfer Mode */ 1178 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1179 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1180 cmd.resp_type = MMC_RSP_R1; 1181 cmd.cmdarg = mmc->rca << 16; 1182 err = mmc_send_cmd(mmc, &cmd, NULL); 1183 1184 if (err) 1185 return err; 1186 } 1187 1188 /* 1189 * For SD, its erase group is always one sector 1190 */ 1191 mmc->erase_grp_size = 1; 1192 mmc->part_config = MMCPART_NOAVAILABLE; 1193 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1194 /* check ext_csd version and capacity */ 1195 err = mmc_send_ext_csd(mmc, ext_csd); 1196 if (err) 1197 return err; 1198 if (ext_csd[EXT_CSD_REV] >= 2) { 1199 /* 1200 * According to the JEDEC Standard, the value of 1201 * ext_csd's capacity is valid if the value is more 1202 * than 2GB 1203 */ 1204 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1205 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1206 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1207 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1208 capacity *= MMC_MAX_BLOCK_LEN; 1209 if ((capacity >> 20) > 2 * 1024) 1210 mmc->capacity_user = capacity; 1211 } 1212 1213 switch (ext_csd[EXT_CSD_REV]) { 1214 case 1: 1215 mmc->version = MMC_VERSION_4_1; 1216 break; 1217 case 2: 1218 mmc->version = MMC_VERSION_4_2; 1219 break; 1220 case 3: 1221 mmc->version = MMC_VERSION_4_3; 1222 break; 1223 case 5: 1224 mmc->version = MMC_VERSION_4_41; 1225 break; 1226 case 6: 1227 mmc->version = MMC_VERSION_4_5; 1228 break; 1229 case 7: 1230 mmc->version = MMC_VERSION_5_0; 1231 break; 1232 } 1233 1234 /* The partition data may be non-zero but it is only 1235 * effective if PARTITION_SETTING_COMPLETED is set in 1236 * EXT_CSD, so ignore any data if this bit is not set, 1237 * except for enabling the high-capacity group size 1238 * definition (see below). */ 1239 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1240 EXT_CSD_PARTITION_SETTING_COMPLETED); 1241 1242 /* store the partition info of emmc */ 1243 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1244 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1245 ext_csd[EXT_CSD_BOOT_MULT]) 1246 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1247 if (part_completed && 1248 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1249 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1250 1251 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1252 1253 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1254 1255 for (i = 0; i < 4; i++) { 1256 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1257 uint mult = (ext_csd[idx + 2] << 16) + 1258 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1259 if (mult) 1260 has_parts = true; 1261 if (!part_completed) 1262 continue; 1263 mmc->capacity_gp[i] = mult; 1264 mmc->capacity_gp[i] *= 1265 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1266 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1267 mmc->capacity_gp[i] <<= 19; 1268 } 1269 1270 if (part_completed) { 1271 mmc->enh_user_size = 1272 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1273 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1274 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1275 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1276 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1277 mmc->enh_user_size <<= 19; 1278 mmc->enh_user_start = 1279 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1280 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1281 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1282 ext_csd[EXT_CSD_ENH_START_ADDR]; 1283 if (mmc->high_capacity) 1284 mmc->enh_user_start <<= 9; 1285 } 1286 1287 /* 1288 * Host needs to enable ERASE_GRP_DEF bit if device is 1289 * partitioned. This bit will be lost every time after a reset 1290 * or power off. This will affect erase size. 1291 */ 1292 if (part_completed) 1293 has_parts = true; 1294 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1295 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1296 has_parts = true; 1297 if (has_parts) { 1298 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1299 EXT_CSD_ERASE_GROUP_DEF, 1); 1300 1301 if (err) 1302 return err; 1303 else 1304 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1305 } 1306 1307 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1308 /* Read out group size from ext_csd */ 1309 mmc->erase_grp_size = 1310 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1311 /* 1312 * if high capacity and partition setting completed 1313 * SEC_COUNT is valid even if it is smaller than 2 GiB 1314 * JEDEC Standard JESD84-B45, 6.2.4 1315 */ 1316 if (mmc->high_capacity && part_completed) { 1317 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1318 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1319 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1320 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1321 capacity *= MMC_MAX_BLOCK_LEN; 1322 mmc->capacity_user = capacity; 1323 } 1324 } else { 1325 /* Calculate the group size from the csd value. */ 1326 int erase_gsz, erase_gmul; 1327 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1328 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1329 mmc->erase_grp_size = (erase_gsz + 1) 1330 * (erase_gmul + 1); 1331 } 1332 1333 mmc->hc_wp_grp_size = 1024 1334 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1335 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1336 1337 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1338 } 1339 1340 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 1341 if (err) 1342 return err; 1343 1344 if (IS_SD(mmc)) 1345 err = sd_change_freq(mmc); 1346 else 1347 err = mmc_change_freq(mmc); 1348 1349 if (err) 1350 return err; 1351 1352 /* Restrict card's capabilities by what the host can do */ 1353 mmc->card_caps &= mmc->cfg->host_caps; 1354 1355 if (IS_SD(mmc)) { 1356 if (mmc->card_caps & MMC_MODE_4BIT) { 1357 cmd.cmdidx = MMC_CMD_APP_CMD; 1358 cmd.resp_type = MMC_RSP_R1; 1359 cmd.cmdarg = mmc->rca << 16; 1360 1361 err = mmc_send_cmd(mmc, &cmd, NULL); 1362 if (err) 1363 return err; 1364 1365 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1366 cmd.resp_type = MMC_RSP_R1; 1367 cmd.cmdarg = 2; 1368 err = mmc_send_cmd(mmc, &cmd, NULL); 1369 if (err) 1370 return err; 1371 1372 mmc_set_bus_width(mmc, 4); 1373 } 1374 1375 if (mmc->card_caps & MMC_MODE_HS) 1376 mmc->tran_speed = 50000000; 1377 else 1378 mmc->tran_speed = 25000000; 1379 } else if (mmc->version >= MMC_VERSION_4) { 1380 /* Only version 4 of MMC supports wider bus widths */ 1381 int idx; 1382 1383 /* An array of possible bus widths in order of preference */ 1384 static unsigned ext_csd_bits[] = { 1385 EXT_CSD_DDR_BUS_WIDTH_8, 1386 EXT_CSD_DDR_BUS_WIDTH_4, 1387 EXT_CSD_BUS_WIDTH_8, 1388 EXT_CSD_BUS_WIDTH_4, 1389 EXT_CSD_BUS_WIDTH_1, 1390 }; 1391 1392 /* An array to map CSD bus widths to host cap bits */ 1393 static unsigned ext_to_hostcaps[] = { 1394 [EXT_CSD_DDR_BUS_WIDTH_4] = 1395 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1396 [EXT_CSD_DDR_BUS_WIDTH_8] = 1397 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1398 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1399 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1400 }; 1401 1402 /* An array to map chosen bus width to an integer */ 1403 static unsigned widths[] = { 1404 8, 4, 8, 4, 1, 1405 }; 1406 1407 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1408 unsigned int extw = ext_csd_bits[idx]; 1409 unsigned int caps = ext_to_hostcaps[extw]; 1410 1411 /* 1412 * If the bus width is still not changed, 1413 * don't try to set the default again. 1414 * Otherwise, recover from switch attempts 1415 * by switching to 1-bit bus width. 1416 */ 1417 if (extw == EXT_CSD_BUS_WIDTH_1 && 1418 mmc->bus_width == 1) { 1419 err = 0; 1420 break; 1421 } 1422 1423 /* 1424 * Check to make sure the card and controller support 1425 * these capabilities 1426 */ 1427 if ((mmc->card_caps & caps) != caps) 1428 continue; 1429 1430 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1431 EXT_CSD_BUS_WIDTH, extw); 1432 1433 if (err) 1434 continue; 1435 1436 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1437 mmc_set_bus_width(mmc, widths[idx]); 1438 1439 err = mmc_send_ext_csd(mmc, test_csd); 1440 1441 if (err) 1442 continue; 1443 1444 /* Only compare read only fields */ 1445 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1446 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1447 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1448 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1449 ext_csd[EXT_CSD_REV] 1450 == test_csd[EXT_CSD_REV] && 1451 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1452 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1453 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1454 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1455 break; 1456 else 1457 err = SWITCH_ERR; 1458 } 1459 1460 if (err) 1461 return err; 1462 1463 if (mmc->card_caps & MMC_MODE_HS) { 1464 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1465 mmc->tran_speed = 52000000; 1466 else 1467 mmc->tran_speed = 26000000; 1468 } 1469 } 1470 1471 mmc_set_clock(mmc, mmc->tran_speed); 1472 1473 /* Fix the block length for DDR mode */ 1474 if (mmc->ddr_mode) { 1475 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1476 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1477 } 1478 1479 /* fill in device description */ 1480 bdesc = mmc_get_blk_desc(mmc); 1481 bdesc->lun = 0; 1482 bdesc->hwpart = 0; 1483 bdesc->type = 0; 1484 bdesc->blksz = mmc->read_bl_len; 1485 bdesc->log2blksz = LOG2(bdesc->blksz); 1486 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 1487 #if !defined(CONFIG_SPL_BUILD) || \ 1488 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1489 !defined(CONFIG_USE_TINY_PRINTF)) 1490 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 1491 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1492 (mmc->cid[3] >> 16) & 0xffff); 1493 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1494 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1495 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1496 (mmc->cid[2] >> 24) & 0xff); 1497 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1498 (mmc->cid[2] >> 16) & 0xf); 1499 #else 1500 bdesc->vendor[0] = 0; 1501 bdesc->product[0] = 0; 1502 bdesc->revision[0] = 0; 1503 #endif 1504 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1505 part_init(bdesc); 1506 #endif 1507 1508 return 0; 1509 } 1510 1511 static int mmc_send_if_cond(struct mmc *mmc) 1512 { 1513 struct mmc_cmd cmd; 1514 int err; 1515 1516 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1517 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1518 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1519 cmd.resp_type = MMC_RSP_R7; 1520 1521 err = mmc_send_cmd(mmc, &cmd, NULL); 1522 1523 if (err) 1524 return err; 1525 1526 if ((cmd.response[0] & 0xff) != 0xaa) 1527 return UNUSABLE_ERR; 1528 else 1529 mmc->version = SD_VERSION_2; 1530 1531 return 0; 1532 } 1533 1534 /* not used any more */ 1535 int __deprecated mmc_register(struct mmc *mmc) 1536 { 1537 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1538 printf("%s is deprecated! use mmc_create() instead.\n", __func__); 1539 #endif 1540 return -1; 1541 } 1542 1543 #ifdef CONFIG_BLK 1544 int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg) 1545 { 1546 struct blk_desc *bdesc; 1547 struct udevice *bdev; 1548 int ret; 1549 1550 ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512, 1551 0, &bdev); 1552 if (ret) { 1553 debug("Cannot create block device\n"); 1554 return ret; 1555 } 1556 bdesc = dev_get_uclass_platdata(bdev); 1557 mmc->cfg = cfg; 1558 mmc->priv = dev; 1559 1560 /* the following chunk was from mmc_register() */ 1561 1562 /* Setup dsr related values */ 1563 mmc->dsr_imp = 0; 1564 mmc->dsr = 0xffffffff; 1565 /* Setup the universal parts of the block interface just once */ 1566 bdesc->removable = 1; 1567 1568 /* setup initial part type */ 1569 bdesc->part_type = mmc->cfg->part_type; 1570 mmc->dev = dev; 1571 1572 return 0; 1573 } 1574 1575 int mmc_unbind(struct udevice *dev) 1576 { 1577 struct udevice *bdev; 1578 1579 device_find_first_child(dev, &bdev); 1580 if (bdev) { 1581 device_remove(bdev); 1582 device_unbind(bdev); 1583 } 1584 1585 return 0; 1586 } 1587 1588 #else 1589 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) 1590 { 1591 struct blk_desc *bdesc; 1592 struct mmc *mmc; 1593 1594 /* quick validation */ 1595 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || 1596 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) 1597 return NULL; 1598 1599 mmc = calloc(1, sizeof(*mmc)); 1600 if (mmc == NULL) 1601 return NULL; 1602 1603 mmc->cfg = cfg; 1604 mmc->priv = priv; 1605 1606 /* the following chunk was mmc_register() */ 1607 1608 /* Setup dsr related values */ 1609 mmc->dsr_imp = 0; 1610 mmc->dsr = 0xffffffff; 1611 /* Setup the universal parts of the block interface just once */ 1612 bdesc = mmc_get_blk_desc(mmc); 1613 bdesc->if_type = IF_TYPE_MMC; 1614 bdesc->removable = 1; 1615 bdesc->devnum = mmc_get_next_devnum(); 1616 bdesc->block_read = mmc_bread; 1617 bdesc->block_write = mmc_bwrite; 1618 bdesc->block_erase = mmc_berase; 1619 1620 /* setup initial part type */ 1621 bdesc->part_type = mmc->cfg->part_type; 1622 mmc_list_add(mmc); 1623 1624 return mmc; 1625 } 1626 1627 void mmc_destroy(struct mmc *mmc) 1628 { 1629 /* only freeing memory for now */ 1630 free(mmc); 1631 } 1632 #endif 1633 1634 #ifndef CONFIG_BLK 1635 static int mmc_get_dev(int dev, struct blk_desc **descp) 1636 { 1637 struct mmc *mmc = find_mmc_device(dev); 1638 int ret; 1639 1640 if (!mmc) 1641 return -ENODEV; 1642 ret = mmc_init(mmc); 1643 if (ret) 1644 return ret; 1645 1646 *descp = &mmc->block_dev; 1647 1648 return 0; 1649 } 1650 #endif 1651 1652 /* board-specific MMC power initializations. */ 1653 __weak void board_mmc_power_init(void) 1654 { 1655 } 1656 1657 int mmc_start_init(struct mmc *mmc) 1658 { 1659 int err; 1660 1661 /* we pretend there's no card when init is NULL */ 1662 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1663 mmc->has_init = 0; 1664 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1665 printf("MMC: no card present\n"); 1666 #endif 1667 return NO_CARD_ERR; 1668 } 1669 1670 if (mmc->has_init) 1671 return 0; 1672 1673 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1674 mmc_adapter_card_type_ident(); 1675 #endif 1676 board_mmc_power_init(); 1677 1678 /* made sure it's not NULL earlier */ 1679 err = mmc->cfg->ops->init(mmc); 1680 1681 if (err) 1682 return err; 1683 1684 mmc->ddr_mode = 0; 1685 mmc_set_bus_width(mmc, 1); 1686 mmc_set_clock(mmc, 1); 1687 1688 /* Reset the Card */ 1689 err = mmc_go_idle(mmc); 1690 1691 if (err) 1692 return err; 1693 1694 /* The internal partition reset to user partition(0) at every CMD0*/ 1695 mmc_get_blk_desc(mmc)->hwpart = 0; 1696 1697 /* Test for SD version 2 */ 1698 err = mmc_send_if_cond(mmc); 1699 1700 /* Now try to get the SD card's operating condition */ 1701 err = sd_send_op_cond(mmc); 1702 1703 /* If the command timed out, we check for an MMC card */ 1704 if (err == TIMEOUT) { 1705 err = mmc_send_op_cond(mmc); 1706 1707 if (err) { 1708 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1709 printf("Card did not respond to voltage select!\n"); 1710 #endif 1711 return UNUSABLE_ERR; 1712 } 1713 } 1714 1715 if (!err) 1716 mmc->init_in_progress = 1; 1717 1718 return err; 1719 } 1720 1721 static int mmc_complete_init(struct mmc *mmc) 1722 { 1723 int err = 0; 1724 1725 mmc->init_in_progress = 0; 1726 if (mmc->op_cond_pending) 1727 err = mmc_complete_op_cond(mmc); 1728 1729 if (!err) 1730 err = mmc_startup(mmc); 1731 if (err) 1732 mmc->has_init = 0; 1733 else 1734 mmc->has_init = 1; 1735 return err; 1736 } 1737 1738 int mmc_init(struct mmc *mmc) 1739 { 1740 int err = 0; 1741 unsigned start; 1742 #ifdef CONFIG_DM_MMC 1743 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 1744 1745 upriv->mmc = mmc; 1746 #endif 1747 if (mmc->has_init) 1748 return 0; 1749 1750 start = get_timer(0); 1751 1752 if (!mmc->init_in_progress) 1753 err = mmc_start_init(mmc); 1754 1755 if (!err) 1756 err = mmc_complete_init(mmc); 1757 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1758 return err; 1759 } 1760 1761 int mmc_set_dsr(struct mmc *mmc, u16 val) 1762 { 1763 mmc->dsr = val; 1764 return 0; 1765 } 1766 1767 /* CPU-specific MMC initializations */ 1768 __weak int cpu_mmc_init(bd_t *bis) 1769 { 1770 return -1; 1771 } 1772 1773 /* board-specific MMC initializations. */ 1774 __weak int board_mmc_init(bd_t *bis) 1775 { 1776 return -1; 1777 } 1778 1779 void mmc_set_preinit(struct mmc *mmc, int preinit) 1780 { 1781 mmc->preinit = preinit; 1782 } 1783 1784 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) 1785 static int mmc_probe(bd_t *bis) 1786 { 1787 return 0; 1788 } 1789 #elif defined(CONFIG_DM_MMC) 1790 static int mmc_probe(bd_t *bis) 1791 { 1792 int ret, i; 1793 struct uclass *uc; 1794 struct udevice *dev; 1795 1796 ret = uclass_get(UCLASS_MMC, &uc); 1797 if (ret) 1798 return ret; 1799 1800 /* 1801 * Try to add them in sequence order. Really with driver model we 1802 * should allow holes, but the current MMC list does not allow that. 1803 * So if we request 0, 1, 3 we will get 0, 1, 2. 1804 */ 1805 for (i = 0; ; i++) { 1806 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 1807 if (ret == -ENODEV) 1808 break; 1809 } 1810 uclass_foreach_dev(dev, uc) { 1811 ret = device_probe(dev); 1812 if (ret) 1813 printf("%s - probe failed: %d\n", dev->name, ret); 1814 } 1815 1816 return 0; 1817 } 1818 #else 1819 static int mmc_probe(bd_t *bis) 1820 { 1821 if (board_mmc_init(bis) < 0) 1822 cpu_mmc_init(bis); 1823 1824 return 0; 1825 } 1826 #endif 1827 1828 int mmc_initialize(bd_t *bis) 1829 { 1830 static int initialized = 0; 1831 int ret; 1832 if (initialized) /* Avoid initializing mmc multiple times */ 1833 return 0; 1834 initialized = 1; 1835 1836 #ifndef CONFIG_BLK 1837 mmc_list_init(); 1838 #endif 1839 ret = mmc_probe(bis); 1840 if (ret) 1841 return ret; 1842 1843 #ifndef CONFIG_SPL_BUILD 1844 print_mmc_devices(','); 1845 #endif 1846 1847 mmc_do_preinit(); 1848 return 0; 1849 } 1850 1851 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1852 /* 1853 * This function changes the size of boot partition and the size of rpmb 1854 * partition present on EMMC devices. 1855 * 1856 * Input Parameters: 1857 * struct *mmc: pointer for the mmc device strcuture 1858 * bootsize: size of boot partition 1859 * rpmbsize: size of rpmb partition 1860 * 1861 * Returns 0 on success. 1862 */ 1863 1864 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1865 unsigned long rpmbsize) 1866 { 1867 int err; 1868 struct mmc_cmd cmd; 1869 1870 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1871 cmd.cmdidx = MMC_CMD_RES_MAN; 1872 cmd.resp_type = MMC_RSP_R1b; 1873 cmd.cmdarg = MMC_CMD62_ARG1; 1874 1875 err = mmc_send_cmd(mmc, &cmd, NULL); 1876 if (err) { 1877 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1878 return err; 1879 } 1880 1881 /* Boot partition changing mode */ 1882 cmd.cmdidx = MMC_CMD_RES_MAN; 1883 cmd.resp_type = MMC_RSP_R1b; 1884 cmd.cmdarg = MMC_CMD62_ARG2; 1885 1886 err = mmc_send_cmd(mmc, &cmd, NULL); 1887 if (err) { 1888 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1889 return err; 1890 } 1891 /* boot partition size is multiple of 128KB */ 1892 bootsize = (bootsize * 1024) / 128; 1893 1894 /* Arg: boot partition size */ 1895 cmd.cmdidx = MMC_CMD_RES_MAN; 1896 cmd.resp_type = MMC_RSP_R1b; 1897 cmd.cmdarg = bootsize; 1898 1899 err = mmc_send_cmd(mmc, &cmd, NULL); 1900 if (err) { 1901 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1902 return err; 1903 } 1904 /* RPMB partition size is multiple of 128KB */ 1905 rpmbsize = (rpmbsize * 1024) / 128; 1906 /* Arg: RPMB partition size */ 1907 cmd.cmdidx = MMC_CMD_RES_MAN; 1908 cmd.resp_type = MMC_RSP_R1b; 1909 cmd.cmdarg = rpmbsize; 1910 1911 err = mmc_send_cmd(mmc, &cmd, NULL); 1912 if (err) { 1913 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1914 return err; 1915 } 1916 return 0; 1917 } 1918 1919 /* 1920 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1921 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1922 * and BOOT_MODE. 1923 * 1924 * Returns 0 on success. 1925 */ 1926 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1927 { 1928 int err; 1929 1930 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1931 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1932 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1933 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1934 1935 if (err) 1936 return err; 1937 return 0; 1938 } 1939 1940 /* 1941 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1942 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1943 * PARTITION_ACCESS. 1944 * 1945 * Returns 0 on success. 1946 */ 1947 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1948 { 1949 int err; 1950 1951 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1952 EXT_CSD_BOOT_ACK(ack) | 1953 EXT_CSD_BOOT_PART_NUM(part_num) | 1954 EXT_CSD_PARTITION_ACCESS(access)); 1955 1956 if (err) 1957 return err; 1958 return 0; 1959 } 1960 1961 /* 1962 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1963 * for enable. Note that this is a write-once field for non-zero values. 1964 * 1965 * Returns 0 on success. 1966 */ 1967 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1968 { 1969 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1970 enable); 1971 } 1972 #endif 1973 1974 #ifdef CONFIG_BLK 1975 static const struct blk_ops mmc_blk_ops = { 1976 .read = mmc_bread, 1977 .write = mmc_bwrite, 1978 .select_hwpart = mmc_select_hwpart, 1979 }; 1980 1981 U_BOOT_DRIVER(mmc_blk) = { 1982 .name = "mmc_blk", 1983 .id = UCLASS_BLK, 1984 .ops = &mmc_blk_ops, 1985 }; 1986 #else 1987 U_BOOT_LEGACY_BLK(mmc) = { 1988 .if_typename = "mmc", 1989 .if_type = IF_TYPE_MMC, 1990 .max_devs = -1, 1991 .get_dev = mmc_get_dev, 1992 .select_hwpart = mmc_select_hwpartp, 1993 }; 1994 #endif 1995