1 /* 2 * (C) Copyright 2016 Carlo Caione <carlo@caione.org> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <malloc.h> 11 #include <mmc.h> 12 #include <asm/io.h> 13 #include <asm/arch/sd_emmc.h> 14 #include <linux/log2.h> 15 16 static inline void *get_regbase(const struct mmc *mmc) 17 { 18 struct meson_mmc_platdata *pdata = mmc->priv; 19 20 return pdata->regbase; 21 } 22 23 static inline uint32_t meson_read(struct mmc *mmc, int offset) 24 { 25 return readl(get_regbase(mmc) + offset); 26 } 27 28 static inline void meson_write(struct mmc *mmc, uint32_t val, int offset) 29 { 30 writel(val, get_regbase(mmc) + offset); 31 } 32 33 static void meson_mmc_config_clock(struct mmc *mmc) 34 { 35 uint32_t meson_mmc_clk = 0; 36 unsigned int clk, clk_src, clk_div; 37 38 /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ 39 if (mmc->clock > 16000000) { 40 clk = SD_EMMC_CLKSRC_DIV2; 41 clk_src = CLK_SRC_DIV2; 42 } else { 43 clk = SD_EMMC_CLKSRC_24M; 44 clk_src = CLK_SRC_24M; 45 } 46 clk_div = DIV_ROUND_UP(clk, mmc->clock); 47 48 /* 180 phase core clock */ 49 meson_mmc_clk |= CLK_CO_PHASE_180; 50 51 /* 180 phase tx clock */ 52 meson_mmc_clk |= CLK_TX_PHASE_000; 53 54 /* clock settings */ 55 meson_mmc_clk |= clk_src; 56 meson_mmc_clk |= clk_div; 57 58 meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK); 59 } 60 61 static int meson_dm_mmc_set_ios(struct udevice *dev) 62 { 63 struct mmc *mmc = mmc_get_mmc_dev(dev); 64 uint32_t meson_mmc_cfg; 65 66 meson_mmc_config_clock(mmc); 67 68 meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG); 69 70 meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK; 71 if (mmc->bus_width == 1) 72 meson_mmc_cfg |= CFG_BUS_WIDTH_1; 73 else if (mmc->bus_width == 4) 74 meson_mmc_cfg |= CFG_BUS_WIDTH_4; 75 else if (mmc->bus_width == 8) 76 meson_mmc_cfg |= CFG_BUS_WIDTH_8; 77 else 78 return -EINVAL; 79 80 /* 512 bytes block length */ 81 meson_mmc_cfg &= ~CFG_BL_LEN_MASK; 82 meson_mmc_cfg |= CFG_BL_LEN_512; 83 84 /* Response timeout 256 clk */ 85 meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK; 86 meson_mmc_cfg |= CFG_RESP_TIMEOUT_256; 87 88 /* Command-command gap 16 clk */ 89 meson_mmc_cfg &= ~CFG_RC_CC_MASK; 90 meson_mmc_cfg |= CFG_RC_CC_16; 91 92 meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG); 93 94 return 0; 95 } 96 97 static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data, 98 struct mmc_cmd *cmd) 99 { 100 uint32_t meson_mmc_cmd = 0, cfg; 101 102 meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT; 103 104 if (cmd->resp_type & MMC_RSP_PRESENT) { 105 if (cmd->resp_type & MMC_RSP_136) 106 meson_mmc_cmd |= CMD_CFG_RESP_128; 107 108 if (cmd->resp_type & MMC_RSP_BUSY) 109 meson_mmc_cmd |= CMD_CFG_R1B; 110 111 if (!(cmd->resp_type & MMC_RSP_CRC)) 112 meson_mmc_cmd |= CMD_CFG_RESP_NOCRC; 113 } else { 114 meson_mmc_cmd |= CMD_CFG_NO_RESP; 115 } 116 117 if (data) { 118 cfg = meson_read(mmc, MESON_SD_EMMC_CFG); 119 cfg &= ~CFG_BL_LEN_MASK; 120 cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT; 121 meson_write(mmc, cfg, MESON_SD_EMMC_CFG); 122 123 if (data->flags == MMC_DATA_WRITE) 124 meson_mmc_cmd |= CMD_CFG_DATA_WR; 125 126 meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE | 127 data->blocks; 128 } 129 130 meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER | 131 CMD_CFG_END_OF_CHAIN; 132 133 meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG); 134 } 135 136 static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data) 137 { 138 struct meson_mmc_platdata *pdata = mmc->priv; 139 unsigned int data_size; 140 uint32_t data_addr = 0; 141 142 if (data) { 143 data_size = data->blocks * data->blocksize; 144 145 if (data->flags == MMC_DATA_READ) { 146 data_addr = (ulong) data->dest; 147 invalidate_dcache_range(data_addr, 148 data_addr + data_size); 149 } else { 150 pdata->w_buf = calloc(data_size, sizeof(char)); 151 data_addr = (ulong) pdata->w_buf; 152 memcpy(pdata->w_buf, data->src, data_size); 153 flush_dcache_range(data_addr, data_addr + data_size); 154 } 155 } 156 157 meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT); 158 } 159 160 static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd) 161 { 162 if (cmd->resp_type & MMC_RSP_136) { 163 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3); 164 cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2); 165 cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1); 166 cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP); 167 } else { 168 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP); 169 } 170 } 171 172 static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 173 struct mmc_data *data) 174 { 175 struct mmc *mmc = mmc_get_mmc_dev(dev); 176 struct meson_mmc_platdata *pdata = mmc->priv; 177 uint32_t status; 178 ulong start; 179 int ret = 0; 180 181 /* max block size supported by chip is 512 byte */ 182 if (data && data->blocksize > 512) 183 return -EINVAL; 184 185 meson_mmc_setup_cmd(mmc, data, cmd); 186 meson_mmc_setup_addr(mmc, data); 187 188 meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG); 189 190 /* use 10s timeout */ 191 start = get_timer(0); 192 do { 193 status = meson_read(mmc, MESON_SD_EMMC_STATUS); 194 } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000); 195 196 if (!(status & STATUS_END_OF_CHAIN)) 197 ret = -ETIMEDOUT; 198 else if (status & STATUS_RESP_TIMEOUT) 199 ret = -ETIMEDOUT; 200 else if (status & STATUS_ERR_MASK) 201 ret = -EIO; 202 203 meson_mmc_read_response(mmc, cmd); 204 205 if (data && data->flags == MMC_DATA_WRITE) 206 free(pdata->w_buf); 207 208 /* reset status bits */ 209 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); 210 211 return ret; 212 } 213 214 static const struct dm_mmc_ops meson_dm_mmc_ops = { 215 .send_cmd = meson_dm_mmc_send_cmd, 216 .set_ios = meson_dm_mmc_set_ios, 217 }; 218 219 static int meson_mmc_ofdata_to_platdata(struct udevice *dev) 220 { 221 struct meson_mmc_platdata *pdata = dev_get_platdata(dev); 222 fdt_addr_t addr; 223 224 addr = devfdt_get_addr(dev); 225 if (addr == FDT_ADDR_T_NONE) 226 return -EINVAL; 227 228 pdata->regbase = (void *)addr; 229 230 return 0; 231 } 232 233 static int meson_mmc_probe(struct udevice *dev) 234 { 235 struct meson_mmc_platdata *pdata = dev_get_platdata(dev); 236 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 237 struct mmc *mmc = &pdata->mmc; 238 struct mmc_config *cfg = &pdata->cfg; 239 uint32_t val; 240 241 cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | 242 MMC_VDD_31_32 | MMC_VDD_165_195; 243 cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | 244 MMC_MODE_HS_52MHz | MMC_MODE_HS; 245 cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); 246 cfg->f_max = 100000000; /* 100 MHz */ 247 cfg->b_max = 511; /* max 512 - 1 blocks */ 248 cfg->name = dev->name; 249 250 mmc->priv = pdata; 251 upriv->mmc = mmc; 252 253 mmc_set_clock(mmc, cfg->f_min); 254 255 /* reset all status bits */ 256 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); 257 258 /* disable interrupts */ 259 meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN); 260 261 /* enable auto clock mode */ 262 val = meson_read(mmc, MESON_SD_EMMC_CFG); 263 val &= ~CFG_SDCLK_ALWAYS_ON; 264 val |= CFG_AUTO_CLK; 265 meson_write(mmc, val, MESON_SD_EMMC_CFG); 266 267 return 0; 268 } 269 270 int meson_mmc_bind(struct udevice *dev) 271 { 272 struct meson_mmc_platdata *pdata = dev_get_platdata(dev); 273 274 return mmc_bind(dev, &pdata->mmc, &pdata->cfg); 275 } 276 277 static const struct udevice_id meson_mmc_match[] = { 278 { .compatible = "amlogic,meson-gx-mmc" }, 279 { /* sentinel */ } 280 }; 281 282 U_BOOT_DRIVER(meson_mmc) = { 283 .name = "meson_gx_mmc", 284 .id = UCLASS_MMC, 285 .of_match = meson_mmc_match, 286 .ops = &meson_dm_mmc_ops, 287 .probe = meson_mmc_probe, 288 .bind = meson_mmc_bind, 289 .ofdata_to_platdata = meson_mmc_ofdata_to_platdata, 290 .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata), 291 }; 292